* [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader
@ 2011-01-28 4:58 Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
` (4 more replies)
0 siblings, 5 replies; 22+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-28 4:58 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code needs to be limitated to 4K byte, then tpl code will load the
final uboot image after ddr is initialized.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v3: remove TPL_BOOT, use HAS_TPL and IN_TPL
Makefile | 15 ++++++++++++++-
README | 27 +++++++++++++++++++++++++++
2 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 0d1ea5d..ae5db69 100644
--- a/Makefile
+++ b/Makefile
@@ -402,8 +402,19 @@ $(obj)u-boot.lds: $(LDSCRIPT)
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+tpl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin
+NAND_SPL_OBJS-$(CONFIG_HAS_TPL) += $(obj)tpl/u-boot-tpl.bin
+NAND_SPL_OBJS-y += $(obj)u-boot.bin
+
+ifeq ($(CONFIG_HAS_TPL),y)
+$(obj)u-boot-nand.bin: nand_spl tpl $(obj)u-boot.bin
+else
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+endif
+ cat $(NAND_SPL_OBJS-y) > $(obj)u-boot-nand.bin
onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1221,6 +1232,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1245,6 +1257,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name "*" -type l -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 755d17c..a37fdb1 100644
--- a/README
+++ b/README
@@ -2124,6 +2124,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_HAS_TPL
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_IN_TPL
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--------------
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support
2011-01-28 4:58 [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
@ 2011-01-28 4:58 ` Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Haiying.Wang at freescale.com
` (3 subsequent siblings)
4 siblings, 0 replies; 22+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-28 4:58 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v3: Use HAS_TPL and IN_TPL, change initdram for TPL, fix the inconsistent
comments.
arch/powerpc/cpu/mpc85xx/cpu.c | 7 ++
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 22 ++++++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++++++++++++++++++++++++++++++
4 files changed, 132 insertions(+), 8 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..e923547 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -296,6 +296,12 @@ void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
phys_size_t initdram(int board_type)
{
+#if defined(CONFIG_HAS_TPL) && !defined(CONFIG_IN_TPL)
+ /* ddr has been initialized in tpl boot stage thus we only need
+ * to get the ddr dram size for the final uboot.
+ */
+ return fsl_ddr_sdram_size();
+#else
phys_size_t dram_size = 0;
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
@@ -342,6 +348,7 @@ phys_size_t initdram(int board_type)
puts("DDR: ");
return dram_size;
+#endif /* CONFIG_HAS_TPL */
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..65c32d9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009 - 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,6 +23,8 @@
#include <common.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void cpu_init_f(void)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
@@ -40,7 +42,8 @@ void cpu_init_f(void)
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) \
+ && !defined(CONFIG_IN_TPL)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
@@ -60,4 +63,19 @@ void cpu_init_f(void)
for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
+#ifdef CONFIG_IN_TPL
+ init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_IN_TPL
+/*
+ * Because the primary cpu's info is enough for the 2nd stage, we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+ return 1;
}
+#endif /* CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index fa98af6..5496fc4 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL*/
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -435,7 +435,7 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -877,7 +877,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
/*------------------------------------------------------------------------------*/
@@ -1067,7 +1067,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
/*
* Copy exception vector code to low memory
*
@@ -1207,4 +1207,4 @@ setup_ivors:
#include "fixed_ivor.S"
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
new file mode 100644
index 0000000..d8ff62b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .text :
+ {
+ *(.text*)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ KEEP(*(.got))
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ start.o KEEP(*(.bootpg))
+ } :text = 0xffff
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 4:58 [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
@ 2011-01-28 4:58 ` Haiying.Wang at freescale.com
2011-01-28 14:49 ` Kumar Gala
2011-01-28 19:06 ` Timur Tabi
2011-01-28 4:58 ` [U-Boot] [PATCH 8/8 v3] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
` (2 subsequent siblings)
4 siblings, 2 replies; 22+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-28 4:58 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there are three stage uboot
images:
* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND.
* tpl_boot, 112KB size. The env variables are copied to offset 128KB
in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env.
It loads final uboot image from offset 128KB in NAND.
* final uboot image, size is variable depends on the functions enabled.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Mohit Kumar <Mohit.Kumar@freescale.com>
Signed-off-by: Yu Liu <Yu.Liu@freescale.com>
Signed-off-by: Kai Jiang <Kai.Jiang@freescale.com>
---
v3: use CONFIG_HAS_TPL and CONFIG_IN_TPL, update copyright year, remove pci.c,
incoperate with the changes in upstream.
MAINTAINERS | 4 +
board/freescale/p1021mds/Makefile | 52 +++
board/freescale/p1021mds/config.mk | 31 ++
board/freescale/p1021mds/ddr.c | 107 +++++
board/freescale/p1021mds/law.c | 38 ++
board/freescale/p1021mds/p1021mds.c | 133 ++++++
board/freescale/p1021mds/tlb.c | 102 +++++
boards.cfg | 1 +
include/configs/P1021MDS.h | 571 +++++++++++++++++++++++++
nand_spl/board/freescale/p1021mds/Makefile | 134 ++++++
nand_spl/board/freescale/p1021mds/nand_boot.c | 69 +++
nand_spl/nand_boot_fsl_elbc.c | 6 +-
tpl/board/freescale/p1021mds/Makefile | 256 +++++++++++
tpl/board/freescale/p1021mds/tpl_boot.c | 79 ++++
14 files changed, 1582 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/p1021mds/Makefile
create mode 100644 board/freescale/p1021mds/config.mk
create mode 100644 board/freescale/p1021mds/ddr.c
create mode 100644 board/freescale/p1021mds/law.c
create mode 100644 board/freescale/p1021mds/p1021mds.c
create mode 100644 board/freescale/p1021mds/tlb.c
create mode 100644 include/configs/P1021MDS.h
create mode 100644 nand_spl/board/freescale/p1021mds/Makefile
create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c
create mode 100644 tpl/board/freescale/p1021mds/Makefile
create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c
diff --git a/MAINTAINERS b/MAINTAINERS
index edd1c5c..da1b2a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17,6 +17,10 @@
# Board CPU #
#########################################################################
+Haiying Wang <Haiying.Wang@freescale.com>
+
+ P1021MDS P1021
+
Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2020RDB P2020
diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..50d4743
--- /dev/null
+++ b/board/freescale/p1021mds/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-y += ddr.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
new file mode 100644
index 0000000..3888f61
--- /dev/null
+++ b/board/freescale/p1021mds/config.mk
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# p1021mds board
+#
+
+ifndef NAND_SPL
+ifndef IN_TPL
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
+endif
diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
new file mode 100644
index 0000000..594a4a8
--- /dev/null
+++ b/board/freescale/p1021mds/ddr.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+ int ret;
+
+ /*
+ * The P1021 only has one DDR controller, and the P1021MDS board has
+ * only one DIMM slot.
+ */
+
+ ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
+ sizeof(ddr3_spd_eeprom_t));
+
+ if (ret) {
+ debug("DDR: failed to read SPD from address %u\n",
+ SPD_EEPROM_ADDRESS1);
+ memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ */
+ popts->cpo_override = 0x1f;
+
+ /*
+ * Factors to consider for write data delay:
+ */
+ popts->write_data_delay = 2;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ */
+ popts->half_strength_driver_enable = 1;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_40_OHM; /* 40 Ohm rtt */
+ popts->rtt_wr_override_value = 2; /* Rtt_WR */
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x8;
+ /*
+ * P1021 supports max 32-bit DDR width
+ */
+ popts->data_bus_width = 1;
+
+ /*
+ * disable on-the-fly burst chop mode for 32 bit data bus
+ */
+ popts->OTF_burst_chop_en = 0;
+
+ /*
+ * Set fixed 8 beat burst for 32 bit data bus
+ */
+ popts->burst_length = DDR_BL8;
+}
diff --git a/board/freescale/p1021mds/law.c b/board/freescale/p1021mds/law.c
new file mode 100644
index 0000000..d0be19e
--- /dev/null
+++ b/board/freescale/p1021mds/law.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_IN_TPL
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC),
+#endif /* !CONFIG_IN_TPL */
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
new file mode 100644
index 0000000..c7a7e57
--- /dev/null
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/mp.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <tsec.h>
+#include <netdev.h>
+
+int board_early_init_f(void)
+{
+
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+#ifdef CONFIG_MMC
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+#endif
+
+ /* Set ABSWP to implement conversion of addresses in the LBC */
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: P1021 MDS\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct tsec_info_struct tsec_info[3];
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII3_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, base, size);
+
+ FT_FSL_PCI_SETUP;
+
+}
+#endif
+;
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
new file mode 100644
index 0000000..30af6dd
--- /dev/null
+++ b/board/freescale/p1021mds/tlb.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_IN_TPL
+ /* *I*G* - PCIE */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIE I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /*
+ * *I*G BCSR/PMC0/PMC1
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+#endif /* !CONFIG_IN_TPL */
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_IN_TPL)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index eceacf6..0787a9a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -483,6 +483,7 @@ P1020RDB powerpc mpc85xx p1_p2_rdb freesca
P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH
+P1021MDS_NAND powerpc mpc85xx p1021mds freescale - P1021MDS:NAND
P1022DS powerpc mpc85xx p1022ds freescale
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h
new file mode 100644
index 0000000..6ada509
--- /dev/null
+++ b/include/configs/P1021MDS.h
@@ -0,0 +1,571 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * p1021mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HAS_TPL
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_RAMBOOT_NAND
+#endif
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#ifdef CONFIG_HAS_TPL
+#define CONFIG_SYS_TEXT_BASE_TPL 0xf8f81000
+#endif
+#define CONFIG_SYS_TEXT_BASE 0x01001000
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#elif CONFIG_IN_TPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_TPL /* start of monitor */
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/68/P1021 */
+#define CONFIG_P1021 /* P1021 silicon support */
+#define CONFIG_P1021MDS /* P1021MDS board specific */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_FSL_ELBC /* Has Enhance localbus controller */
+
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_HWCONFIG
+
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+
+#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
+ addresses in the LBC */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
+ /* physical addr of CCSRBAR */
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#endif
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+ /* PQII uses CONFIG_SYS_IMMR */
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_TLB_START 11
+
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+ /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
+#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL 0x86559608
+#define CONFIG_SYS_DDR_CDR_1 0x000eaa00
+#define CONFIG_SYS_DDR_CDR_2 0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0x470c0000 /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
+#define CONFIG_SYS_DDR_DATA_INIT 0x1021babe
+#define CONFIG_SYS_DDR_TIMING_3 0x00010000
+#define CONFIG_SYS_DDR_TIMING_0 0x00330004
+#define CONFIG_SYS_DDR_TIMING_1 0x5d5bd746
+#define CONFIG_SYS_DDR_TIMING_2 0x0fa8c8cd
+#define CONFIG_SYS_DDR_SDRAM_MODE 0x40461320
+#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x0a280000
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
+#define CONFIG_SYS_DDR_TIMING_4 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+
+#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
+#define CONFIG_SYS_DDR_SBE 0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR3 512MB cacheable
+ * 0xa000_0000 0xbfff_ffff PCIE2 Mem 512MB non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCIE1 Mem 512MB non-cacheable
+ * 0xffc1_0000 0xffc1_ffff PCIE2 IO range 64K non-cacheable
+ * 0xffc2_0000 0xffc2_ffff PCIE1 IO range 64K non-cacheable
+ * 0xf800_0000 0xf800_7fff BCSR on CS1 32KB non-cacheable
+ * 0xf801_0000 0xf801_ffff PMC1 on CS2 64KB non-cacheable
+ * 0xf802_0000 0xf802_ffff PMC0 on CS3 64KB non-cacheable
+ * 0xfc00_0000 0xfdff_ffff NAND on CS0 32MB non-cacheable
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_BCSR_BASE 0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
+
+#define CONFIG_SYS_PIB_PMC1_BASE 0xf8010000
+ /* start of PIB-QOC3(PMC1) 64K */
+#define CONFIG_SYS_PIB_PMC1_BASE_PHYS CONFIG_SYS_PIB_PMC1_BASE
+
+#define CONFIG_SYS_PIB_PMC0_BASE 0xf8020000
+ /* start of PIB-T1/E1(PMC0) 64K */
+#define CONFIG_SYS_PIB_PMC0_BASE_PHYS CONFIG_SYS_PIB_PMC0_BASE
+
+/* chip select 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+/* chip select 2 - PIB(QOC3-PMC1)*/
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC1_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+/* chip select 3 - PIB(T1/E1-PMC0)*/
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC0_BASE_PHYS) \
+ | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+ | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) \
+ || defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE 0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#endif
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (112 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#ifdef CONFIG_IN_TPL
+/* tpl boot: 112K tpl uboot config*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+
+/* NAND FLASH CONFIG */
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+/* chip select 0 - NAND */
+#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (576 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (128 << 10))
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot Argument Buffer Size */
+
+/*********************************/
+#ifndef CONFIG_IN_TPL
+
+#define CONFIG_MP /* Multiprocessor support */
+
+#define CONFIG_PCI /* Disable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller */
+#define CONFIG_PCIE2 /* PCIE controller */
+#define CONFIG_FSL_PCI_INIT /* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* TSEC support */
+#if defined(CONFIG_TSEC_ENET)
+
+/* TSECV2 */
+#define CONFIG_TSECV2
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX 0
+
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_SGMII)
+#define TSEC2_PHYIDX 0
+
+#ifdef CONFIG_TSEC3_IN_SGMII /* Need to set SW8.6 to 0 */
+#define TSEC3_PHY_ADDR 6
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_SGMII)
+#else
+#define TSEC3_PHY_ADDR 1
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#endif
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+
+#define PLPPAR1_I2C_BIT_MASK 0x0000000F
+#define PLPPAR1_I2C2_VAL 0x00000000
+#define PLPPAR1_ESDHC_VAL 0x0000000A
+#define PLPDIR1_I2C_BIT_MASK 0x0000000F
+#define PLPDIR1_I2C2_VAL 0x0000000F
+#define PLPDIR1_ESDHC_VAL 0x00000006
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64K */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
+ /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME p1021mds
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=your.fdt.dtb\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "run nfsargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "run ramargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* !CONFIG_IN_TPL */
+#endif /* __CONFIG_H */
diff --git a/nand_spl/board/freescale/p1021mds/Makefile b/nand_spl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..5e0fa1d
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,134 @@
+#
+# Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+PAD_TO := 0xfff04000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
+ $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o resetvec.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c \
+ $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c \
+ $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+ @rm -f $(obj)nand_boot_fsl_elbc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+ $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S \
+ $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c \
+ $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1021mds/nand_boot.c b/nand_spl/board/freescale/p1021mds/nand_boot.c
new file mode 100644
index 0000000..73a66fa
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/nand_boot.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ uint plat_ratio, bus_clk, sys_clk = 0;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ sys_clk = CONFIG_SYS_CLK_FREQ;
+
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = plat_ratio * sys_clk;
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+ /* copy code to DDR and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 9547d44..8b135bc 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -4,7 +4,7 @@
* (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr at denx.de.
*
- * Copyright (c) 2008 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or
@@ -47,7 +47,11 @@ static void nand_wait(void)
}
}
+#ifdef CONFIG_IN_TPL
+void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#else
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
diff --git a/tpl/board/freescale/p1021mds/Makefile b/tpl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..e6c18ad
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,256 @@
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+IN_TPL := y
+PAD_TO := 0xf8f9c000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-tpl.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_TPL) \
+ $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_IN_TPL
+CFLAGS += -DCONFIG_IN_TPL
+
+SOBJS = start.o ticks.o ppcstring.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o speed.o \
+ tpl_boot.o tlb.o tlb_table.o ddr-gen3.o time.o ddr.o cpu.o fsl_lbc.o \
+ string.o hwconfig.o time_lib.o ddr_spd.o ctype.o div64.o crc32.o\
+ console.o cmd_nvedit.o env_common.o env_nand.o vsprintf.o \
+ display_options.o hashtable.o dlmalloc.o stdio.o ns16550.o serial.o \
+ errno.o command.o serial_driver.o qsort.o
+
+ifdef CONFIG_RAMBOOT_NAND
+COBJS += nand_boot_fsl_elbc.o
+endif
+
+LIBS = $(OBJTREE)/arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS += $(OBJTREE)/drivers/i2c/libi2c.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+__LIBS := $(addprefix $(obj), $(LIBS))
+LNDIR := $(OBJTREE)/tpl/board/$(BOARDDIR)
+
+tplobj := $(OBJTREE)/tpl/
+
+ALL = $(tplobj)u-boot-tpl $(tplobj)u-boot-tpl.bin
+
+all: $(obj).depend $(ALL)
+
+$(tplobj)u-boot-tpl.bin: $(tplobj)u-boot-tpl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(tplobj)u-boot-tpl: $(OBJS) $(LIBS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(__LIBS) $(PLATFORM_LIBS) \
+ -Map $(tplobj)u-boot-tpl.map \
+ -o $(tplobj)u-boot-tpl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)fsl_lbc.c:
+ @rm -f $(obj)fsl_lbc.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c $(obj)fsl_lbc.c
+
+$(obj)cpu.c:
+ @rm -f $(obj)cpu.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu.c $(obj)cpu.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+ @rm -f $(obj)nand_boot_fsl_elbc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+ $(obj)nand_boot_fsl_elbc.c
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)speed.c:
+ @rm -f $(obj)speed.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/speed.c $(obj)speed.c
+
+$(obj)interrupts.c:
+ @rm -f $(obj)interrupts.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/interrupts.c $(obj)interrupts.c
+
+$(obj)ticks.S:
+ @rm -f $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+
+$(obj)bootm.c:
+ @rm -f $(obj)bootm.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/bootm.c $(obj)bootm.c
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+$(obj)ddr.c:
+ @rm -f $(obj)ddr.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/ddr.c $(obj)ddr.c
+
+$(obj)time.c:
+ @rm -f $(obj)time.o
+ ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
+
+$(obj)ddr-gen3.c:
+ @rm -f $(obj)ddr-gen3.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/ddr-gen3.c $(obj)ddr-gen3.c
+
+$(obj)ppcstring.S:
+ @rm -f $(obj)ppcstring.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ppcstring.S $(obj)ppcstring.S
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)serial_driver.c:
+ @rm -f $(obj)serial_driver.c
+ ln -sf $(SRCTREE)/drivers/serial/serial.c $(obj)serial_driver.c
+
+$(obj)time_lib.c:
+ @rm -f $(obj)time_lib.o
+ ln -sf $(SRCTREE)/lib/time.c $(obj)time_lib.c
+
+$(obj)ddr_spd.c:
+ @rm -f $(obj)ddr_spd.c
+ ln -sf $(SRCTREE)/common/ddr_spd.c $(obj)ddr_spd.c
+
+$(obj)ctype.c:
+ @rm -f $(obj)ctype.c
+ ln -sf $(SRCTREE)/lib/ctype.c $(obj)ctype.c
+
+$(obj)div64.c:
+ @rm -f $(obj)div64.c
+ ln -sf $(SRCTREE)/lib/div64.c $(obj)div64.c
+
+$(obj)crc32.c:
+ @rm -f $(obj)crc32.c
+ ln -sf $(SRCTREE)/lib/crc32.c $(obj)crc32.c
+
+$(obj)env_common.c:
+ @rm -f $(obj)env_common.c
+ ln -sf $(SRCTREE)/common/env_common.c $(obj)env_common.c
+
+$(obj)env_nand.c:
+ @rm -f $(obj)env_nand.c
+ ln -sf $(SRCTREE)/common/env_nand.c $(obj)env_nand.c
+
+$(obj)cmd_nvedit.c:
+ @rm -f $(obj)cmd_nvedit.c
+ ln -sf $(SRCTREE)/common/cmd_nvedit.c $(obj)cmd_nvedit.c
+
+$(obj)console.c:
+ @rm -f $(obj)console.c
+ ln -sf $(SRCTREE)/common/console.c $(obj)console.c
+
+$(obj)dlmalloc.c:
+ @rm -f $(obj)dlmalloc.c
+ ln -sf $(SRCTREE)/common/dlmalloc.c $(obj)dlmalloc.c
+
+$(obj)hwconfig.c:
+ @rm -f $(obj)hwconfig.c
+ ln -sf $(SRCTREE)/common/hwconfig.c $(obj)hwconfig.c
+
+$(obj)stdio.c:
+ @rm -f $(obj)stdio.c
+ ln -sf $(SRCTREE)/common/stdio.c $(obj)stdio.c
+
+$(obj)string.c:
+ @rm -f $(obj)string.c
+ ln -sf $(SRCTREE)/lib/string.c $(obj)string.c
+
+$(obj)vsprintf.c:
+ @rm -f $(obj)vsprintf.c
+ ln -sf $(SRCTREE)/lib/vsprintf.c $(obj)vsprintf.c
+
+$(obj)display_options.c:
+ @rm -f $(obj)display_options.c
+ ln -sf $(SRCTREE)/lib/display_options.c $(obj)display_options.c
+
+$(obj)hashtable.c:
+ @rm -f $(obj)hashtable.c
+ ln -sf $(SRCTREE)/lib/hashtable.c $(obj)hashtable.c
+
+$(obj)serial.c:
+ @rm -f $(obj)serial.c
+ ln -sf $(SRCTREE)/common/serial.c $(obj)serial.c
+
+$(obj)command.c:
+ @rm -f $(obj)command.c
+ ln -sf $(SRCTREE)/common/command.c $(obj)command.c
+
+$(obj)errno.c:
+ @rm -f $(obj)errno.c
+ ln -sf $(SRCTREE)/lib/errno.c $(obj)errno.c
+
+$(obj)qsort.c:
+ @rm -f $(obj)qsort.c
+ ln -sf $(SRCTREE)/lib/qsort.c $(obj)qsort.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)tpl_boot.c:
+ @rm -f $(obj)tpl_boot.c
+ ln -s $(SRCTREE)/tpl/freescale/tpl_boot.c $(obj)tpl_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/tpl/board/freescale/p1021mds/tpl_boot.c b/tpl/board/freescale/p1021mds/tpl_boot.c
new file mode 100644
index 0000000..386d76c
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/tpl_boot.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void nand_load(unsigned int offs, int uboot_size, uchar *dst);
+extern phys_size_t init_ddr_dram(void);
+
+void board_init_f(ulong bootflag)
+{
+ uint plat_ratio, bus_clk, sys_clk = 0;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ sys_clk = CONFIG_SYS_CLK_FREQ;
+
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = plat_ratio * sys_clk;
+ get_clocks();
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* load environment */
+#ifdef CONFIG_NAND_U_BOOT
+ nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ /* board specific DDR initialization */
+ gd->ram_size = initdram(0);
+ puts("DRAM:");
+ print_size(gd->ram_size, "");
+
+ puts("\nThird program loader running in sram... ");
+
+ /*
+ * Load final image to DDR and let it run from there.
+ */
+#ifdef CONFIG_NAND_U_BOOT
+ nand_boot();
+#endif
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+}
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 8/8 v3] p1021mds: add QE and UEC support
2011-01-28 4:58 [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Haiying.Wang at freescale.com
@ 2011-01-28 4:58 ` Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 7/7] add gc-sections to TPL boot Haiying.Wang at freescale.com
[not found] ` <1296190690-21146-3-git-send-email-Haiying.Wang@freescale.c om>
4 siblings, 0 replies; 22+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-28 4:58 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v3: make changes in p1021mds.c and P1021MDS.h according to the changes in patch
5/8, update the copyright years.
arch/powerpc/cpu/mpc85xx/speed.c | 4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +++++
board/freescale/p1021mds/p1021mds.c | 83 +++++++++++++++++++++++++++++++++
drivers/qe/uec.c | 40 +++++++++++++++-
include/configs/P1021MDS.h | 47 ++++++++++++++++++
5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo->freqQE = sysInfo->freqSystemBus;
+#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 77e3629..9b7de6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
+#define MPC85xx_PMUXCR_QE0 0x00008000
+#define MPC85xx_PMUXCR_QE1 0x00004000
+#define MPC85xx_PMUXCR_QE2 0x00002000
+#define MPC85xx_PMUXCR_QE3 0x00001000
+#define MPC85xx_PMUXCR_QE4 0x00000800
+#define MPC85xx_PMUXCR_QE5 0x00000400
+#define MPC85xx_PMUXCR_QE6 0x00000200
+#define MPC85xx_PMUXCR_QE7 0x00000100
+#define MPC85xx_PMUXCR_QE8 0x00000080
+#define MPC85xx_PMUXCR_QE9 0x00000040
+#define MPC85xx_PMUXCR_QE10 0x00000020
+#define MPC85xx_PMUXCR_QE11 0x00000010
+#define MPC85xx_PMUXCR_QE12 0x00000008
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr; /* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
index c7a7e57..e1ee1cf 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include <tsec.h>
#include <netdev.h>
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include <nand.h>
+#include <asm/errno.h>
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+ {0, 17, 2, 0, 2}, /* ENET1_CRS */
+ {0, 16, 2, 0, 2}, /* ENET1_COL */
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +148,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
+
+ uec_standard_init(bis);
+#endif
+
return pci_eth_init(bis);
}
#endif
@@ -120,6 +176,10 @@ void ft_board_setup(void *blob, bd_t *bd)
FT_FSL_PCI_SETUP;
+#ifdef CONFIG_QE
+ do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+ sizeof("okay"), 0);
+#endif
}
#endif
;
@@ -131,3 +191,26 @@ void board_lmb_reserve(struct lmb *lmb)
cpu_mp_lmb_reserve(lmb);
}
#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r()
+{
+#if defined(CONFIG_QE) && defined(CONFIG_SYS_QE_FW_LENGTH)
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret && ret == -EUCLEAN) {
+ printf ("NAND read for QE firmware at offset %x failed %d\n",
+ CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+
+ qe_init(CONFIG_SYS_IMMR + 0x00080000);
+ qe_reset();
+#endif
+ return 0;
+}
+#endif
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 282ab23..04d7987 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -30,6 +30,9 @@
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#ifdef CONFIG_P1021
+#define BCSR11_ENET_MICRST 0x20
+#endif
/* Default UTBIPAR SMI address */
#ifndef CONFIG_UTBIPAR_INIT_TBIPA
@@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
+#ifdef CONFIG_P1021
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
+#ifdef CONFIG_P1021
+ /*
+ * QE12 is muxed with LBCTL, it needs to be released for enabling
+ * LBCTL signal for LBC usage.
+ */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Adjust the interface according to speed */
adjust_link(dev);
}
@@ -1198,10 +1217,24 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
+#ifdef CONFIG_P1021
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
@@ -1228,6 +1261,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
+#ifdef CONFIG_P1021
+ /* QE12 needs to be released for enabling LBCTL signal*/
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h
index 0496cd3..65226eb 100644
--- a/include/configs/P1021MDS.h
+++ b/include/configs/P1021MDS.h
@@ -414,6 +414,50 @@
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
+#define CONFIG_QE
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
+#define CONFIG_SYS_QE_FW_ADDR 0x10000000
+#define CONFIG_SYS_QE_FW_LENGTH 0x10000
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
+
+#define CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5 /* GETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH2 */
+
+#endif /* CONFIG_QE */
+
/*
* I2C2 EEPROM
*/
@@ -458,6 +502,8 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#endif
+#define CONFIG_E1000
+
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
@@ -491,6 +537,7 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+#define CONFIG_MISC_INIT_R /* Call misc_init_r */
#define CONFIG_MMC
#ifdef CONFIG_MMC
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 4:58 [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
` (2 preceding siblings ...)
2011-01-28 4:58 ` [U-Boot] [PATCH 8/8 v3] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
@ 2011-01-28 4:58 ` Haiying.Wang at freescale.com
2011-01-28 17:36 ` Scott Wood
[not found] ` <1296190690-21146-3-git-send-email-Haiying.Wang@freescale.c om>
4 siblings, 1 reply; 22+ messages in thread
From: Haiying.Wang at freescale.com @ 2011-01-28 4:58 UTC (permalink / raw)
To: u-boot
From: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/config.mk | 4 ++++
config.mk | 7 ++++++-
2 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 64191c7..78e53c4 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -27,7 +27,11 @@ STANDALONE_LOAD_ADDR = 0x40000
LDFLAGS_u-boot = --gc-sections
PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
+ifdef CONFIG_HAS_TPL
+PLATFORM_LDFLAGS += -n --gc-sections
+else
PLATFORM_LDFLAGS += -n
+endif
ifdef CONFIG_SYS_LDSCRIPT
# need to strip off double quotes
diff --git a/config.mk b/config.mk
index 5147c35..d7bb07f 100644
--- a/config.mk
+++ b/config.mk
@@ -260,8 +260,13 @@ $(obj)%.s: %.c
#########################################################################
# If the list of objects to link is empty, just create an empty built-in.o
+ifdef CONFIG_HAS_TPL
+cmd_link_o_target = $(if $(strip $1),\
+ $(LD) -r -o $@ $1,\
+ rm -f $@; $(AR) rcs $@ )
+else
cmd_link_o_target = $(if $(strip $1),\
$(LD) $(LDFLAGS) -r -o $@ $1,\
rm -f $@; $(AR) rcs $@ )
-
+endif
#########################################################################
--
1.7.3.1.50.g1e633
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
[not found] ` <1296190690-21146-3-git-send-email-Haiying.Wang@freescale.c om>
@ 2011-01-28 10:02 ` Fabian Cenedese
2011-01-28 14:43 ` Haiying Wang
0 siblings, 1 reply; 22+ messages in thread
From: Fabian Cenedese @ 2011-01-28 10:02 UTC (permalink / raw)
To: u-boot
At 23:58 27.01.2011 -0500, Haiying.Wang at freescale.com wrote:
>From: Haiying Wang <Haiying.Wang@freescale.com>
>
>Support P1021MDS board to boot from NAND flash (No NOR flash on this
>board). And because P1021 only has 256K L2 SRAM, which can not used for final
>uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
>be initialized in L2 SRAM through SPD code. So there are three stage uboot
>images:
>* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND.
>* tpl_boot, 112KB size. The env variables are copied to offset 128KB
> in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env.
> It loads final uboot image from offset 128KB in NAND.
>* final uboot image, size is variable depends on the functions enabled.
I'm not questioning the patch, I'm just trying to understand.
>+#define CONFIG_MP /* Multiprocessor support */
>+
>+#define CONFIG_PCI /* Disable PCI/PCIE */
Shouldn't that be "Enable" PCI?
bye Fabi
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 10:02 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Fabian Cenedese
@ 2011-01-28 14:43 ` Haiying Wang
0 siblings, 0 replies; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 14:43 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 11:02 +0100, Fabian Cenedese wrote:
>
> I'm not questioning the patch, I'm just trying to understand.
>
> >+#define CONFIG_MP /* Multiprocessor support */
> >+
> >+#define CONFIG_PCI /* Disable PCI/PCIE */
>
> Shouldn't that be "Enable" PCI?
Yes, you are right. Thanks for pointing out.
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 4:58 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Haiying.Wang at freescale.com
@ 2011-01-28 14:49 ` Kumar Gala
2011-01-28 15:19 ` Haiying Wang
2011-01-28 19:06 ` Timur Tabi
1 sibling, 1 reply; 22+ messages in thread
From: Kumar Gala @ 2011-01-28 14:49 UTC (permalink / raw)
To: u-boot
>
>
> diff --git a/board/freescale/p1021mds/law.c b/board/freescale/p1021mds/law.c
> new file mode 100644
> index 0000000..d0be19e
> --- /dev/null
> +++ b/board/freescale/p1021mds/law.c
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/fsl_law.h>
> +#include <asm/mmu.h>
> +
> +struct law_entry law_table[] = {
> +#ifndef CONFIG_IN_TPL
> + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
PCIe LAWs are now set by common code, you can remove these.
- k
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 14:49 ` Kumar Gala
@ 2011-01-28 15:19 ` Haiying Wang
0 siblings, 0 replies; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 15:19 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 08:49 -0600, Kumar Gala wrote:
> > +
> > +struct law_entry law_table[] = {
> > +#ifndef CONFIG_IN_TPL
> > + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> > + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> > + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> > + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
>
> PCIe LAWs are now set by common code, you can remove these.
>
Fixed it in v4 patch, thanks.
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 4:58 ` [U-Boot] [PATCH 7/7] add gc-sections to TPL boot Haiying.Wang at freescale.com
@ 2011-01-28 17:36 ` Scott Wood
2011-01-28 18:08 ` Haiying Wang
0 siblings, 1 reply; 22+ messages in thread
From: Scott Wood @ 2011-01-28 17:36 UTC (permalink / raw)
To: u-boot
On Thu, 27 Jan 2011 23:58:10 -0500
<Haiying.Wang@freescale.com> wrote:
> From: Haiying Wang <Haiying.Wang@freescale.com>
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> ---
> arch/powerpc/config.mk | 4 ++++
> config.mk | 7 ++++++-
> 2 files changed, 10 insertions(+), 1 deletions(-)
I see patch 3/8, 4/8, 5/8, and 7/7. Where are the rest?
> diff --git a/config.mk b/config.mk
> index 5147c35..d7bb07f 100644
> --- a/config.mk
> +++ b/config.mk
> @@ -260,8 +260,13 @@ $(obj)%.s: %.c
> #########################################################################
>
> # If the list of objects to link is empty, just create an empty built-in.o
> +ifdef CONFIG_HAS_TPL
> +cmd_link_o_target = $(if $(strip $1),\
> + $(LD) -r -o $@ $1,\
> + rm -f $@; $(AR) rcs $@ )
> +else
> cmd_link_o_target = $(if $(strip $1),\
> $(LD) $(LDFLAGS) -r -o $@ $1,\
> rm -f $@; $(AR) rcs $@ )
> -
> +endif
What's going on here?
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 17:36 ` Scott Wood
@ 2011-01-28 18:08 ` Haiying Wang
2011-01-28 18:21 ` Albert ARIBAUD
2011-01-28 18:30 ` Scott Wood
0 siblings, 2 replies; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 18:08 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 11:36 -0600, Scott Wood wrote:
> On Thu, 27 Jan 2011 23:58:10 -0500
> <Haiying.Wang@freescale.com> wrote:
>
> > From: Haiying Wang <Haiying.Wang@freescale.com>
> >
> > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> > ---
> > arch/powerpc/config.mk | 4 ++++
> > config.mk | 7 ++++++-
> > 2 files changed, 10 insertions(+), 1 deletions(-)
>
> I see patch 3/8, 4/8, 5/8, and 7/7. Where are the rest?
Sorry, patch 7/7 is a wrong number here. I kept the patch # as 3/8/,
4/8, 5/8, 8/8 to be consistent with the order in the patchset(v2) I
submitted in last December. I thought it would be clearer to compare
them with v2 version and review. Patch 1/8,2/8 have been applied by
Kumar, patch 6/8, 7/8 remain the same as v2 version. This patch, is a
new patch because that TPL still needs --gc-sections in linker option to
do partial link.
If it is preferable to have new whole set of patch, I can reorder them
from 3/8-8/8 plus this one to submit.
> > diff --git a/config.mk b/config.mk
> > index 5147c35..d7bb07f 100644
> > --- a/config.mk
> > +++ b/config.mk
> > @@ -260,8 +260,13 @@ $(obj)%.s: %.c
> > #########################################################################
> >
> > # If the list of objects to link is empty, just create an empty built-in.o
> > +ifdef CONFIG_HAS_TPL
> > +cmd_link_o_target = $(if $(strip $1),\
> > + $(LD) -r -o $@ $1,\
> > + rm -f $@; $(AR) rcs $@ )
> > +else
> > cmd_link_o_target = $(if $(strip $1),\
> > $(LD) $(LDFLAGS) -r -o $@ $1,\
> > rm -f $@; $(AR) rcs $@ )
> > -
> > +endif
>
> What's going on here?
>
For CONFIG_HAS_TPL, LDFLAGS has --gc-sections now, passing it to
cmd_link_o_target here will fail in linking stage:
"
powerpc-none-linux-gnuspe-ld: gc-sections requires either an entry or an
undefined symbol
"
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 18:08 ` Haiying Wang
@ 2011-01-28 18:21 ` Albert ARIBAUD
2011-01-28 18:30 ` Scott Wood
1 sibling, 0 replies; 22+ messages in thread
From: Albert ARIBAUD @ 2011-01-28 18:21 UTC (permalink / raw)
To: u-boot
Le 28/01/2011 19:08, Haiying Wang a ?crit :
>> I see patch 3/8, 4/8, 5/8, and 7/7. Where are the rest?
> Sorry, patch 7/7 is a wrong number here. I kept the patch # as 3/8/,
> 4/8, 5/8, 8/8 to be consistent with the order in the patchset(v2) I
> submitted in last December. I thought it would be clearer to compare
> them with v2 version and review. Patch 1/8,2/8 have been applied by
> Kumar, patch 6/8, 7/8 remain the same as v2 version. This patch, is a
> new patch because that TPL still needs --gc-sections in linker option to
> do partial link.
>
> If it is preferable to have new whole set of patch, I can reorder them
> from 3/8-8/8 plus this one to submit.
I would suggest to simply number patches from 1 to N for each version
even if that means the same patch gets numbered differently across
versions, because readers of a given version may not have read the
previous one. A patchset should be self-sufficient and self-consistent IMO.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 18:08 ` Haiying Wang
2011-01-28 18:21 ` Albert ARIBAUD
@ 2011-01-28 18:30 ` Scott Wood
2011-01-28 18:46 ` Haiying Wang
1 sibling, 1 reply; 22+ messages in thread
From: Scott Wood @ 2011-01-28 18:30 UTC (permalink / raw)
To: u-boot
On Fri, 28 Jan 2011 13:08:30 -0500
Haiying Wang <Haiying.Wang@freescale.com> wrote:
> On Fri, 2011-01-28 at 11:36 -0600, Scott Wood wrote:
> > On Thu, 27 Jan 2011 23:58:10 -0500
> > <Haiying.Wang@freescale.com> wrote:
> >
> > > From: Haiying Wang <Haiying.Wang@freescale.com>
> > >
> > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> > > ---
> > > arch/powerpc/config.mk | 4 ++++
> > > config.mk | 7 ++++++-
> > > 2 files changed, 10 insertions(+), 1 deletions(-)
> >
> > I see patch 3/8, 4/8, 5/8, and 7/7. Where are the rest?
> Sorry, patch 7/7 is a wrong number here. I kept the patch # as 3/8/,
> 4/8, 5/8, 8/8 to be consistent with the order in the patchset(v2) I
> submitted in last December. I thought it would be clearer to compare
> them with v2 version and review. Patch 1/8,2/8 have been applied by
> Kumar, patch 6/8, 7/8 remain the same as v2 version. This patch, is a
> new patch because that TPL still needs --gc-sections in linker option to
> do partial link.
>
> If it is preferable to have new whole set of patch, I can reorder them
> from 3/8-8/8 plus this one to submit.
Just produce a new complete patchset of what still needs to be
applied. Don't preserve the numbering.
> > > diff --git a/config.mk b/config.mk
> > > index 5147c35..d7bb07f 100644
> > > --- a/config.mk
> > > +++ b/config.mk
> > > @@ -260,8 +260,13 @@ $(obj)%.s: %.c
> > > #########################################################################
> > >
> > > # If the list of objects to link is empty, just create an empty built-in.o
> > > +ifdef CONFIG_HAS_TPL
> > > +cmd_link_o_target = $(if $(strip $1),\
> > > + $(LD) -r -o $@ $1,\
> > > + rm -f $@; $(AR) rcs $@ )
> > > +else
> > > cmd_link_o_target = $(if $(strip $1),\
> > > $(LD) $(LDFLAGS) -r -o $@ $1,\
> > > rm -f $@; $(AR) rcs $@ )
> > > -
> > > +endif
> >
> > What's going on here?
> >
> For CONFIG_HAS_TPL, LDFLAGS has --gc-sections now, passing it to
> cmd_link_o_target here will fail in linking stage:
> "
> powerpc-none-linux-gnuspe-ld: gc-sections requires either an entry or an
> undefined symbol
> "
I think --gc-sections should go in LDFLAGS_u-boot instead.
In any case, I don't think we want different behavior here based on
whether we have TPL. Either LDFLAGS is used in partial linking, or
it's not.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 18:30 ` Scott Wood
@ 2011-01-28 18:46 ` Haiying Wang
2011-01-28 18:58 ` Scott Wood
2011-01-28 19:07 ` Haiying Wang
0 siblings, 2 replies; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 18:46 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 12:30 -0600, Scott Wood wrote:
> > > > diff --git a/config.mk b/config.mk
> > > > index 5147c35..d7bb07f 100644
> > > > --- a/config.mk
> > > > +++ b/config.mk
> > > > @@ -260,8 +260,13 @@ $(obj)%.s: %.c
> > > > #########################################################################
> > > >
> > > > # If the list of objects to link is empty, just create an empty built-in.o
> > > > +ifdef CONFIG_HAS_TPL
> > > > +cmd_link_o_target = $(if $(strip $1),\
> > > > + $(LD) -r -o $@ $1,\
> > > > + rm -f $@; $(AR) rcs $@ )
> > > > +else
> > > > cmd_link_o_target = $(if $(strip $1),\
> > > > $(LD) $(LDFLAGS) -r -o $@ $1,\
> > > > rm -f $@; $(AR) rcs $@ )
> > > > -
> > > > +endif
> > >
> > > What's going on here?
> > >
> > For CONFIG_HAS_TPL, LDFLAGS has --gc-sections now, passing it to
> > cmd_link_o_target here will fail in linking stage:
> > "
> > powerpc-none-linux-gnuspe-ld: gc-sections requires either an entry or an
> > undefined symbol
> > "
>
> I think --gc-sections should go in LDFLAGS_u-boot instead.
LDFLAGS_u-boot has --gc-sections already, I did not change it. I only add --gc-sections to PLATFORM_LDFLAGS in arch/powerpc/config.mk under "ifdef CONFIG_HAS_TPL"
> In any case, I don't think we want different behavior here based on
> whether we have TPL. Either LDFLAGS is used in partial linking, or
> it's not.
I don't understand why LDFLAGS was added here in patch
http://lists.denx.de/pipermail/u-boot/2011-January/084705.html
It says "LDFLAGS sets necessary option by partial linking (use in
cmd_link_o_target)." But without this changing, the partial linking
worked well before. Please correct me if I am wrong.
So if someone can confirm LDFLAGS is not necessary to be added in
cmd_link_o_target, I prefer not add it here.
Thanks.
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 18:46 ` Haiying Wang
@ 2011-01-28 18:58 ` Scott Wood
2011-01-28 19:07 ` Haiying Wang
1 sibling, 0 replies; 22+ messages in thread
From: Scott Wood @ 2011-01-28 18:58 UTC (permalink / raw)
To: u-boot
On Fri, 28 Jan 2011 13:46:06 -0500
Haiying Wang <Haiying.Wang@freescale.com> wrote:
> On Fri, 2011-01-28 at 12:30 -0600, Scott Wood wrote:
> > I think --gc-sections should go in LDFLAGS_u-boot instead.
> LDFLAGS_u-boot has --gc-sections already, I did not change it.
It looks like LDFLAGS_u-boot may not be suitable for building SPL/TPL
images. Since TPL is new, and we don't have to worry about breaking
any existing boards, just unconditionally use --gc-sections when
linking the final TPL image. Or, if we want a way for
boards/cpus to add ld options that things like TPL use, introduce
LDFLAGS_FINAL that holds ld parameters used for final link of any
image, with LDFLAGS_u-boot holding things like text addresses and linker
scripts with values that only apply to the main image.
I'd prefer the latter approach, as we could make use of it in SPL as
well, which does have existing boards to worry about.
> > In any case, I don't think we want different behavior here based on
> > whether we have TPL. Either LDFLAGS is used in partial linking, or
> > it's not.
> I don't understand why LDFLAGS was added here in patch
> http://lists.denx.de/pipermail/u-boot/2011-January/084705.html
>
> It says "LDFLAGS sets necessary option by partial linking (use in
> cmd_link_o_target)." But without this changing, the partial linking
> worked well before. Please correct me if I am wrong.
>
> So if someone can confirm LDFLAGS is not necessary to be added in
> cmd_link_o_target, I prefer not add it here.
Whether leaving out -n during partial link worked for you or not,
LDFLAGS is supposed to be used by partial links (that distinction is
why LDFLAGS_u-boot was created). So don't put things in LDFPLAGS that
break partial links.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 4:58 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Haiying.Wang at freescale.com
2011-01-28 14:49 ` Kumar Gala
@ 2011-01-28 19:06 ` Timur Tabi
2011-01-28 19:13 ` Scott Wood
2011-01-28 19:22 ` Haiying Wang
1 sibling, 2 replies; 22+ messages in thread
From: Timur Tabi @ 2011-01-28 19:06 UTC (permalink / raw)
To: u-boot
On Thu, Jan 27, 2011 at 10:58 PM, <Haiying.Wang@freescale.com> wrote:
> +/* These are used when DDR doesn't use SPD. ?*/
> +#define CONFIG_SYS_SDRAM_SIZE ? ? ? ? ? 512 ? ? ? ? ? ?/* DDR is 512MB */
> +#define CONFIG_SYS_DDR_CS0_BNDS ? ? ? ? 0x0000001F
> +#define CONFIG_SYS_DDR_CS0_CONFIG ? ? ? 0x80014202
> +#define CONFIG_SYS_DDR_CS0_CONFIG_2 ? ?0x00000000
> +#define CONFIG_SYS_DDR_SDRAM_CFG ? ? ? 0x47000000
> +#define CONFIG_SYS_DDR_SDRAM_CFG_2 ? ? 0x04401040
> +#define CONFIG_SYS_DDR_ZQ_CNTL ? ? ? ? 0x89080600
> +#define CONFIG_SYS_DDR_WRLVL_CNTL ? ? ?0x86559608
> +#define CONFIG_SYS_DDR_CDR_1 ? ? ? ? ? 0x000eaa00
> +#define CONFIG_SYS_DDR_CDR_2 ? ? ? ? ? 0x00000000
> +#define CONFIG_SYS_DDR_OCD_CTRL ? ? ? ? 0x00000000
> +#define CONFIG_SYS_DDR_OCD_STATUS ? ? ? 0x00000000
> +#define CONFIG_SYS_DDR_CONTROL ? ? ? ? ?0x470c0000 ? ? ?/* Type = DDR3 */
> +#define CONFIG_SYS_DDR_CONTROL_2 ? ? ? 0x04401050
> +#define CONFIG_SYS_DDR_DATA_INIT ? ? ? ?0x1021babe
> +#define CONFIG_SYS_DDR_TIMING_3 ? ? ? ? ? ? ? ?0x00010000
> +#define CONFIG_SYS_DDR_TIMING_0 ? ? ? ? ? ? ? ?0x00330004
> +#define CONFIG_SYS_DDR_TIMING_1 ? ? ? ? ? ? ? ?0x5d5bd746
> +#define CONFIG_SYS_DDR_TIMING_2 ? ? ? ? ? ? ? ?0x0fa8c8cd
> +#define CONFIG_SYS_DDR_SDRAM_MODE ? ? ?0x40461320
> +#define CONFIG_SYS_DDR_SDRAM_MODE_2 ? ?0x8000C000
> +#define CONFIG_SYS_DDR_SDRAM_INTERVAL ?0x0a280000
> +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL ?0x03000000
> +#define CONFIG_SYS_DDR_TIMING_4 ? ? ? ? ? ? ? ?0x00220001
> +#define CONFIG_SYS_DDR_TIMING_5 ? ? ? ? ? ? ? ?0x03402400
Aren't static DDR configurations now handled in a board-specific
source file? Look at board/freescale/corenet_ds/p4080ds_ddr.c
> +#define CONFIG_ID_EEPROM
> +#ifdef CONFIG_ID_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_NXID
> +#endif
No need for the #ifdef here. CONFIG_SYS_I2C_EEPROM_NXID is not used
in any Makefile.
> +#define CONFIG_SYS_I2C_EEPROM_ADDR ? ? ?0x52
Not 0x57? That's where the NXID EEPROM almost always is.
> +void putc(char c)
> +{
> + ? ? ? if (c == '\n')
> + ? ? ? ? ? ? ? NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
> +
> + ? ? ? NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
> +}
> +
> +void puts(const char *str)
> +{
> + ? ? ? while (*str)
> + ? ? ? ? ? ? ? putc(*str++);
> +}
These look like functions that shouldn't be in board-specific code.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 18:46 ` Haiying Wang
2011-01-28 18:58 ` Scott Wood
@ 2011-01-28 19:07 ` Haiying Wang
2011-01-28 19:12 ` Scott Wood
1 sibling, 1 reply; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 19:07 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 13:46 -0500, Haiying Wang wrote:
> > In any case, I don't think we want different behavior here based on
> > whether we have TPL. Either LDFLAGS is used in partial linking, or
> > it's not.
> I don't understand why LDFLAGS was added here in patch
> http://lists.denx.de/pipermail/u-boot/2011-January/084705.html
>
> It says "LDFLAGS sets necessary option by partial linking (use in
> cmd_link_o_target)." But without this changing, the partial linking
> worked well before. Please correct me if I am wrong.
>
> So if someone can confirm LDFLAGS is not necessary to be added in
> cmd_link_o_target, I prefer not add it here.
BTW, I doubt removing --gc-sections for PLATFORM_FLAGS by patch
http://lists.denx.de/pipermail/u-boot/2011-January/084705.html may have
the risk of building failure for nand_spl, as we encountered the message
"NAND bootstrap too big" before
For example, the size for MPC8572DS_NAND_config before applying patch:
text data bss dec hex filename
3320 520 0 3840 f00 nand_spl/u-boot-spl
After applying that patch:
text data bss dec hex filename
3476 520 0 3996 f9c nand_spl/u-boot-spl
Once 8572 support is getting bigger as that in BSP, the error message
will be triggered.
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
2011-01-28 19:07 ` Haiying Wang
@ 2011-01-28 19:12 ` Scott Wood
0 siblings, 0 replies; 22+ messages in thread
From: Scott Wood @ 2011-01-28 19:12 UTC (permalink / raw)
To: u-boot
On Fri, 28 Jan 2011 14:07:09 -0500
Haiying Wang <Haiying.Wang@freescale.com> wrote:
> On Fri, 2011-01-28 at 13:46 -0500, Haiying Wang wrote:
> > > In any case, I don't think we want different behavior here based on
> > > whether we have TPL. Either LDFLAGS is used in partial linking, or
> > > it's not.
> > I don't understand why LDFLAGS was added here in patch
> > http://lists.denx.de/pipermail/u-boot/2011-January/084705.html
> >
> > It says "LDFLAGS sets necessary option by partial linking (use in
> > cmd_link_o_target)." But without this changing, the partial linking
> > worked well before. Please correct me if I am wrong.
> >
> > So if someone can confirm LDFLAGS is not necessary to be added in
> > cmd_link_o_target, I prefer not add it here.
>
> BTW, I doubt removing --gc-sections for PLATFORM_FLAGS by patch
> http://lists.denx.de/pipermail/u-boot/2011-January/084705.html may have
> the risk of building failure for nand_spl, as we encountered the message
> "NAND bootstrap too big" before
Yes, I saw that as well -- we need gc-sections. It just can't go in
LDFLAGS.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 19:06 ` Timur Tabi
@ 2011-01-28 19:13 ` Scott Wood
2011-01-28 19:22 ` Haiying Wang
1 sibling, 0 replies; 22+ messages in thread
From: Scott Wood @ 2011-01-28 19:13 UTC (permalink / raw)
To: u-boot
On Fri, 28 Jan 2011 13:06:28 -0600
Timur Tabi <timur@freescale.com> wrote:
> > +void putc(char c)
> > +{
> > + ? ? ? if (c == '\n')
> > + ? ? ? ? ? ? ? NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
> > +
> > + ? ? ? NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
> > +}
> > +
> > +void puts(const char *str)
> > +{
> > + ? ? ? while (*str)
> > + ? ? ? ? ? ? ? putc(*str++);
> > +}
>
> These look like functions that shouldn't be in board-specific code.
That's been established practice in the SPL board files so far, though
I suppose it could be factored out to its own file.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 19:06 ` Timur Tabi
2011-01-28 19:13 ` Scott Wood
@ 2011-01-28 19:22 ` Haiying Wang
2011-01-28 19:24 ` Timur Tabi
1 sibling, 1 reply; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 19:22 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 13:06 -0600, Timur Tabi wrote:
> On Thu, Jan 27, 2011 at 10:58 PM, <Haiying.Wang@freescale.com> wrote:
>
> > +/* These are used when DDR doesn't use SPD. */
> > +#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
> > +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
> > +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
> > +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
> > +#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
> > +#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
> > +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
> > +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x86559608
> > +#define CONFIG_SYS_DDR_CDR_1 0x000eaa00
> > +#define CONFIG_SYS_DDR_CDR_2 0x00000000
> > +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
> > +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
> > +#define CONFIG_SYS_DDR_CONTROL 0x470c0000 /* Type = DDR3 */
> > +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
> > +#define CONFIG_SYS_DDR_DATA_INIT 0x1021babe
> > +#define CONFIG_SYS_DDR_TIMING_3 0x00010000
> > +#define CONFIG_SYS_DDR_TIMING_0 0x00330004
> > +#define CONFIG_SYS_DDR_TIMING_1 0x5d5bd746
> > +#define CONFIG_SYS_DDR_TIMING_2 0x0fa8c8cd
> > +#define CONFIG_SYS_DDR_SDRAM_MODE 0x40461320
> > +#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
> > +#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x0a280000
> > +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
> > +#define CONFIG_SYS_DDR_TIMING_4 0x00220001
> > +#define CONFIG_SYS_DDR_TIMING_5 0x03402400
>
> Aren't static DDR configurations now handled in a board-specific
> source file? Look at board/freescale/corenet_ds/p4080ds_ddr.c
yes, static ddr configurations are handled in board c file, but it
doesn't matter to define those MACROs in header file. But anyway, I've
remove static ddr setting from board file as Scott suggested, so I
should remove above setting in header file.
>
> > +#define CONFIG_ID_EEPROM
> > +#ifdef CONFIG_ID_EEPROM
> > +#define CONFIG_SYS_I2C_EEPROM_NXID
> > +#endif
>
> No need for the #ifdef here. CONFIG_SYS_I2C_EEPROM_NXID is not used
> in any Makefile.
OK.
>
> > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
>
> Not 0x57? That's where the NXID EEPROM almost always is.
It is board specific value, isn't it? P1021MDS does use 0x52 for board eeprom.
> > +void putc(char c)
> > +{
> > + if (c == '\n')
> > + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
> > +
> > + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
> > +}
> > +
> > +void puts(const char *str)
> > +{
> > + while (*str)
> > + putc(*str++);
> > +}
>
> These look like functions that shouldn't be in board-specific code.
>
Scott replied you. I also think with partial linking, this can be
factored out.
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 19:22 ` Haiying Wang
@ 2011-01-28 19:24 ` Timur Tabi
2011-01-28 19:30 ` Haiying Wang
0 siblings, 1 reply; 22+ messages in thread
From: Timur Tabi @ 2011-01-28 19:24 UTC (permalink / raw)
To: u-boot
Haiying Wang wrote:
>>> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
>> >
>> > Not 0x57? That's where the NXID EEPROM almost always is.
> It is board specific value, isn't it? P1021MDS does use 0x52 for board eeprom.
I just wanted you to be sure it wasn't a typo. Did you actual test reading and
writing to the EEPROM with the 'mac' command?
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
2011-01-28 19:24 ` Timur Tabi
@ 2011-01-28 19:30 ` Haiying Wang
0 siblings, 0 replies; 22+ messages in thread
From: Haiying Wang @ 2011-01-28 19:30 UTC (permalink / raw)
To: u-boot
On Fri, 2011-01-28 at 13:24 -0600, Timur Tabi wrote:
> Haiying Wang wrote:
> >>> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
> >> >
> >> > Not 0x57? That's where the NXID EEPROM almost always is.
> > It is board specific value, isn't it? P1021MDS does use 0x52 for board eeprom.
>
> I just wanted you to be sure it wasn't a typo. Did you actual test reading and
> writing to the EEPROM with the 'mac' command?
Yes, I did test and have used it for almost one year. :)
Haiying
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2011-01-28 19:30 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-01-28 4:58 [U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Haiying.Wang at freescale.com
2011-01-28 14:49 ` Kumar Gala
2011-01-28 15:19 ` Haiying Wang
2011-01-28 19:06 ` Timur Tabi
2011-01-28 19:13 ` Scott Wood
2011-01-28 19:22 ` Haiying Wang
2011-01-28 19:24 ` Timur Tabi
2011-01-28 19:30 ` Haiying Wang
2011-01-28 4:58 ` [U-Boot] [PATCH 8/8 v3] p1021mds: add QE and UEC support Haiying.Wang at freescale.com
2011-01-28 4:58 ` [U-Boot] [PATCH 7/7] add gc-sections to TPL boot Haiying.Wang at freescale.com
2011-01-28 17:36 ` Scott Wood
2011-01-28 18:08 ` Haiying Wang
2011-01-28 18:21 ` Albert ARIBAUD
2011-01-28 18:30 ` Scott Wood
2011-01-28 18:46 ` Haiying Wang
2011-01-28 18:58 ` Scott Wood
2011-01-28 19:07 ` Haiying Wang
2011-01-28 19:12 ` Scott Wood
[not found] ` <1296190690-21146-3-git-send-email-Haiying.Wang@freescale.c om>
2011-01-28 10:02 ` [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support Fabian Cenedese
2011-01-28 14:43 ` Haiying Wang
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