From: Aneesh V <aneesh@ti.com> To: devicetree-discuss@lists.ozlabs.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Aneesh V <aneesh@ti.com>, Rajendra Nayak <rnayak@ti.com>, Benoit Cousson <b-cousson@ti.com> Subject: [PATCH 1/3] dt: device tree bindings for DDR memories Date: Thu, 19 Jan 2012 19:58:39 +0530 [thread overview] Message-ID: <1326983321-319-2-git-send-email-aneesh@ti.com> (raw) In-Reply-To: <1324303533-17458-1-git-send-email-aneesh@ti.com> device tree bindings for DDR SDRAM memories compliant to JEDEC standards. Currently only DDR3 and LPDDR2 have been considered for this binding. Properties for other memory types(DDR2 etc) could be added to this binding on a need-basis. The 'ddr' binding in-turn uses another binding 'ddr-timings' for specifying the AC timing parameters of the memory device at different speed-bins. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Changes in RFC v2: * Removed the "manufacturer" property and added it in compatible property instead * Changed the DDR device names in example to indicate the part number --- .../devicetree/bindings/ddr/lpddr2-timings.txt | 50 +++++++++ Documentation/devicetree/bindings/ddr/lpddr2.txt | 106 ++++++++++++++++++++ 2 files changed, 156 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt new file mode 100644 index 0000000..d4c1bff --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt @@ -0,0 +1,50 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin +- max-freq : maximum DDR clock frequency for the speed-bin + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type <u32> and the default unit is ps (pico seconds). +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt new file mode 100644 index 0000000..c03c62d --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -0,0 +1,106 @@ +* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", + "jedec,lpddr2-s4" + + "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type + + "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type + + "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type + +- density : <u32> representing density in Mb (Mega bits) + +- io-width : <u32> representing bus width. Possible values are 8, 16, and 32 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. + +The suffix 'tck' indicates that the unit for these parameters is number +of DDR clock cycles. + +- tRRD-min-tck +- tWTR-min-tck +- tXP-min-tck +- tRTP-min-tck +- tCKE-min-tck +- tRPab-min-tck +- tRCD-min-tck +- tWR-min-tck +- tRASmin-min-tck +- tCKESR-min-tck +- tFAW-min-tck + +Child nodes: +- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + +Example: + +elpida_ECB240ABACN : lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRP = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQoper = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRP = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQoper = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + +} -- 1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: aneesh@ti.com (Aneesh V) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] dt: device tree bindings for DDR memories Date: Thu, 19 Jan 2012 19:58:39 +0530 [thread overview] Message-ID: <1326983321-319-2-git-send-email-aneesh@ti.com> (raw) In-Reply-To: <1324303533-17458-1-git-send-email-aneesh@ti.com> device tree bindings for DDR SDRAM memories compliant to JEDEC standards. Currently only DDR3 and LPDDR2 have been considered for this binding. Properties for other memory types(DDR2 etc) could be added to this binding on a need-basis. The 'ddr' binding in-turn uses another binding 'ddr-timings' for specifying the AC timing parameters of the memory device at different speed-bins. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Changes in RFC v2: * Removed the "manufacturer" property and added it in compatible property instead * Changed the DDR device names in example to indicate the part number --- .../devicetree/bindings/ddr/lpddr2-timings.txt | 50 +++++++++ Documentation/devicetree/bindings/ddr/lpddr2.txt | 106 ++++++++++++++++++++ 2 files changed, 156 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt new file mode 100644 index 0000000..d4c1bff --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt @@ -0,0 +1,50 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin +- max-freq : maximum DDR clock frequency for the speed-bin + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type <u32> and the default unit is ps (pico seconds). +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt new file mode 100644 index 0000000..c03c62d --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -0,0 +1,106 @@ +* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", + "jedec,lpddr2-s4" + + "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type + + "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type + + "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type + +- density : <u32> representing density in Mb (Mega bits) + +- io-width : <u32> representing bus width. Possible values are 8, 16, and 32 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. + +The suffix 'tck' indicates that the unit for these parameters is number +of DDR clock cycles. + +- tRRD-min-tck +- tWTR-min-tck +- tXP-min-tck +- tRTP-min-tck +- tCKE-min-tck +- tRPab-min-tck +- tRCD-min-tck +- tWR-min-tck +- tRASmin-min-tck +- tCKESR-min-tck +- tFAW-min-tck + +Child nodes: +- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + +Example: + +elpida_ECB240ABACN : lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRP = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQoper = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings at 1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRP = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQoper = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + +} -- 1.7.1
next prev parent reply other threads:[~2012-01-19 14:28 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-12-19 14:05 [RFC v2 PATCH 0/3] dt: device tree bindings and data for EMIF and DDR Aneesh V 2011-12-19 14:05 ` Aneesh V 2011-12-19 14:05 ` [RFC v2 PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V 2011-12-19 14:05 ` Aneesh V 2011-12-19 16:52 ` Olof Johansson 2011-12-19 16:52 ` Olof Johansson 2011-12-20 7:09 ` Aneesh V 2011-12-20 7:09 ` Aneesh V 2012-01-19 12:18 ` Aneesh V 2012-01-19 12:18 ` Aneesh V 2011-12-19 14:05 ` [RFC v2 PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V 2011-12-19 14:05 ` Aneesh V 2011-12-19 16:56 ` Olof Johansson 2011-12-19 16:56 ` Olof Johansson 2011-12-20 7:12 ` Aneesh V 2011-12-20 7:12 ` Aneesh V 2011-12-19 16:59 ` Olof Johansson 2011-12-19 16:59 ` Olof Johansson 2011-12-20 7:19 ` Aneesh V 2011-12-20 7:19 ` Aneesh V 2011-12-19 14:05 ` [RFC v2 PATCH 3/3] arm/dts: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V 2011-12-19 14:05 ` Aneesh V 2011-12-19 23:01 ` [RFC v2 PATCH 0/3] dt: device tree bindings and data for EMIF and DDR Rob Herring 2011-12-19 23:01 ` Rob Herring 2011-12-19 23:35 ` Tony Lindgren 2011-12-19 23:35 ` Tony Lindgren 2011-12-20 10:44 ` Aneesh V 2011-12-20 10:44 ` Aneesh V 2011-12-20 12:40 ` Cousson, Benoit 2011-12-20 12:40 ` Cousson, Benoit 2011-12-20 14:08 ` Aneesh V 2011-12-20 14:08 ` Aneesh V 2012-01-08 17:23 ` Aneesh V 2012-01-08 17:23 ` Aneesh V 2012-01-09 5:42 ` Olof Johansson 2012-01-09 5:42 ` Olof Johansson 2012-01-13 19:36 ` Aneesh V 2012-01-13 19:36 ` Aneesh V 2012-01-16 19:15 ` Turquette, Mike 2012-01-16 19:15 ` Turquette, Mike 2012-01-19 19:26 ` Olof Johansson 2012-01-19 19:26 ` Olof Johansson 2012-01-17 12:06 ` Aneesh V 2012-01-17 12:06 ` Aneesh V 2011-12-20 10:16 ` Aneesh V 2011-12-20 10:16 ` Aneesh V 2012-01-19 14:28 ` Aneesh V 2012-01-19 14:28 ` Aneesh V 2012-01-19 14:31 ` Aneesh V 2012-01-19 14:31 ` Aneesh V 2012-01-19 14:28 ` Aneesh V [this message] 2012-01-19 14:28 ` [PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V 2012-01-19 14:28 ` [PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V 2012-01-19 14:28 ` Aneesh V 2012-01-19 14:28 ` [PATCH 3/3] arm/dts: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V 2012-01-19 14:28 ` Aneesh V
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