From: Olof Johansson <olof@lixom.net>
To: Aneesh V <aneesh@ti.com>
Cc: devicetree-discuss@lists.ozlabs.org, linux-omap@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Rajendra Nayak <rnayak@ti.com>, Benoit Cousson <b-cousson@ti.com>
Subject: Re: [RFC v2 PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller
Date: Mon, 19 Dec 2011 08:56:01 -0800 [thread overview]
Message-ID: <CAOesGMi79_4EH58rErxkBNevEUeCf56pSfEG2A4ejD4b4pNf-A@mail.gmail.com> (raw)
In-Reply-To: <1324303533-17458-3-git-send-email-aneesh@ti.com>
Hi,
Fewer comments here. :) But see below.
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh V <aneesh@ti.com> wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> @@ -0,0 +1,64 @@
> +* EMIF family of TI SDRAM controllers
> +
> +EMIF - External Memory Interface - is an SDRAM controller used in
> +TI SoCs. EMIF supports, based on the IP revision, one or more of
> +DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
> +of the EMIF IP and memory parts attached to it.
> +
> +Required properties:
> +- compatible : One or more of "ti,emif-ddr2", "ti,emif-ddr3", and
> + "ti,emif-lpddr2"
> +
> + "ti,emif-ddr2" should be listed of the EMIF controller on this SoC
> + supports DDR2 memories
> +
> + "ti,emif-ddr3" should be listed of the EMIF controller on this SoC
> + supports DDR3 memories
> +
> + "ti,emif-lpddr2" should be listed of the EMIF controller on this SoC
> + supports LPDDR2 memories
> +
> +- ti,hwmods : For TI hwmods processing and omap device creation
> + the value shall be "emif<n>" where <n> is the number of the EMIF
> + instance with base 1.
> +
> +- phy-type : string indicating the phy type. Should be one of the
> + following:
> +
> + "phy-type-omap4" : PHY used in OMAP4 family of SoCs
> +
> + "phy-type-dm81xx" : PHY used in DM81XX family of SoCs
> +
> +- ddr-handle : phandle to a "ddr" node representing the memory part
> + attached to this EMIF instance.
Just specify said ddr node as a child of this node instead of give it
a handle. What other bus would the ddr node sit on, if not the memory
controller bus?
-Olof
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WARNING: multiple messages have this Message-ID (diff)
From: olof@lixom.net (Olof Johansson)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC v2 PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller
Date: Mon, 19 Dec 2011 08:56:01 -0800 [thread overview]
Message-ID: <CAOesGMi79_4EH58rErxkBNevEUeCf56pSfEG2A4ejD4b4pNf-A@mail.gmail.com> (raw)
In-Reply-To: <1324303533-17458-3-git-send-email-aneesh@ti.com>
Hi,
Fewer comments here. :) But see below.
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh V <aneesh@ti.com> wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> @@ -0,0 +1,64 @@
> +* EMIF family of TI SDRAM controllers
> +
> +EMIF - External Memory Interface - is an SDRAM controller used in
> +TI SoCs. EMIF supports, based on the IP revision, one or more of
> +DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
> +of the EMIF IP and memory parts attached to it.
> +
> +Required properties:
> +- compatible ? : One or more of "ti,emif-ddr2", "ti,emif-ddr3", and
> + ?"ti,emif-lpddr2"
> +
> + ?"ti,emif-ddr2" should be listed of the EMIF controller on this SoC
> + ?supports DDR2 memories
> +
> + ?"ti,emif-ddr3" should be listed of the EMIF controller on this SoC
> + ?supports DDR3 memories
> +
> + ?"ti,emif-lpddr2" should be listed of the EMIF controller on this SoC
> + ?supports LPDDR2 memories
> +
> +- ti,hwmods ? ?: For TI hwmods processing and omap device creation
> + ?the value shall be "emif<n>" where <n> is the number of the EMIF
> + ?instance with base 1.
> +
> +- phy-type ? ? : string indicating the phy type. Should be one of the
> + ?following:
> +
> + ?"phy-type-omap4" ?: PHY used in OMAP4 family of SoCs
> +
> + ?"phy-type-dm81xx" : PHY used in DM81XX family of SoCs
> +
> +- ddr-handle ? : phandle to a "ddr" node representing the memory part
> + ?attached to this EMIF instance.
Just specify said ddr node as a child of this node instead of give it
a handle. What other bus would the ddr node sit on, if not the memory
controller bus?
-Olof
next prev parent reply other threads:[~2011-12-19 16:56 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-19 14:05 [RFC v2 PATCH 0/3] dt: device tree bindings and data for EMIF and DDR Aneesh V
2011-12-19 14:05 ` Aneesh V
2011-12-19 14:05 ` [RFC v2 PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V
2011-12-19 14:05 ` Aneesh V
2011-12-19 16:52 ` Olof Johansson
2011-12-19 16:52 ` Olof Johansson
2011-12-20 7:09 ` Aneesh V
2011-12-20 7:09 ` Aneesh V
2012-01-19 12:18 ` Aneesh V
2012-01-19 12:18 ` Aneesh V
2011-12-19 14:05 ` [RFC v2 PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V
2011-12-19 14:05 ` Aneesh V
2011-12-19 16:56 ` Olof Johansson [this message]
2011-12-19 16:56 ` Olof Johansson
2011-12-20 7:12 ` Aneesh V
2011-12-20 7:12 ` Aneesh V
2011-12-19 16:59 ` Olof Johansson
2011-12-19 16:59 ` Olof Johansson
2011-12-20 7:19 ` Aneesh V
2011-12-20 7:19 ` Aneesh V
2011-12-19 14:05 ` [RFC v2 PATCH 3/3] arm/dts: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V
2011-12-19 14:05 ` Aneesh V
2011-12-19 23:01 ` [RFC v2 PATCH 0/3] dt: device tree bindings and data for EMIF and DDR Rob Herring
2011-12-19 23:01 ` Rob Herring
2011-12-19 23:35 ` Tony Lindgren
2011-12-19 23:35 ` Tony Lindgren
2011-12-20 10:44 ` Aneesh V
2011-12-20 10:44 ` Aneesh V
2011-12-20 12:40 ` Cousson, Benoit
2011-12-20 12:40 ` Cousson, Benoit
2011-12-20 14:08 ` Aneesh V
2011-12-20 14:08 ` Aneesh V
2012-01-08 17:23 ` Aneesh V
2012-01-08 17:23 ` Aneesh V
2012-01-09 5:42 ` Olof Johansson
2012-01-09 5:42 ` Olof Johansson
2012-01-13 19:36 ` Aneesh V
2012-01-13 19:36 ` Aneesh V
2012-01-16 19:15 ` Turquette, Mike
2012-01-16 19:15 ` Turquette, Mike
2012-01-19 19:26 ` Olof Johansson
2012-01-19 19:26 ` Olof Johansson
2012-01-17 12:06 ` Aneesh V
2012-01-17 12:06 ` Aneesh V
2011-12-20 10:16 ` Aneesh V
2011-12-20 10:16 ` Aneesh V
2012-01-19 14:28 ` Aneesh V
2012-01-19 14:28 ` Aneesh V
2012-01-19 14:31 ` Aneesh V
2012-01-19 14:31 ` Aneesh V
2012-01-19 14:28 ` [PATCH 1/3] dt: device tree bindings for DDR memories Aneesh V
2012-01-19 14:28 ` Aneesh V
2012-01-19 14:28 ` [PATCH 2/3] dt: device tree bindings for TI's EMIF sdram controller Aneesh V
2012-01-19 14:28 ` Aneesh V
2012-01-19 14:28 ` [PATCH 3/3] arm/dts: EMIF and lpddr2 device tree data for OMAP4 boards Aneesh V
2012-01-19 14:28 ` Aneesh V
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