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From: Lee Jones <lee.jones@linaro.org>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: lee.jones@linaro.org, kernel@stlinux.com, tglx@linutronix.de,
	jason@lakedaemon.net, devicetree@vger.kernel.org
Subject: [PATCH v3 5/8] ARM: STi: STiH416: Enable PMU IRQs
Date: Wed, 18 Feb 2015 15:14:01 +0000	[thread overview]
Message-ID: <1424272444-16230-6-git-send-email-lee.jones@linaro.org> (raw)
In-Reply-To: <1424272444-16230-1-git-send-email-lee.jones@linaro.org>

This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.

Here we are enabling PMU IRQs on both channels.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index cdbf29c..de2afb9 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
 / {
 	L2: cache-controller {
 		compatible = "arm,pl310-cache";
@@ -92,6 +93,15 @@
 			reg		= <0xfe4b5100 0x8>;
 		};
 
+		irq-syscfg {
+			compatible    = "st,stih416-irq-syscfg";
+			st,syscfg     = <&syscfg_cpu>;
+			st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+					<ST_IRQ_SYSCFG_PMU_1>;
+			st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+					<ST_IRQ_SYSCFG_DISABLED>;
+		};
+
 		serial2: serial@fed32000{
 			compatible	= "st,asc";
 			status 		= "disabled";
-- 
1.9.1


WARNING: multiple messages have this Message-ID
From: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
	kernel-F5mvAk5X5gdBDgjK7y7TUQ@public.gmane.org,
	tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org,
	jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v3 5/8] ARM: STi: STiH416: Enable PMU IRQs
Date: Wed, 18 Feb 2015 15:14:01 +0000	[thread overview]
Message-ID: <1424272444-16230-6-git-send-email-lee.jones@linaro.org> (raw)
In-Reply-To: <1424272444-16230-1-git-send-email-lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.

Here we are enabling PMU IRQs on both channels.

Signed-off-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index cdbf29c..de2afb9 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
 / {
 	L2: cache-controller {
 		compatible = "arm,pl310-cache";
@@ -92,6 +93,15 @@
 			reg		= <0xfe4b5100 0x8>;
 		};
 
+		irq-syscfg {
+			compatible    = "st,stih416-irq-syscfg";
+			st,syscfg     = <&syscfg_cpu>;
+			st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+					<ST_IRQ_SYSCFG_PMU_1>;
+			st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+					<ST_IRQ_SYSCFG_DISABLED>;
+		};
+
 		serial2: serial@fed32000{
 			compatible	= "st,asc";
 			status 		= "disabled";
-- 
1.9.1

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WARNING: multiple messages have this Message-ID
From: lee.jones@linaro.org (Lee Jones)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/8] ARM: STi: STiH416: Enable PMU IRQs
Date: Wed, 18 Feb 2015 15:14:01 +0000	[thread overview]
Message-ID: <1424272444-16230-6-git-send-email-lee.jones@linaro.org> (raw)
In-Reply-To: <1424272444-16230-1-git-send-email-lee.jones@linaro.org>

This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.

Here we are enabling PMU IRQs on both channels.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index cdbf29c..de2afb9 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
 / {
 	L2: cache-controller {
 		compatible = "arm,pl310-cache";
@@ -92,6 +93,15 @@
 			reg		= <0xfe4b5100 0x8>;
 		};
 
+		irq-syscfg {
+			compatible    = "st,stih416-irq-syscfg";
+			st,syscfg     = <&syscfg_cpu>;
+			st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+					<ST_IRQ_SYSCFG_PMU_1>;
+			st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+					<ST_IRQ_SYSCFG_DISABLED>;
+		};
+
 		serial2: serial at fed32000{
 			compatible	= "st,asc";
 			status 		= "disabled";
-- 
1.9.1

  parent reply	other threads:[~2015-02-18 15:16 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-18 15:13 [PATCH v3 0/8] irqchip: New driver for ST's SysCfg controlled IRQs Lee Jones
2015-02-18 15:13 ` Lee Jones
2015-02-18 15:13 ` [PATCH v3 1/8] dt: bindings: Supply shared ST IRQ defines Lee Jones
2015-02-18 15:13   ` Lee Jones
2015-02-18 15:13   ` Lee Jones
2015-02-18 15:13 ` [PATCH v3 2/8] irqchip: Supply new driver for STi based devices Lee Jones
2015-02-18 15:13   ` Lee Jones
2015-02-18 15:13   ` Lee Jones
2015-02-18 15:13 ` [PATCH v3 3/8] irqchip: irq-st: Add documentation for STi based syscfg IRQs Lee Jones
2015-02-18 15:13   ` Lee Jones
2015-02-18 15:14 ` [PATCH v3 4/8] ARM: STi: STiH416: Enable Cortex-A9 PMU support Lee Jones
2015-02-18 15:14   ` Lee Jones
2015-02-18 15:14 ` Lee Jones [this message]
2015-02-18 15:14   ` [PATCH v3 5/8] ARM: STi: STiH416: Enable PMU IRQs Lee Jones
2015-02-18 15:14   ` Lee Jones
2015-02-18 15:14 ` [PATCH v3 6/8] ARM: STi: STiH407: Enable Cortex-A9 PMU support Lee Jones
2015-02-18 15:14   ` Lee Jones
2015-02-18 15:14 ` [PATCH v3 7/8] ARM: STi: STiH407: Enable PMU IRQs Lee Jones
2015-02-18 15:14   ` Lee Jones
2015-02-18 15:14 ` [PATCH v3 8/8] ARM: STI: Ensure requested STi's SysCfg Controlled IRQs are enabled at boot Lee Jones
2015-02-18 15:14   ` Lee Jones
2015-03-08  4:02 ` [PATCH v3 0/8] irqchip: New driver for ST's SysCfg controlled IRQs Jason Cooper
2015-03-08  4:02   ` Jason Cooper
2015-03-08  4:02   ` Jason Cooper
2015-03-09  7:48   ` Lee Jones
2015-03-09  7:48     ` Lee Jones
2015-03-09  7:48     ` Lee Jones

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