[PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Lucas Stach]

From: Philipp Zabel <p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/panel/panel-simple.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 30904a9b2a4c..dc6a923c89d7 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -729,6 +729,7 @@ static const struct panel_desc hannstar_hsd070pww1 = {
 		.width = 151,
 		.height = 94,
 	},
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 };
 
 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
-- 
2.1.4

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[PATCH 2/2] drm/panel: correct minimum hsync length of the HannStar HSD070PWW1 panel

[Lucas Stach]

From: Philipp Zabel <p.zabel@pengutronix.de>

According to the data sheet, the minimum horizontal blanking interval
is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
minimum working horizontal blanking interval to be 60 clocks.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/panel/panel-simple.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index dc6a923c89d7..7196b940a928 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -713,7 +713,12 @@ static const struct display_timing hannstar_hsd070pww1_timing = {
 	.hactive = { 1280, 1280, 1280 },
 	.hfront_porch = { 1, 1, 10 },
 	.hback_porch = { 1, 1, 10 },
-	.hsync_len = { 52, 158, 661 },
+	/*
+	 * According to the data sheet, the minimum horizontal blanking interval
+	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
+	 * minimum working horizontal blanking interval to be 60 clocks.
+	 */
+	.hsync_len = { 58, 158, 661 },
 	.vactive = { 800, 800, 800 },
 	.vfront_porch = { 1, 1, 10 },
 	.vback_porch = { 1, 1, 10 },
-- 
2.1.4

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Re: [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Lucas Stach]

Hey Thierry,

can you please take some time to look at those two small patches?

Thanks,
Lucas

Am Freitag, den 26.06.2015, 12:27 +0200 schrieb Lucas Stach:
> From: Philipp Zabel <p.zabel@pengutronix.de>
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 30904a9b2a4c..dc6a923c89d7 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -729,6 +729,7 @@ static const struct panel_desc hannstar_hsd070pww1 = {
>  		.width = 151,
>  		.height = 94,
>  	},
> +	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
>  };
>  
>  static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {

-- 
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |

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Re: [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Lucas Stach]

Ping.
Please take a look at those, it would be a shame if they miss the next
merge window, despite being on the list for over 1.5 months now.

Regards,
Lucas

Am Donnerstag, den 23.07.2015, 16:45 +0200 schrieb Lucas Stach:
> Hey Thierry,
> 
> can you please take some time to look at those two small patches?
> 
> Thanks,
> Lucas
> 
> Am Freitag, den 26.06.2015, 12:27 +0200 schrieb Lucas Stach:
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index 30904a9b2a4c..dc6a923c89d7 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -729,6 +729,7 @@ static const struct panel_desc hannstar_hsd070pww1 = {
> >  		.width = 151,
> >  		.height = 94,
> >  	},
> > +	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
> >  };
> >  
> >  static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
> 

-- 
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Industrial Linux Solutions   | http://www.pengutronix.de/  |

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Re: [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Thierry Reding]

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On Fri, Jun 26, 2015 at 12:27:08PM +0200, Lucas Stach wrote:
> From: Philipp Zabel <p.zabel@pengutronix.de>
> 

Can you be more specific here? What kind of bus format is this? Why is
it that .bpc = 6 doesn't work here?

Thierry

> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 30904a9b2a4c..dc6a923c89d7 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -729,6 +729,7 @@ static const struct panel_desc hannstar_hsd070pww1 = {
>  		.width = 151,
>  		.height = 94,
>  	},
> +	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
>  };
>  
>  static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
> -- 
> 2.1.4
> 

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Re: [PATCH 2/2] drm/panel: correct minimum hsync length of the HannStar HSD070PWW1 panel

[Thierry Reding]

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On Fri, Jun 26, 2015 at 12:27:09PM +0200, Lucas Stach wrote:
> From: Philipp Zabel <p.zabel@pengutronix.de>
> 
> According to the data sheet, the minimum horizontal blanking interval
> is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> minimum working horizontal blanking interval to be 60 clocks.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index dc6a923c89d7..7196b940a928 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -713,7 +713,12 @@ static const struct display_timing hannstar_hsd070pww1_timing = {
>  	.hactive = { 1280, 1280, 1280 },
>  	.hfront_porch = { 1, 1, 10 },
>  	.hback_porch = { 1, 1, 10 },
> -	.hsync_len = { 52, 158, 661 },
> +	/*
> +	 * According to the data sheet, the minimum horizontal blanking interval
> +	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> +	 * minimum working horizontal blanking interval to be 60 clocks.
> +	 */
> +	.hsync_len = { 58, 158, 661 },

58 != 60, so which one is the truth here?

Thierry

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Re: [PATCH 2/2] drm/panel: correct minimum hsync length of the HannStar HSD070PWW1 panel

[Lucas Stach]

Am Freitag, den 07.08.2015, 14:43 +0200 schrieb Thierry Reding:
> On Fri, Jun 26, 2015 at 12:27:09PM +0200, Lucas Stach wrote:
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > 
> > According to the data sheet, the minimum horizontal blanking interval
> > is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> > minimum working horizontal blanking interval to be 60 clocks.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index dc6a923c89d7..7196b940a928 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -713,7 +713,12 @@ static const struct display_timing hannstar_hsd070pww1_timing = {
> >  	.hactive = { 1280, 1280, 1280 },
> >  	.hfront_porch = { 1, 1, 10 },
> >  	.hback_porch = { 1, 1, 10 },
> > -	.hsync_len = { 52, 158, 661 },
> > +	/*
> > +	 * According to the data sheet, the minimum horizontal blanking interval
> > +	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> > +	 * minimum working horizontal blanking interval to be 60 clocks.
> > +	 */
> > +	.hsync_len = { 58, 158, 661 },
> 
> 58 != 60, so which one is the truth here?
> 
The comment says blanking interval must be at least 60 clocks. Blanking
interval = front_porch + hsync_len + back_porch. Both minimum front and
back porch for this panel are 1 clock, so the values match the comment.

Regards,
Lucas

-- 
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Industrial Linux Solutions   | http://www.pengutronix.de/  |

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Re: [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Philipp Zabel]

Am Freitag, den 07.08.2015, 14:42 +0200 schrieb Thierry Reding:
> On Fri, Jun 26, 2015 at 12:27:08PM +0200, Lucas Stach wrote:
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > 
> 
> Can you be more specific here? What kind of bus format is this?

The bus_format contains more information than just the bpc. In this
case, the SPWG default format for RGB666 via 3-pair LVDS specifies how
the 18 color bits are serialized in the 7 time slots for each pixel
clock. See
http://linuxtv.org/downloads/v4l-dvb-apis/subdev.html#v4l2-mbus-pixelcode-rgb-lvds
for details.

> Why is it that .bpc = 6 doesn't work here?

In this case a LVDS driver could indeed still decide itself that
bpc == 6 should be translated to MEDIA_BUS_FMT_RGB666_1X7X3_SPWG (and
not MEDIA_BUS_FMT_RGB666_1X18, or MEDIA_BUS_FMT_RGB666_1X24_CPADHI, for
example). But in the bpc == 8 case there are two different standard ways
to order the bits (SPWG/VESA vs JEIDA).
For consistency, I'd prefer to set bus_format to the correct value
everywhere.

regards
Philipp

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Re: [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

[Thierry Reding]

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On Fri, Aug 07, 2015 at 03:06:38PM +0200, Philipp Zabel wrote:
> Am Freitag, den 07.08.2015, 14:42 +0200 schrieb Thierry Reding:
> > On Fri, Jun 26, 2015 at 12:27:08PM +0200, Lucas Stach wrote:
> > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > 
> > 
> > Can you be more specific here? What kind of bus format is this?
> 
> The bus_format contains more information than just the bpc. In this
> case, the SPWG default format for RGB666 via 3-pair LVDS specifies how
> the 18 color bits are serialized in the 7 time slots for each pixel
> clock. See
> http://linuxtv.org/downloads/v4l-dvb-apis/subdev.html#v4l2-mbus-pixelcode-rgb-lvds
> for details.
> 
> > Why is it that .bpc = 6 doesn't work here?
> 
> In this case a LVDS driver could indeed still decide itself that
> bpc == 6 should be translated to MEDIA_BUS_FMT_RGB666_1X7X3_SPWG (and
> not MEDIA_BUS_FMT_RGB666_1X18, or MEDIA_BUS_FMT_RGB666_1X24_CPADHI, for
> example). But in the bpc == 8 case there are two different standard ways
> to order the bits (SPWG/VESA vs JEIDA).
> For consistency, I'd prefer to set bus_format to the correct value
> everywhere.

Now if we can put that into a commit message, that'd be perfect.

Thierry

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