From: Alistair <alistair23@gmail.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
sagark@eecs.berkeley.edu, palmer@sifive.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G()
Date: Fri, 25 Jan 2019 14:29:30 -0800 [thread overview]
Message-ID: <14f6462f-ea46-7e1a-d03a-bed324f9d88b@gmail.com> (raw)
In-Reply-To: <20190123092538.8004-31-kbastian@mail.uni-paderborn.de>
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
> decodetree handles all instructions now so the fallback is not necessary
> anymore.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 23 +----------------------
> 1 file changed, 1 insertion(+), 22 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0e37beb68e..b0251b3518 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
> #include "decode_insn16.inc.c"
> #include "insn_trans/trans_rvc.inc.c"
>
> -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> -{
> - uint32_t op;
> -
> - /* We do not do misaligned address check here: the address should never be
> - * misaligned at this point. Instructions that set PC must do the check,
> - * since epc must be the address of the instruction that caused us to
> - * perform the misaligned instruction fetch */
> -
> - op = MASK_OP_MAJOR(ctx->opcode);
> -
> - switch (op) {
> - case OPC_RISC_SYSTEM:
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> static void decode_opc(DisasContext *ctx)
> {
> /* check for compressed insn */
> @@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx)
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> if (!decode_insn32(ctx, ctx->opcode)) {
> - /* fallback to old decoder */
> - decode_RV32_64G(ctx->env, ctx);
> + gen_exception_illegal(ctx);
> }
> }
> }
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair <alistair23@gmail.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
sagark@eecs.berkeley.edu, palmer@sifive.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G()
Date: Fri, 25 Jan 2019 14:29:30 -0800 [thread overview]
Message-ID: <14f6462f-ea46-7e1a-d03a-bed324f9d88b@gmail.com> (raw)
In-Reply-To: <20190123092538.8004-31-kbastian@mail.uni-paderborn.de>
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
> decodetree handles all instructions now so the fallback is not necessary
> anymore.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 23 +----------------------
> 1 file changed, 1 insertion(+), 22 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0e37beb68e..b0251b3518 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
> #include "decode_insn16.inc.c"
> #include "insn_trans/trans_rvc.inc.c"
>
> -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> -{
> - uint32_t op;
> -
> - /* We do not do misaligned address check here: the address should never be
> - * misaligned at this point. Instructions that set PC must do the check,
> - * since epc must be the address of the instruction that caused us to
> - * perform the misaligned instruction fetch */
> -
> - op = MASK_OP_MAJOR(ctx->opcode);
> -
> - switch (op) {
> - case OPC_RISC_SYSTEM:
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> static void decode_opc(DisasContext *ctx)
> {
> /* check for compressed insn */
> @@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx)
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> if (!decode_insn32(ctx, ctx->opcode)) {
> - /* fallback to old decoder */
> - decode_RV32_64G(ctx->env, ctx);
> + gen_exception_illegal(ctx);
> }
> }
> }
>
next prev parent reply other threads:[~2019-01-25 22:30 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23 ` [Qemu-devel] " Alistair
2019-01-25 22:23 ` [Qemu-riscv] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23 ` [Qemu-devel] " Alistair
2019-01-25 22:23 ` [Qemu-riscv] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:25 ` [Qemu-devel] " Alistair
2019-01-25 22:25 ` [Qemu-riscv] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:27 ` [Qemu-devel] " Alistair
2019-01-25 22:27 ` [Qemu-riscv] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:28 ` [Qemu-devel] " Alistair
2019-01-25 22:28 ` [Qemu-riscv] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:29 ` Alistair [this message]
2019-01-25 22:29 ` [Qemu-riscv] [Qemu-devel] " Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 17:50 ` [Qemu-riscv] " no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:18 ` [Qemu-riscv] " no-reply
2019-01-31 18:22 ` no-reply
2019-01-31 18:22 ` [Qemu-riscv] " no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-12 23:21 ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13 2:15 ` [Qemu-devel] " Palmer Dabbelt
2019-02-13 2:15 ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13 9:06 ` [Qemu-devel] " Bastian Koppelmann
2019-02-13 9:06 ` [Qemu-riscv] " Bastian Koppelmann
2019-02-13 15:34 ` Palmer Dabbelt
2019-02-13 15:34 ` [Qemu-riscv] " Palmer Dabbelt
2019-02-14 0:37 ` Palmer Dabbelt
2019-02-14 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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