From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com> Subject: [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I load/store insns to decodetree Date: Wed, 23 Jan 2019 10:25:08 +0100 [thread overview] Message-ID: <20190123092538.8004-6-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 8 +++++--- target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++ target/riscv/translate.c | 7 ------- 4 files changed, 50 insertions(+), 10 deletions(-) create mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index bf0a268033..05087a91bb 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/riscv/decode_insn32.inc.c: \ - $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) +decode32-y = $(SRC_PATH)/target/riscv/insn32.decode +decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode + +target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode new file mode 100644 index 0000000000..439d4e2c58 --- /dev/null +++ b/target/riscv/insn32-64.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index f3b88ebb69..39a20a70e8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); return true; } + +#ifdef TARGET_RISCV64 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sd(DisasContext *ctx, arg_sd *a) +{ + gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b81297f23e..609207f785 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LOAD: - gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_STORE: - gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2, - GET_STORE_IMM(ctx->opcode)); - break; case OPC_RISC_ARITH_IMM: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_IMM_W: -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com> Subject: [Qemu-riscv] [PATCH v6 05/35] target/riscv: Convert RV64I load/store insns to decodetree Date: Wed, 23 Jan 2019 10:25:08 +0100 [thread overview] Message-ID: <20190123092538.8004-6-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 8 +++++--- target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++ target/riscv/translate.c | 7 ------- 4 files changed, 50 insertions(+), 10 deletions(-) create mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index bf0a268033..05087a91bb 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/riscv/decode_insn32.inc.c: \ - $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) +decode32-y = $(SRC_PATH)/target/riscv/insn32.decode +decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode + +target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode new file mode 100644 index 0000000000..439d4e2c58 --- /dev/null +++ b/target/riscv/insn32-64.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index f3b88ebb69..39a20a70e8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); return true; } + +#ifdef TARGET_RISCV64 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sd(DisasContext *ctx, arg_sd *a) +{ + gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b81297f23e..609207f785 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LOAD: - gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_STORE: - gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2, - GET_STORE_IMM(ctx->opcode)); - break; case OPC_RISC_ARITH_IMM: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_IMM_W: -- 2.20.1
next prev parent reply other threads:[~2019-01-23 9:26 UTC|newest] Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` Bastian Koppelmann [this message] 2019-01-23 9:25 ` [Qemu-riscv] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:25 ` [Qemu-devel] " Alistair 2019-01-25 22:25 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:27 ` [Qemu-devel] " Alistair 2019-01-25 22:27 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:28 ` [Qemu-devel] " Alistair 2019-01-25 22:28 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:29 ` [Qemu-devel] " Alistair 2019-01-25 22:29 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply 2019-01-31 17:50 ` [Qemu-riscv] " no-reply 2019-01-31 18:18 ` no-reply 2019-01-31 18:18 ` [Qemu-riscv] " no-reply 2019-01-31 18:22 ` no-reply 2019-01-31 18:22 ` [Qemu-riscv] " no-reply 2019-02-12 23:21 ` Palmer Dabbelt 2019-02-12 23:21 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-devel] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 9:06 ` [Qemu-devel] " Bastian Koppelmann 2019-02-13 9:06 ` [Qemu-riscv] " Bastian Koppelmann 2019-02-13 15:34 ` Palmer Dabbelt 2019-02-13 15:34 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-14 0:37 ` Palmer Dabbelt 2019-02-14 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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