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From: Palmer Dabbelt <palmer@sifive.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	sagark@eecs.berkeley.edu
Subject: Re: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Date: Wed, 13 Feb 2019 16:37:53 -0800 (PST)	[thread overview]
Message-ID: <mhng-ee0701f2-0571-4996-a9e1-2e6e03dd2167@palmer-si-x1c4> (raw)
In-Reply-To: <7a7b5675-3d66-6c87-8830-74c60f8a7471@mail.uni-paderborn.de>

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
>
> On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
>> On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> [snip]
>>>
>>> Do you, by any chance, have a v7?  It looks like there's quite a few merge
>>> conflicts here, and while I'm OK fixing them I don't want to do it if you
>>> already have.
>>>
>> I made it through my rebase, so unless you want to send out a v7 I will.
>> There were some meaningful changes so I'd like to get a round of review
>> just so everyone is on the same page.
>
>
> Thanks for doing this work. I don't have a v7 yet, since I was waiting
> on your current pull-request to get merged. So please do send a v7, I'm
> happy to review/test it.

No problem, they're my merge conflicts :).  It's on the list.

WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	sagark@eecs.berkeley.edu
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Date: Wed, 13 Feb 2019 16:37:53 -0800 (PST)	[thread overview]
Message-ID: <mhng-ee0701f2-0571-4996-a9e1-2e6e03dd2167@palmer-si-x1c4> (raw)
In-Reply-To: <7a7b5675-3d66-6c87-8830-74c60f8a7471@mail.uni-paderborn.de>

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
>
> On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
>> On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> [snip]
>>>
>>> Do you, by any chance, have a v7?  It looks like there's quite a few merge
>>> conflicts here, and while I'm OK fixing them I don't want to do it if you
>>> already have.
>>>
>> I made it through my rebase, so unless you want to send out a v7 I will.
>> There were some meaningful changes so I'd like to get a round of review
>> just so everyone is on the same page.
>
>
> Thanks for doing this work. I don't have a v7 yet, since I was waiting
> on your current pull-request to get merged. So please do send a v7, I'm
> happy to review/test it.

No problem, they're my merge conflicts :).  It's on the list.


  parent reply	other threads:[~2019-02-14  0:51 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-23  9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23   ` [Qemu-devel] " Alistair
2019-01-25 22:23     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:23   ` [Qemu-devel] " Alistair
2019-01-25 22:23     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:25   ` [Qemu-devel] " Alistair
2019-01-25 22:25     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:27   ` [Qemu-devel] " Alistair
2019-01-25 22:27     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:28   ` [Qemu-devel] " Alistair
2019-01-25 22:28     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-25 22:29   ` [Qemu-devel] " Alistair
2019-01-25 22:29     ` [Qemu-riscv] " Alistair
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-23  9:25   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 17:50   ` [Qemu-riscv] " no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:18   ` [Qemu-riscv] " no-reply
2019-01-31 18:22 ` no-reply
2019-01-31 18:22   ` [Qemu-riscv] " no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-12 23:21   ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13  2:15   ` [Qemu-devel] " Palmer Dabbelt
2019-02-13  2:15     ` [Qemu-riscv] " Palmer Dabbelt
2019-02-13  9:06     ` [Qemu-devel] " Bastian Koppelmann
2019-02-13  9:06       ` [Qemu-riscv] " Bastian Koppelmann
2019-02-13 15:34       ` Palmer Dabbelt
2019-02-13 15:34         ` [Qemu-riscv] " Palmer Dabbelt
2019-02-14  0:37       ` Palmer Dabbelt [this message]
2019-02-14  0:37         ` Palmer Dabbelt

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