From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com> Subject: [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Date: Wed, 23 Jan 2019 10:25:05 +0100 [thread overview] Message-ID: <20190123092538.8004-3-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 10 +++++++ target/riscv/insn32.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++ target/riscv/translate.c | 31 ++++++++++++---------- 4 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 4072abe3e4..bf0a268033 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1,11 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o + +DECODETREE = $(SRC_PATH)/scripts/decodetree.py + +target/riscv/decode_insn32.inc.c: \ + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode new file mode 100644 index 0000000000..44d4e922b6 --- /dev/null +++ b/target/riscv/insn32.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# Fields: +%rd 7:5 + +# immediates: +%imm_u 12:s20 !function=ex_shift_12 + +# Formats 32: +@u .................... ..... ....... imm=%imm_u %rd + +# *** RV32I Base Instruction Set *** +lui .................... ..... 0110111 @u +auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c new file mode 100644 index 0000000000..9885a8d275 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -0,0 +1,35 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_lui(DisasContext *ctx, arg_lui *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c4a4d8115c..99829a600d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1677,6 +1677,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) } } +#define EX_SH(amount) \ + static int ex_shift_##amount(int imm) \ + { \ + return imm << amount; \ + } +EX_SH(12) + +bool decode_insn32(DisasContext *ctx, uint32_t insn); +/* Include the auto-generated decoder for 32 bit insn */ +#include "decode_insn32.inc.c" +/* Include insn module translation function */ +#include "insn_trans/trans_rvi.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1; @@ -1697,19 +1710,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LUI: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12); - break; - case OPC_RISC_AUIPC: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) + - ctx->base.pc_next); - break; case OPC_RISC_JAL: imm = GET_JAL_IMM(ctx->opcode); gen_jal(env, ctx, rd, imm); @@ -1810,7 +1810,10 @@ static void decode_opc(DisasContext *ctx) } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_RV32_64G(ctx->env, ctx); + if (!decode_insn32(ctx, ctx->opcode)) { + /* fallback to old decoder */ + decode_RV32_64G(ctx->env, ctx); + } } } -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com> Subject: [Qemu-riscv] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Date: Wed, 23 Jan 2019 10:25:05 +0100 [thread overview] Message-ID: <20190123092538.8004-3-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 10 +++++++ target/riscv/insn32.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++ target/riscv/translate.c | 31 ++++++++++++---------- 4 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 4072abe3e4..bf0a268033 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1,11 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o + +DECODETREE = $(SRC_PATH)/scripts/decodetree.py + +target/riscv/decode_insn32.inc.c: \ + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode new file mode 100644 index 0000000000..44d4e922b6 --- /dev/null +++ b/target/riscv/insn32.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# Fields: +%rd 7:5 + +# immediates: +%imm_u 12:s20 !function=ex_shift_12 + +# Formats 32: +@u .................... ..... ....... imm=%imm_u %rd + +# *** RV32I Base Instruction Set *** +lui .................... ..... 0110111 @u +auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c new file mode 100644 index 0000000000..9885a8d275 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -0,0 +1,35 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_lui(DisasContext *ctx, arg_lui *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c4a4d8115c..99829a600d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1677,6 +1677,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) } } +#define EX_SH(amount) \ + static int ex_shift_##amount(int imm) \ + { \ + return imm << amount; \ + } +EX_SH(12) + +bool decode_insn32(DisasContext *ctx, uint32_t insn); +/* Include the auto-generated decoder for 32 bit insn */ +#include "decode_insn32.inc.c" +/* Include insn module translation function */ +#include "insn_trans/trans_rvi.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1; @@ -1697,19 +1710,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LUI: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12); - break; - case OPC_RISC_AUIPC: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) + - ctx->base.pc_next); - break; case OPC_RISC_JAL: imm = GET_JAL_IMM(ctx->opcode); gen_jal(env, ctx, rd, imm); @@ -1810,7 +1810,10 @@ static void decode_opc(DisasContext *ctx) } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_RV32_64G(ctx->env, ctx); + if (!decode_insn32(ctx, ctx->opcode)) { + /* fallback to old decoder */ + decode_RV32_64G(ctx->env, ctx); + } } } -- 2.20.1
next prev parent reply other threads:[~2019-01-23 9:26 UTC|newest] Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` Bastian Koppelmann [this message] 2019-01-23 9:25 ` [Qemu-riscv] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:25 ` [Qemu-devel] " Alistair 2019-01-25 22:25 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:27 ` [Qemu-devel] " Alistair 2019-01-25 22:27 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:28 ` [Qemu-devel] " Alistair 2019-01-25 22:28 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:29 ` [Qemu-devel] " Alistair 2019-01-25 22:29 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply 2019-01-31 17:50 ` [Qemu-riscv] " no-reply 2019-01-31 18:18 ` no-reply 2019-01-31 18:18 ` [Qemu-riscv] " no-reply 2019-01-31 18:22 ` no-reply 2019-01-31 18:22 ` [Qemu-riscv] " no-reply 2019-02-12 23:21 ` Palmer Dabbelt 2019-02-12 23:21 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-devel] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 9:06 ` [Qemu-devel] " Bastian Koppelmann 2019-02-13 9:06 ` [Qemu-riscv] " Bastian Koppelmann 2019-02-13 15:34 ` Palmer Dabbelt 2019-02-13 15:34 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-14 0:37 ` Palmer Dabbelt 2019-02-14 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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