From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Date: Wed, 23 Jan 2019 10:25:31 +0100 [thread overview] Message-ID: <20190123092538.8004-29-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++--------- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++------- target/riscv/translate.c | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index eac79f076f..904ae44968 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) static bool trans_add(DisasContext *ctx, arg_add *a) { - return trans_arith(ctx, a, &tcg_gen_add_tl); + return gen_arith(ctx, a, &tcg_gen_add_tl); } static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return trans_arith(ctx, a, &tcg_gen_sub_tl); + return gen_arith(ctx, a, &tcg_gen_sub_tl); } static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return trans_arith(ctx, a, &gen_slt); + return gen_arith(ctx, a, &gen_slt); } static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return trans_arith(ctx, a, &gen_sltu); + return gen_arith(ctx, a, &gen_sltu); } static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return trans_arith(ctx, a, &tcg_gen_xor_tl); + return gen_arith(ctx, a, &tcg_gen_xor_tl); } static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) static bool trans_or(DisasContext *ctx, arg_or *a) { - return trans_arith(ctx, a, &tcg_gen_or_tl); + return gen_arith(ctx, a, &tcg_gen_or_tl); } static bool trans_and(DisasContext *ctx, arg_and *a) { - return trans_arith(ctx, a, &tcg_gen_and_tl); + return gen_arith(ctx, a, &tcg_gen_and_tl); } #ifdef TARGET_RISCV64 @@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) static bool trans_addw(DisasContext *ctx, arg_addw *a) { - return trans_arith(ctx, a, &gen_addw); + return gen_arith(ctx, a, &gen_addw); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { - return trans_arith(ctx, a, &gen_subw); + return gen_arith(ctx, a, &gen_subw); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index 949f59ddb2..5844d6f5be 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -21,7 +21,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) { - return trans_arith(ctx, a, &tcg_gen_mul_tl); + return gen_arith(ctx, a, &tcg_gen_mul_tl); } static bool trans_mulh(DisasContext *ctx, arg_mulh *a) @@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { - return trans_arith(ctx, a, &gen_mulhsu); + return gen_arith(ctx, a, &gen_mulhsu); } static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) static bool trans_div(DisasContext *ctx, arg_div *a) { - return trans_arith(ctx, a, &gen_div); + return gen_arith(ctx, a, &gen_div); } static bool trans_divu(DisasContext *ctx, arg_divu *a) { - return trans_arith(ctx, a, &gen_divu); + return gen_arith(ctx, a, &gen_divu); } static bool trans_rem(DisasContext *ctx, arg_rem *a) { - return trans_arith(ctx, a, &gen_rem); + return gen_arith(ctx, a, &gen_rem); } static bool trans_remu(DisasContext *ctx, arg_remu *a) { - return trans_arith(ctx, a, &gen_remu); + return gen_arith(ctx, a, &gen_remu); } #ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { - return trans_arith(ctx, a, &gen_mulw); + return gen_arith(ctx, a, &gen_mulw); } static bool trans_divw(DisasContext *ctx, arg_divw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6a722a0045..d0b0fca12b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, #endif -static bool trans_arith(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; source1 = tcg_temp_new(); -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Subject: [Qemu-riscv] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Date: Wed, 23 Jan 2019 10:25:31 +0100 [thread overview] Message-ID: <20190123092538.8004-29-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++--------- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++------- target/riscv/translate.c | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index eac79f076f..904ae44968 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) static bool trans_add(DisasContext *ctx, arg_add *a) { - return trans_arith(ctx, a, &tcg_gen_add_tl); + return gen_arith(ctx, a, &tcg_gen_add_tl); } static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return trans_arith(ctx, a, &tcg_gen_sub_tl); + return gen_arith(ctx, a, &tcg_gen_sub_tl); } static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return trans_arith(ctx, a, &gen_slt); + return gen_arith(ctx, a, &gen_slt); } static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return trans_arith(ctx, a, &gen_sltu); + return gen_arith(ctx, a, &gen_sltu); } static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return trans_arith(ctx, a, &tcg_gen_xor_tl); + return gen_arith(ctx, a, &tcg_gen_xor_tl); } static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) static bool trans_or(DisasContext *ctx, arg_or *a) { - return trans_arith(ctx, a, &tcg_gen_or_tl); + return gen_arith(ctx, a, &tcg_gen_or_tl); } static bool trans_and(DisasContext *ctx, arg_and *a) { - return trans_arith(ctx, a, &tcg_gen_and_tl); + return gen_arith(ctx, a, &tcg_gen_and_tl); } #ifdef TARGET_RISCV64 @@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) static bool trans_addw(DisasContext *ctx, arg_addw *a) { - return trans_arith(ctx, a, &gen_addw); + return gen_arith(ctx, a, &gen_addw); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { - return trans_arith(ctx, a, &gen_subw); + return gen_arith(ctx, a, &gen_subw); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index 949f59ddb2..5844d6f5be 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -21,7 +21,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) { - return trans_arith(ctx, a, &tcg_gen_mul_tl); + return gen_arith(ctx, a, &tcg_gen_mul_tl); } static bool trans_mulh(DisasContext *ctx, arg_mulh *a) @@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { - return trans_arith(ctx, a, &gen_mulhsu); + return gen_arith(ctx, a, &gen_mulhsu); } static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) static bool trans_div(DisasContext *ctx, arg_div *a) { - return trans_arith(ctx, a, &gen_div); + return gen_arith(ctx, a, &gen_div); } static bool trans_divu(DisasContext *ctx, arg_divu *a) { - return trans_arith(ctx, a, &gen_divu); + return gen_arith(ctx, a, &gen_divu); } static bool trans_rem(DisasContext *ctx, arg_rem *a) { - return trans_arith(ctx, a, &gen_rem); + return gen_arith(ctx, a, &gen_rem); } static bool trans_remu(DisasContext *ctx, arg_remu *a) { - return trans_arith(ctx, a, &gen_remu); + return gen_arith(ctx, a, &gen_remu); } #ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { - return trans_arith(ctx, a, &gen_mulw); + return gen_arith(ctx, a, &gen_mulw); } static bool trans_divw(DisasContext *ctx, arg_divw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6a722a0045..d0b0fca12b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, #endif -static bool trans_arith(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; source1 = tcg_temp_new(); -- 2.20.1
next prev parent reply other threads:[~2019-01-23 9:43 UTC|newest] Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:23 ` [Qemu-devel] " Alistair 2019-01-25 22:23 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:25 ` [Qemu-devel] " Alistair 2019-01-25 22:25 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:27 ` [Qemu-devel] " Alistair 2019-01-25 22:27 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` Bastian Koppelmann [this message] 2019-01-23 9:25 ` [Qemu-riscv] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-25 22:28 ` [Qemu-devel] " Alistair 2019-01-25 22:28 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-25 22:29 ` [Qemu-devel] " Alistair 2019-01-25 22:29 ` [Qemu-riscv] " Alistair 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-23 9:25 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply 2019-01-31 17:50 ` [Qemu-riscv] " no-reply 2019-01-31 18:18 ` no-reply 2019-01-31 18:18 ` [Qemu-riscv] " no-reply 2019-01-31 18:22 ` no-reply 2019-01-31 18:22 ` [Qemu-riscv] " no-reply 2019-02-12 23:21 ` Palmer Dabbelt 2019-02-12 23:21 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-devel] " Palmer Dabbelt 2019-02-13 2:15 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-13 9:06 ` [Qemu-devel] " Bastian Koppelmann 2019-02-13 9:06 ` [Qemu-riscv] " Bastian Koppelmann 2019-02-13 15:34 ` Palmer Dabbelt 2019-02-13 15:34 ` [Qemu-riscv] " Palmer Dabbelt 2019-02-14 0:37 ` Palmer Dabbelt 2019-02-14 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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