[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

[Bin Meng]

This series adds QEMU RISC-V 'virt' board target support, with the
hope of helping people easily test U-Boot on RISC-V.

Some existing RISC-V codes have been changed to make it easily to
support new targets. Some spotted coding style issues are fixed.

This series is available at u-boot-x86/riscv-working for testing.

Resend v2 to rebase on top of v2018.09 release with Tom's tree on
github, as the git.denx.de is still out of sync ...

Changes in v2:
- Change Linux kernel entry parameters' type to support 32/64 bit
- new patch to remove CSR read/write defines in encoding.h
- new patch to pass mhartid CSR value to kernel
- new patch to move do_reset() to a common place

Bin Meng (15):
  riscv: kconfig: Normalize architecture name spelling
  riscv: Remove setup.h
  riscv: bootm: Correct the 1st kernel argument to hart id
  riscv: Remove mach type
  riscv: Move the linker script to the CPU root directory
  riscv: Fix coding style issues in the linker script
  riscv: Explicitly pass -march and -mabi to the compiler
  riscv: Add a helper routine to print CPU information
  riscv: Remove CSR read/write defines in encoding.h
  riscv: bootm: Pass mhartid CSR value to kernel
  riscv: Make start.S available for all targets
  riscv: ae350: Clean up mixed tabs and spaces in the dts
  riscv: kconfig: Select DM and OF_CONTROL
  riscv: Add QEMU virt board support
  riscv: Move do_reset() to a common place

 arch/Kconfig                            |   5 +-
 arch/riscv/Kconfig                      |  10 +-
 arch/riscv/Makefile                     |   3 +-
 arch/riscv/config.mk                    |   9 +-
 arch/riscv/cpu/Makefile                 |   7 ++
 arch/riscv/cpu/ax25/Makefile            |   2 -
 arch/riscv/cpu/ax25/cpu.c               |   9 --
 arch/riscv/cpu/cpu.c                    |  49 ++++++++
 arch/riscv/cpu/qemu/Makefile            |   6 +
 arch/riscv/cpu/qemu/cpu.c               |  21 ++++
 arch/riscv/cpu/qemu/dram.c              |  17 +++
 arch/riscv/cpu/{ax25 => }/start.S       |   0
 arch/riscv/cpu/{ax25 => }/u-boot.lds    |  60 +++++-----
 arch/riscv/dts/ae350.dts                | 177 +++++++++++++++--------------
 arch/riscv/include/asm/bootm.h          |  13 ---
 arch/riscv/include/asm/csr.h            | 124 ++++++++++++++++++++
 arch/riscv/include/asm/encoding.h       |  50 +-------
 arch/riscv/include/asm/mach-types.h     |  29 -----
 arch/riscv/include/asm/setup.h          | 194 --------------------------------
 arch/riscv/include/asm/u-boot.h         |   1 -
 arch/riscv/lib/Makefile                 |   1 +
 arch/riscv/lib/bootm.c                  |  20 +---
 arch/riscv/lib/reset.c                  |  14 +++
 board/AndesTech/ax25-ae350/ax25-ae350.c |   2 -
 board/emulation/qemu-riscv/Kconfig      |  21 ++++
 board/emulation/qemu-riscv/MAINTAINERS  |   7 ++
 board/emulation/qemu-riscv/Makefile     |   5 +
 board/emulation/qemu-riscv/qemu-riscv.c |  23 ++++
 cmd/bdinfo.c                            |   1 -
 configs/ax25-ae350_defconfig            |   2 -
 configs/qemu-riscv32_defconfig          |  10 ++
 configs/qemu-riscv64_defconfig          |  11 ++
 doc/README.qemu-riscv                   |  46 ++++++++
 include/configs/qemu-riscv.h            |  21 ++++
 34 files changed, 532 insertions(+), 438 deletions(-)
 create mode 100644 arch/riscv/cpu/Makefile
 create mode 100644 arch/riscv/cpu/cpu.c
 create mode 100644 arch/riscv/cpu/qemu/Makefile
 create mode 100644 arch/riscv/cpu/qemu/cpu.c
 create mode 100644 arch/riscv/cpu/qemu/dram.c
 rename arch/riscv/cpu/{ax25 => }/start.S (100%)
 rename arch/riscv/cpu/{ax25 => }/u-boot.lds (54%)
 delete mode 100644 arch/riscv/include/asm/bootm.h
 create mode 100644 arch/riscv/include/asm/csr.h
 delete mode 100644 arch/riscv/include/asm/mach-types.h
 delete mode 100644 arch/riscv/include/asm/setup.h
 create mode 100644 arch/riscv/lib/reset.c
 create mode 100644 board/emulation/qemu-riscv/Kconfig
 create mode 100644 board/emulation/qemu-riscv/MAINTAINERS
 create mode 100644 board/emulation/qemu-riscv/Makefile
 create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c
 create mode 100644 configs/qemu-riscv32_defconfig
 create mode 100644 configs/qemu-riscv64_defconfig
 create mode 100644 doc/README.qemu-riscv
 create mode 100644 include/configs/qemu-riscv.h

-- 
2.7.4

[U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling

[Bin Meng]

It's RISC-V that is the official name, not RISCV.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/Kconfig       | 2 +-
 arch/riscv/Kconfig | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index bf1b4a9..42c23b5 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -60,7 +60,7 @@ config PPC
 	select SYS_BOOT_GET_KBD
 
 config RISCV
-	bool "riscv architecture"
+	bool "RISC-V architecture"
 	select SUPPORT_OF_CONTROL
 
 config SANDBOX
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 20a43d8..49f87de 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -1,4 +1,4 @@
-menu "RISCV architecture"
+menu "RISC-V architecture"
 	depends on RISCV
 
 config SYS_ARCH
@@ -20,13 +20,13 @@ choice
 	default CPU_RISCV_32
 
 config CPU_RISCV_32
-	bool "RISCV 32 bit"
+	bool "RISC-V 32-bit"
 	select 32BIT
 	help
 	  Choose this option to build an U-Boot for RISCV32 architecture.
 
 config CPU_RISCV_64
-	bool "RISCV 64 bit"
+	bool "RISC-V 64-bit"
 	select 64BIT
 	help
 	  Choose this option to build an U-Boot for RISCV64 architecture.
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h

[Bin Meng]

This was copied from ARM, and does not apply to RISC-V. While we
are here, bootm.h is eventually removed as its content is only
the inclusion of setup.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/include/asm/bootm.h |  13 ---
 arch/riscv/include/asm/setup.h | 194 -----------------------------------------
 arch/riscv/lib/bootm.c         |   1 -
 3 files changed, 208 deletions(-)
 delete mode 100644 arch/riscv/include/asm/bootm.h
 delete mode 100644 arch/riscv/include/asm/setup.h

diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h
deleted file mode 100644
index 6786345..0000000
--- a/arch/riscv/include/asm/bootm.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013, Google Inc.
- *
- * Copyright (C) 2011
- * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
- */
-#ifndef NDS32_BOOTM_H
-#define NDS32_BOOTM_H
-
-#include <asm/setup.h>
-
-#endif
diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h
deleted file mode 100644
index ff8de16..0000000
--- a/arch/riscv/include/asm/setup.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- *  linux/arch/nds32/include/asm/setup.h
- *
- * Copyright (C) 1997-1999 Russell King
- * Copyright (C) 2008 Andes Technology Corporation
- * Copyright (C) 2013 Ken Kuo (ken_kuo at andestech.com)
- * Copyright (C) 2017 Rick Chen (rick at andestech.com)
- *
- *  Structure passed to kernel to tell it about the
- *  hardware it's running on.  See Documentation/arm/Setup
- *  for more info.
- */
-#ifndef __RISCV_SETUP_H
-#define __RISCV_SETUP_H
-
-#define COMMAND_LINE_SIZE 256
-
-/* The list ends with an ATAG_NONE node. */
-#define ATAG_NONE	0x00000000
-
-struct tag_header {
-	u32 size;
-	u32 tag;
-};
-
-/* The list must start with an ATAG_CORE node */
-#define ATAG_CORE	0x54410001
-
-struct tag_core {
-	u32 flags;		/* bit 0 = read-only */
-	u32 pagesize;
-	u32 rootdev;
-};
-
-/* it is allowed to have multiple ATAG_MEM nodes */
-#define ATAG_MEM	0x54410002
-
-struct tag_mem32 {
-	u32	size;
-	u32	start;	/* physical start address */
-};
-
-/* VGA text type displays */
-#define ATAG_VIDEOTEXT	0x54410003
-
-struct tag_videotext {
-	u8		x;
-	u8		y;
-	u16		video_page;
-	u8		video_mode;
-	u8		video_cols;
-	u16		video_ega_bx;
-	u8		video_lines;
-	u8		video_isvga;
-	u16		video_points;
-};
-
-/* describes how the ramdisk will be used in kernel */
-#define ATAG_RAMDISK	0x54410004
-
-struct tag_ramdisk {
-	u32 flags;	/* bit 0 = load, bit 1 = prompt */
-	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
-	u32 start;	/* starting block of floppy-based RAM disk image */
-};
-
-/*
- * this one accidentally used virtual addresses - as such,
- * it's deprecated.
- * describes where the compressed ramdisk image lives (virtual address)
- */
-#define ATAG_INITRD		0x54410005
-
-/* describes where the compressed ramdisk image lives (physical address) */
-#define ATAG_INITRD2	0x54420005
-
-struct tag_initrd {
-	u32 start;	/* physical start address */
-	u32 size;	/* size of compressed ramdisk image in bytes */
-};
-
-/* board serial number. "64 bits should be enough for everybody" */
-#define ATAG_SERIAL		0x54410006
-
-struct tag_serialnr {
-	u32 low;
-	u32 high;
-};
-
-/* board revision */
-#define ATAG_REVISION	0x54410007
-
-struct tag_revision {
-	u32 rev;
-};
-
-/* initial values for vesafb-type framebuffers. see struct screen_info
- * in include/linux/tty.h
- */
-#define ATAG_VIDEOLFB	0x54410008
-
-struct tag_videolfb {
-	u16		lfb_width;
-	u16		lfb_height;
-	u16		lfb_depth;
-	u16		lfb_linelength;
-	u32		lfb_base;
-	u32		lfb_size;
-	u8		red_size;
-	u8		red_pos;
-	u8		green_size;
-	u8		green_pos;
-	u8		blue_size;
-	u8		blue_pos;
-	u8		rsvd_size;
-	u8		rsvd_pos;
-};
-
-/* command line: \0 terminated string */
-#define ATAG_CMDLINE	0x54410009
-
-struct tag_cmdline {
-	char	cmdline[COMMAND_LINE_SIZE];
-};
-
-struct tag {
-	struct tag_header hdr;
-	union {
-		struct tag_core		core;
-		struct tag_mem32	mem;
-		struct tag_videotext	videotext;
-		struct tag_ramdisk	ramdisk;
-		struct tag_initrd	initrd;
-		struct tag_serialnr	serialnr;
-		struct tag_revision	revision;
-		struct tag_videolfb	videolfb;
-		struct tag_cmdline	cmdline;
-	} u;
-};
-
-struct tagtable {
-	u32 tag;
-	int (*parse)(const struct tag *);
-};
-
-#define tag_member_present(_tag, member)				\
-	typeof(_tag) (tag) = (_tag); \
-	((unsigned long)(&((struct tag *)0L)->member + 1)	\
-		<= (tag)->hdr.size * 4)
-
-#define tag_next(_t)	\
-	typeof(_t) (t) = (_t); \
-	((struct tag *)((u32 *)(t) + (t)->hdr.size))
-#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
-
-#define for_each_tag(_t, base) \
-	typeof(_t) (t) = (_t); \
-	for (t = base; t->hdr.size; t = tag_next(t))
-
-#ifdef __KERNEL__
-
-#define __tag __used __attribute__((__section__(".taglist")))
-#define __tagtable(tag, fn) \
-static struct tagtable __tagtable_##fn __tag = { tag, fn }
-
-/*
- * Memory map description
- */
-#define NR_BANKS 8
-
-struct meminfo {
-	int nr_banks;
-	struct {
-		unsigned long start;
-		unsigned long size;
-		int           node;
-	} bank[NR_BANKS];
-};
-
-/*
- * Early command line parameters.
- */
-struct early_params {
-	const char *arg;
-	void (*fn)(char **p);
-};
-
-#define __early_param(name, fn)					\
-static struct early_params __early_##fn __used	\
-__attribute__((__section__("__early_param"))) = { name, fn }
-
-#endif
-#endif
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 2610a57..6662aff 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -11,7 +11,6 @@
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
-#include <asm/bootm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id

[Bin Meng]

The first argument of Linux kernel is the risc-v core hart id,
from which the kernel is booted from. It is not the mach_id,
which seems to be copied from arm.

While we are here, this also changes the Linux kernel entry
parameters' type to support both 32-bit and 64-bit.

Note the hart id is hardcoded to zero for now, and we should
change to fill in it with the value read from mhartid CSR of
the hart which this routine is currently running on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- Change Linux kernel entry parameters' type to support 32/64 bit

 arch/riscv/lib/bootm.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 6662aff..6893108 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob)
 
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
-	bd_t	*bd = gd->bd;
-	char	*s;
-	int	machid = bd->bi_arch_number;
-	void	(*theKernel)(int arch, uint params);
+	void	(*kernel)(ulong hart, void *dtb);
 
 	/*
 	 * allow the PREP bootm subcommand, it is required for bootm to work
@@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 		return 1;
 
-	theKernel = (void (*)(int, uint))images->ep;
-
-	s = env_get("machid");
-	if (s) {
-		machid = simple_strtoul(s, NULL, 16);
-		printf("Using machid 0x%x from environment\n", machid);
-	}
+	kernel = (void (*)(ulong, void *))images->ep;
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
 	debug("## Transferring control to Linux (at address %08lx) ...\n",
-	       (ulong)theKernel);
+	       (ulong)kernel);
 
 	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 #ifdef CONFIG_OF_LIBFDT
@@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 	printf("\nStarting kernel ...\n\n");
 
 	cleanup_before_linux();
+	/* TODO: hardcode the hart id to zero for now */
 	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
-		theKernel(machid, (unsigned long)images->ft_addr);
+		kernel(0, images->ft_addr);
 
 	/* does not return */
 
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type

[Bin Meng]

Since the mach_id is not used by RISC-V, remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/include/asm/mach-types.h     | 29 -----------------------------
 arch/riscv/include/asm/u-boot.h         |  1 -
 board/AndesTech/ax25-ae350/ax25-ae350.c |  2 --
 cmd/bdinfo.c                            |  1 -
 4 files changed, 33 deletions(-)
 delete mode 100644 arch/riscv/include/asm/mach-types.h

diff --git a/arch/riscv/include/asm/mach-types.h b/arch/riscv/include/asm/mach-types.h
deleted file mode 100644
index f219ced..0000000
--- a/arch/riscv/include/asm/mach-types.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-#ifndef __ASM_RISCV_MACH_TYPE_H
-#define __ASM_RISCV_MACH_TYPE_H
-
-#ifndef __ASSEMBLY__
-/* The type of machine we're running on */
-extern unsigned int __machine_arch_type;
-#endif
-
-#define MACH_TYPE_AE350		1
-
-#ifdef CONFIG_ARCH_AE350
-# ifdef machine_arch_type
-#  undef machine_arch_type
-#  define machine_arch_type __machine_arch_type
-# else
-#  define machine_arch_type MACH_TYPE_AE350
-# endif
-# define machine_is_ae350() (machine_arch_type == MACH_TYPE_AE350)
-#else
-# define machine_is_ae350() (1)
-#endif
-
-#endif /* __ASM_RISCV_MACH_TYPE_H */
diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h
index 9e5b32d..3186835 100644
--- a/arch/riscv/include/asm/u-boot.h
+++ b/arch/riscv/include/asm/u-boot.h
@@ -23,7 +23,6 @@
 #include <environment.h>
 
 typedef struct bd_info {
-	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
 	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index fd5aaa1..5f4ca0f 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -4,7 +4,6 @@
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
-#include <asm/mach-types.h>
 #include <common.h>
 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
 #include <netdev.h>
@@ -21,7 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	gd->bd->bi_arch_number = MACH_TYPE_AE350;
 	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
 
 	return 0;
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 397dd15..bc440e4 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -424,7 +424,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	bd_t *bd = gd->bd;
 
-	print_num("arch_number", bd->bi_arch_number);
 	print_bi_boot_params(bd);
 	print_bi_dram(bd);
 	print_eth_ip_addr();
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory

[Bin Meng]

The linker script can be shared by all RISC-V targets. Move it to
a common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/cpu/{ax25 => }/u-boot.lds | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename arch/riscv/cpu/{ax25 => }/u-boot.lds (100%)

diff --git a/arch/riscv/cpu/ax25/u-boot.lds b/arch/riscv/cpu/u-boot.lds
similarity index 100%
rename from arch/riscv/cpu/ax25/u-boot.lds
rename to arch/riscv/cpu/u-boot.lds
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script

[Bin Meng]

There are several coding style issues in the linker script. Fix them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/cpu/u-boot.lds | 58 +++++++++++++++++++++++------------------------
 1 file changed, 28 insertions(+), 30 deletions(-)

diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index c50b964..f414473 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -3,28 +3,27 @@
  * Copyright (C) 2017 Andes Technology Corporation
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
+
 OUTPUT_ARCH("riscv")
 ENTRY(_start)
 
 SECTIONS
 {
 	. = ALIGN(4);
-	.text :
-	{
+	.text : {
 		arch/riscv/cpu/ax25/start.o	(.text)
 	}
 
 	/* This needs to come before *(.text*) */
 	.efi_runtime : {
-                __efi_runtime_start = .;
+		__efi_runtime_start = .;
 		*(.text.efi_runtime*)
 		*(.rodata.efi_runtime*)
 		*(.data.efi_runtime*)
-                __efi_runtime_stop = .;
+		__efi_runtime_stop = .;
 	}
 
-	.text_rest :
-	{
+	.text_rest : {
 		*(.text*)
 	}
 
@@ -39,10 +38,10 @@ SECTIONS
 	. = ALIGN(4);
 
 	.got : {
-	   __got_start = .;
-	   *(.got.plt) *(.got)
-	   __got_end = .;
-    }
+		__got_start = .;
+		*(.got.plt) *(.got)
+		__got_end = .;
+	}
 
 	. = ALIGN(4);
 
@@ -50,41 +49,40 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
-    . = ALIGN(4);
+	. = ALIGN(4);
 
 	.efi_runtime_rel : {
-                __efi_runtime_rel_start = .;
+		__efi_runtime_rel_start = .;
 		*(.rel*.efi_runtime)
 		*(.rel*.efi_runtime.*)
-                __efi_runtime_rel_stop = .;
+		__efi_runtime_rel_stop = .;
 	}
 
-    . = ALIGN(4);
+	. = ALIGN(4);
 
-    /DISCARD/ : { *(.rela.plt*) }
-    .rela.dyn : {
-        __rel_dyn_start = .;
-        *(.rela*)
-        __rel_dyn_end = .;
-    }
+	/DISCARD/ : { *(.rela.plt*) }
+	.rela.dyn : {
+		__rel_dyn_start = .;
+		*(.rela*)
+		__rel_dyn_end = .;
+	}
 
-    . = ALIGN(4);
+	. = ALIGN(4);
 
-    .dynsym : {
-        __dyn_sym_start = .;
-        *(.dynsym)
-        __dyn_sym_end = .;
-    }
+	.dynsym : {
+		__dyn_sym_start = .;
+		*(.dynsym)
+		__dyn_sym_end = .;
+	}
 
-    . = ALIGN(4);
+	. = ALIGN(4);
 
 	_end = .;
 
 	.bss : {
-        __bss_start = .;
-        *(.bss*)
+		__bss_start = .;
+		*(.bss*)
 		. = ALIGN(4);
 		__bss_end = .;
 	}
-
 }
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler

[Bin Meng]

At present the compiler flag against which architecture and abi
variant the riscv image is built for is not explicitly indicated
which means the default compiler configuration is used. But this
does not work if we want to build a different target (eg: 32-bit
riscv images using a toolchain configured for 64-bit riscv).

Fix this by explicitly passing -march and -mabi to the compiler.
Since generically we don't use floating point in U-Boot, specify
the RV[32|64]IMA ISA and software floating ABI.

This also fix some alignment coding style issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/config.mk | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index 219e666..1484887 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -18,12 +18,16 @@ endif
 64bit-emul		:= elf64lriscv
 
 ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS	+= -march=rv32ima -mabi=ilp32
 PLATFORM_LDFLAGS	+= -m $(32bit-emul)
+CFLAGS_EFI		+= -march=rv32ima -mabi=ilp32
 EFI_LDS			:= elf_riscv32_efi.lds
 endif
 
 ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS	+= -march=rv64ima -mabi=lp64
 PLATFORM_LDFLAGS	+= -m $(64bit-emul)
+CFLAGS_EFI		+= -march=rv64ima -mabi=lp64
 EFI_LDS			:= elf_riscv64_efi.lds
 endif
 
@@ -31,8 +35,9 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
 			      -T $(srctree)/examples/standalone/riscv.lds
 
 PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 -ffunction-sections
-LDFLAGS_u-boot += --gc-sections -static -pie
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -gdwarf-2 \
+			   -ffunction-sections
+LDFLAGS_u-boot		+= --gc-sections -static -pie
 
 EFI_CRT0		:= crt0_riscv_efi.o
 EFI_RELOC		:= reloc_riscv_efi.o
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Bin Meng]

This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/Makefile          |   1 +
 arch/riscv/cpu/Makefile      |   5 ++
 arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
 arch/riscv/include/asm/csr.h | 124 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 179 insertions(+)
 create mode 100644 arch/riscv/cpu/Makefile
 create mode 100644 arch/riscv/cpu/cpu.c
 create mode 100644 arch/riscv/include/asm/csr.h

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 084888a..af432e1 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -5,5 +5,6 @@
 
 head-y := arch/riscv/cpu/$(CPU)/start.o
 
+libs-y += arch/riscv/cpu/
 libs-y += arch/riscv/cpu/$(CPU)/
 libs-y += arch/riscv/lib/
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
new file mode 100644
index 0000000..63de163
--- /dev/null
+++ b/arch/riscv/cpu/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
new file mode 100644
index 0000000..ae57fb8
--- /dev/null
+++ b/arch/riscv/cpu/cpu.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/csr.h>
+
+enum {
+	ISA_INVALID = 0,
+	ISA_32BIT,
+	ISA_64BIT,
+	ISA_128BIT
+};
+
+static const char * const isa_bits[] = {
+	[ISA_INVALID] = NULL,
+	[ISA_32BIT]   = "32",
+	[ISA_64BIT]   = "64",
+	[ISA_128BIT]  = "128"
+};
+
+static inline bool supports_extension(char ext)
+{
+	return csr_read(misa) & (1 << (ext - 'a'));
+}
+
+int print_cpuinfo(void)
+{
+	char name[32];
+	char *s = name;
+	int bit;
+
+	s += sprintf(name, "rv");
+	bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
+	s += sprintf(s, isa_bits[bit]);
+
+	supports_extension('i') ? *s++ = 'i' : 'r';
+	supports_extension('m') ? *s++ = 'm' : 'i';
+	supports_extension('a') ? *s++ = 'a' : 's';
+	supports_extension('f') ? *s++ = 'f' : 'c';
+	supports_extension('d') ? *s++ = 'd' : '-';
+	supports_extension('c') ? *s++ = 'c' : 'v';
+	*s++ = '\0';
+
+	printf("CPU:   %s\n", name);
+
+	return 0;
+}
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
new file mode 100644
index 0000000..50fccea
--- /dev/null
+++ b/arch/riscv/include/asm/csr.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/csr.h
+ */
+
+#ifndef _ASM_RISCV_CSR_H
+#define _ASM_RISCV_CSR_H
+
+/* Status register flags */
+#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
+#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
+#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor access User Memory */
+
+#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
+#define SR_FS_OFF	_AC(0x00000000, UL)
+#define SR_FS_INITIAL	_AC(0x00002000, UL)
+#define SR_FS_CLEAN	_AC(0x00004000, UL)
+#define SR_FS_DIRTY	_AC(0x00006000, UL)
+
+#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
+#define SR_XS_OFF	_AC(0x00000000, UL)
+#define SR_XS_INITIAL	_AC(0x00008000, UL)
+#define SR_XS_CLEAN	_AC(0x00010000, UL)
+#define SR_XS_DIRTY	_AC(0x00018000, UL)
+
+#ifndef CONFIG_64BIT
+#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#else
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#endif
+
+/* SATP flags */
+#if __riscv_xlen == 32
+#define SATP_PPN	_AC(0x003FFFFF, UL)
+#define SATP_MODE_32	_AC(0x80000000, UL)
+#define SATP_MODE	SATP_MODE_32
+#else
+#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39	_AC(0x8000000000000000, UL)
+#define SATP_MODE	SATP_MODE_39
+#endif
+
+/* Interrupt Enable and Interrupt Pending flags */
+#define SIE_SSIE	_AC(0x00000002, UL) /* Software Interrupt Enable */
+#define SIE_STIE	_AC(0x00000020, UL) /* Timer Interrupt Enable */
+
+#define EXC_INST_MISALIGNED	0
+#define EXC_INST_ACCESS		1
+#define EXC_BREAKPOINT		3
+#define EXC_LOAD_ACCESS		5
+#define EXC_STORE_ACCESS	7
+#define EXC_SYSCALL		8
+#define EXC_INST_PAGE_FAULT	12
+#define EXC_LOAD_PAGE_FAULT	13
+#define EXC_STORE_PAGE_FAULT	15
+
+#ifndef __ASSEMBLY__
+
+#define csr_swap(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrw %0, " #csr ", %1"		\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_read(csr)						\
+({								\
+	register unsigned long __v;				\
+	__asm__ __volatile__ ("csrr %0, " #csr			\
+			      : "=r" (__v) :			\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_write(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrw " #csr ", %0"		\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrs %0, " #csr ", %1"		\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrs " #csr ", %0"		\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_clear(csr, val)				\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrc %0, " #csr ", %1"		\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_clear(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrc " #csr ", %0"		\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_CSR_H */
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h

[Bin Meng]

There is no reason to keep two versions of CSR read/write defines
in encoding.h. We already have one set of defines in csr.h, which
is from Linux kernel, and let's drop the one in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- new patch to remove CSR read/write defines in encoding.h

 arch/riscv/include/asm/encoding.h | 50 ++++-----------------------------------
 1 file changed, 4 insertions(+), 46 deletions(-)

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index f237a72..9ea50ce 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -128,6 +128,7 @@
 	((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 
 #ifdef __riscv
+
 #ifdef CONFIG_64BIT
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
@@ -141,53 +142,10 @@
 # define MCAUSE_INT MCAUSE32_INT
 # define MCAUSE_CAUSE MCAUSE32_CAUSE
 #endif
+
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
 
-#ifndef __ASSEMBLER__
-
-#ifdef __GNUC__
-
-#define read_csr(reg) ({ unsigned long __tmp; \
-	asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
-	__tmp; })
-
-#define write_csr(reg, _val) ({ \
-typeof(_val) (val) = (_val); \
-if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
-else \
-	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
-
-#define swap_csr(reg, _val) ({ unsigned long __tmp; \
-typeof(_val) (val) = (_val); \
-if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-	asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
-else \
-	asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
-	__tmp; })
-
-#define set_csr(reg, _bit) ({ unsigned long __tmp; \
-typeof(_bit) (bit) = (_bit); \
-if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-else \
-	asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-	__tmp; })
-
-#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
-typeof(_bit) (bit) = (_bit); \
-if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-else \
-	asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-	__tmp; })
-
-#define rdtime() read_csr(time)
-#define rdcycle() read_csr(cycle)
-#define rdinstret() read_csr(instret)
+#endif /* __riscv */
 
-#endif
-#endif
-#endif
-#endif
+#endif /* RISCV_CSR_ENCODING_H */
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel

[Bin Meng]

So far this is hardcoded to zero, and we should read the value from
mhartid CSR and pass it to Linux kernel.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- new patch to pass mhartid CSR value to kernel

 arch/riscv/lib/bootm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 6893108..a7a9fb9 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -11,6 +11,7 @@
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
+#include <asm/csr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 	printf("\nStarting kernel ...\n\n");
 
 	cleanup_before_linux();
-	/* TODO: hardcode the hart id to zero for now */
+
 	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
-		kernel(0, images->ft_addr);
+		kernel(csr_read(mhartid), images->ft_addr);
 
 	/* does not return */
 
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets

[Bin Meng]

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/Makefile               | 2 +-
 arch/riscv/cpu/Makefile           | 2 ++
 arch/riscv/cpu/ax25/Makefile      | 2 --
 arch/riscv/cpu/{ax25 => }/start.S | 0
 arch/riscv/cpu/u-boot.lds         | 2 +-
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/riscv/cpu/{ax25 => }/start.S (100%)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index af432e1..8fb6a88 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,7 +3,7 @@
 # Copyright (C) 2017 Andes Technology Corporation.
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-head-y := arch/riscv/cpu/$(CPU)/start.o
+head-y := arch/riscv/cpu/start.o
 
 libs-y += arch/riscv/cpu/
 libs-y += arch/riscv/cpu/$(CPU)/
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 63de163..2cc6757 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -2,4 +2,6 @@
 #
 # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 
+extra-y = start.o
+
 obj-y += cpu.o
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
index c3f164c..2ab0342 100644
--- a/arch/riscv/cpu/ax25/Makefile
+++ b/arch/riscv/cpu/ax25/Makefile
@@ -3,6 +3,4 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-extra-y	= start.o
-
 obj-y	:= cpu.o
diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/start.S
similarity index 100%
rename from arch/riscv/cpu/ax25/start.S
rename to arch/riscv/cpu/start.S
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index f414473..11bc4a7 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -11,7 +11,7 @@ SECTIONS
 {
 	. = ALIGN(4);
 	.text : {
-		arch/riscv/cpu/ax25/start.o	(.text)
+		arch/riscv/cpu/start.o	(.text)
 	}
 
 	/* This needs to come before *(.text*) */
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts

[Bin Meng]

There are quite a lot of mixed tabs and spaces in the ae350.dts.
Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/dts/ae350.dts | 177 ++++++++++++++++++++++++-----------------------
 1 file changed, 90 insertions(+), 87 deletions(-)

diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
index 2927e41..4717ae8 100644
--- a/arch/riscv/dts/ae350.dts
+++ b/arch/riscv/dts/ae350.dts
@@ -1,144 +1,147 @@
 /dts-v1/;
 
 / {
-  #address-cells = <2>;
-  #size-cells = <2>;
-  compatible = "andestech,ax25";
-  model = "andestech,ax25";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "andestech,ax25";
+	model = "andestech,ax25";
 
 	aliases {
 		uart0 = &serial0;
 		spi0 = &spi;
-	} ;
+	};
 
 	chosen {
 		bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
 		stdout-path = "uart0:38400n8";
-  };
-
-  cpus {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    timebase-frequency = <10000000>;
-    CPU0: cpu at 0 {
-      device_type = "cpu";
-      reg = <0>;
-      status = "okay";
-      compatible = "riscv";
-      riscv,isa = "rv64imafdc";
-      mmu-type = "riscv,sv39";
-      clock-frequency = <60000000>;
-      CPU0_intc: interrupt-controller {
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        compatible = "riscv,cpu-intc";
-      };
-    };
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <10000000>;
+
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+
+			CPU0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
 	};
 
 	memory at 0 {
 		device_type = "memory";
-    reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x00000000 0x0 0x40000000>;
 	};
 
-  soc {
-    #address-cells = <2>;
-    #size-cells = <2>;
-    compatible = "andestech,riscv-ae350-soc";
-    ranges;
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "andestech,riscv-ae350-soc";
+		ranges;
 	};
 
-  plmt0 at e6000000 {
-    compatible = "riscv,plmt0";
-    interrupts-extended = <&CPU0_intc 7>;
-    reg = <0x0 0xe6000000 0x0 0x100000>;
-		};
+	plmt0 at e6000000 {
+		compatible = "riscv,plmt0";
+		interrupts-extended = <&CPU0_intc 7>;
+		reg = <0x0 0xe6000000 0x0 0x100000>;
+	};
 
-  plic0: interrupt-controller at e4000000 {
-    compatible = "riscv,plic0";
-    #address-cells = <2>;
-    #interrupt-cells = <2>;
-    interrupt-controller;
-    reg = <0x0 0xe4000000 0x0 0x2000000>;
-    riscv,ndev=<31>;
-    interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+	plic0: interrupt-controller at e4000000 {
+		compatible = "riscv,plic0";
+		#address-cells = <2>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x0 0xe4000000 0x0 0x2000000>;
+		riscv,ndev=<31>;
+		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
 	};
 
-  plic1: interrupt-controller at e6400000 {
-    compatible = "riscv,plic1";
-    #address-cells = <2>;
-    #interrupt-cells = <2>;
+	plic1: interrupt-controller at e6400000 {
+		compatible = "riscv,plic1";
+		#address-cells = <2>;
+		#interrupt-cells = <2>;
 		interrupt-controller;
-    reg = <0x0 0xe6400000 0x0 0x400000>;
-    riscv,ndev=<1>;
-    interrupts-extended = <&CPU0_intc 3>;
-  };
+		reg = <0x0 0xe6400000 0x0 0x400000>;
+		riscv,ndev=<1>;
+		interrupts-extended = <&CPU0_intc 3>;
+	};
 
-  spiclk: virt_100mhz {
-    #clock-cells = <0>;
-    compatible = "fixed-clock";
-    clock-frequency = <100000000>;
-  };
+	spiclk: virt_100mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
 
-  timer0: timer at f0400000 {
-    compatible = "andestech,atcpit100";
-    reg = <0x0 0xf0400000 0x0 0x1000>;
-    clock-frequency = <40000000>;
-    interrupts = <3 4>;
-    interrupt-parent = <&plic0>;
+	timer0: timer at f0400000 {
+		compatible = "andestech,atcpit100";
+		reg = <0x0 0xf0400000 0x0 0x1000>;
+		clock-frequency = <40000000>;
+		interrupts = <3 4>;
+		interrupt-parent = <&plic0>;
 	};
 
 	serial0: serial at f0300000 {
 		compatible = "andestech,uart16550", "ns16550a";
-    reg = <0x0 0xf0300000 0x0 0x1000>;
-    interrupts = <9 4>;
+		reg = <0x0 0xf0300000 0x0 0x1000>;
+		interrupts = <9 4>;
 		clock-frequency = <19660800>;
 		reg-shift = <2>;
 		reg-offset = <32>;
 		no-loopback-test = <1>;
-    interrupt-parent = <&plic0>;
+		interrupt-parent = <&plic0>;
 	};
 
 	mac0: mac at e0100000 {
 		compatible = "andestech,atmac100";
-    reg = <0x0 0xe0100000 0x0 0x1000>;
-    interrupts = <19 4>;
-    interrupt-parent = <&plic0>;
+		reg = <0x0 0xe0100000 0x0 0x1000>;
+		interrupts = <19 4>;
+		interrupt-parent = <&plic0>;
 	};
 
 	mmc0: mmc at f0e00000 {
-    compatible = "andestech,atfsdc010";
+		compatible = "andestech,atfsdc010";
 		max-frequency = <100000000>;
-    clock-freq-min-max = <400000 100000000>;
+		clock-freq-min-max = <400000 100000000>;
 		fifo-depth = <0x10>;
-    reg = <0x0 0xf0e00000 0x0 0x1000>;
-    interrupts = <18 4>;
+		reg = <0x0 0xf0e00000 0x0 0x1000>;
+		interrupts = <18 4>;
 		cap-sd-highspeed;
-    interrupt-parent = <&plic0>;
+		interrupt-parent = <&plic0>;
 	};
 
-  smc0: smc at e0400000 {
-    compatible = "andestech,atfsmc020";
-    reg = <0x0 0xe0400000 0x0 0x1000>;
-  };
+	smc0: smc at e0400000 {
+		compatible = "andestech,atfsmc020";
+		reg = <0x0 0xe0400000 0x0 0x1000>;
+	};
 
-  nor at 0,0 {
-    compatible = "cfi-flash";
-    reg = <0x0 0x88000000 0x0 0x1000>;
-    bank-width = <2>;
-    device-width = <1>;
-  };
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0x0 0x88000000 0x0 0x1000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
 
 	spi: spi at f0b00000 {
 		compatible = "andestech,atcspi200";
-    reg = <0x0 0xf0b00000 0x0 0x1000>;
+		reg = <0x0 0xf0b00000 0x0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		num-cs = <1>;
 		clocks = <&spiclk>;
 		interrupts = <3 4>;
-    interrupt-parent = <&plic0>;
-			flash at 0 {
+		interrupt-parent = <&plic0>;
+
+		flash at 0 {
 			compatible = "spi-flash";
 			spi-max-frequency = <50000000>;
 			reg = <0>;
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL

[Bin Meng]

RISC-V is a pretty new architecture and should support DM and
OF_CONTROL by default.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/Kconfig                 | 3 +++
 configs/ax25-ae350_defconfig | 2 --
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 42c23b5..01330a4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -62,6 +62,9 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select SUPPORT_OF_CONTROL
+	select OF_CONTROL
+	select DM
+	imply CMD_DM
 
 config SANDBOX
 	bool "Sandbox"
diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig
index d64f078..ebcc52e 100644
--- a/configs/ax25-ae350_defconfig
+++ b/configs/ax25-ae350_defconfig
@@ -15,12 +15,10 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support

[Bin Meng]

This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2: None

 arch/riscv/Kconfig                      |  4 +++
 arch/riscv/cpu/qemu/Makefile            |  6 +++++
 arch/riscv/cpu/qemu/cpu.c               | 29 +++++++++++++++++++++
 arch/riscv/cpu/qemu/dram.c              | 17 ++++++++++++
 board/emulation/qemu-riscv/Kconfig      | 21 +++++++++++++++
 board/emulation/qemu-riscv/MAINTAINERS  |  7 +++++
 board/emulation/qemu-riscv/Makefile     |  5 ++++
 board/emulation/qemu-riscv/qemu-riscv.c | 23 +++++++++++++++++
 configs/qemu-riscv32_defconfig          | 10 +++++++
 configs/qemu-riscv64_defconfig          | 11 ++++++++
 doc/README.qemu-riscv                   | 46 +++++++++++++++++++++++++++++++++
 include/configs/qemu-riscv.h            | 21 +++++++++++++++
 12 files changed, 200 insertions(+)
 create mode 100644 arch/riscv/cpu/qemu/Makefile
 create mode 100644 arch/riscv/cpu/qemu/cpu.c
 create mode 100644 arch/riscv/cpu/qemu/dram.c
 create mode 100644 board/emulation/qemu-riscv/Kconfig
 create mode 100644 board/emulation/qemu-riscv/MAINTAINERS
 create mode 100644 board/emulation/qemu-riscv/Makefile
 create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c
 create mode 100644 configs/qemu-riscv32_defconfig
 create mode 100644 configs/qemu-riscv64_defconfig
 create mode 100644 doc/README.qemu-riscv
 create mode 100644 include/configs/qemu-riscv.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 49f87de..168ca3d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,9 +11,13 @@ choice
 config TARGET_AX25_AE350
 	bool "Support ax25-ae350"
 
+config TARGET_QEMU_VIRT
+	bool "Support QEMU Virt Board"
+
 endchoice
 
 source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/emulation/qemu-riscv/Kconfig"
 
 choice
 	prompt "CPU selection"
diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/qemu/Makefile
new file mode 100644
index 0000000..258e462
--- /dev/null
+++ b/arch/riscv/cpu/qemu/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
new file mode 100644
index 0000000..a064639
--- /dev/null
+++ b/arch/riscv/cpu/qemu/cpu.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	/* turn off I/D-cache */
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("reset unsupported yet\n");
+
+	return 0;
+}
diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c
new file mode 100644
index 0000000..84d87d2
--- /dev/null
+++ b/arch/riscv/cpu/qemu/dram.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
new file mode 100644
index 0000000..029f5efb
--- /dev/null
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_QEMU_VIRT
+
+config SYS_BOARD
+	default "qemu-riscv"
+
+config SYS_VENDOR
+	default "emulation"
+
+config SYS_CPU
+	default "qemu"
+
+config SYS_CONFIG_NAME
+	default "qemu-riscv"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
new file mode 100644
index 0000000..3c6eb4f
--- /dev/null
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -0,0 +1,7 @@
+QEMU RISC-V 'VIRT' BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-riscv/
+F:	include/configs/qemu-riscv.h
+F:	configs/qemu-riscv32_defconfig
+F:	configs/qemu-riscv64_defconfig
diff --git a/board/emulation/qemu-riscv/Makefile b/board/emulation/qemu-riscv/Makefile
new file mode 100644
index 0000000..3f29b90
--- /dev/null
+++ b/board/emulation/qemu-riscv/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= qemu-riscv.o
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
new file mode 100644
index 0000000..041e716
--- /dev/null
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+#define MROM_FDT_ADDR	0x1020
+
+int board_init(void)
+{
+	return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	/*
+	 * QEMU loads a generated DTB for us immediately
+	 * after the reset vectors in the MROM
+	 */
+	return (void *)MROM_FDT_ADDR;
+}
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
new file mode 100644
index 0000000..cbd2c91
--- /dev/null
+++ b/configs/qemu-riscv32_defconfig
@@ -0,0 +1,10 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_OF_BOARD=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
new file mode 100644
index 0000000..af8b307
--- /dev/null
+++ b/configs/qemu-riscv64_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_CPU_RISCV_64=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_OF_BOARD=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
diff --git a/doc/README.qemu-riscv b/doc/README.qemu-riscv
new file mode 100644
index 0000000..e2e4804
--- /dev/null
+++ b/doc/README.qemu-riscv
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+U-Boot on QEMU's 'virt' machine on RISC-V
+=========================================
+
+QEMU for RISC-V supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit 64-bit targets are supported.
+
+The QEMU virt machine models a generic RISC-V virtual machine with support for
+the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
+16550A UART devices in addition to VirtIO and it also uses device-tree to pass
+configuration information to guest software. It implements RISC-V privileged
+architecture spec v1.10.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+- For 32-bit RISC-V:
+    make qemu-riscv32_defconfig
+    make
+
+- For 64-bit RISC-V:
+    make qemu-riscv64_defconfig
+    make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+- For 32-bit RISC-V:
+    qemu-system-riscv32 -nographic -machine virt -kernel u-boot
+
+- For 64-bit RISC-V:
+    qemu-system-riscv64 -nographic -machine virt -kernel u-boot
+
+The commands above create targets with 128MiB memory by default.
+A freely configurable amount of RAM can be created via the '-m'
+parameter. For example, '-m 2G' creates 2GiB memory for the target,
+and the memory node in the embedded DTB created by QEMU reflects
+the new setting.
+
+These have been tested in QEMU 3.0.0.
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
new file mode 100644
index 0000000..d279c23
--- /dev/null
+++ b/include/configs/qemu-riscv.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_8M
+
+/* Environment options */
+#define CONFIG_ENV_SIZE			SZ_4K
+
+#endif /* __CONFIG_H */
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Bin Meng]

We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- new patch to move do_reset() to a common place

 arch/riscv/cpu/ax25/cpu.c |  9 ---------
 arch/riscv/cpu/qemu/cpu.c |  8 --------
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/reset.c    | 14 ++++++++++++++
 4 files changed, 15 insertions(+), 17 deletions(-)
 create mode 100644 arch/riscv/lib/reset.c

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index ab05b57..fddcc15 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -6,9 +6,6 @@
 
 /* CPU specific code */
 #include <common.h>
-#include <command.h>
-#include <watchdog.h>
-#include <asm/cache.h>
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -24,9 +21,3 @@ int cleanup_before_linux(void)
 
 	return 0;
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	disable_interrupts();
-	panic("ax25-ae350 wdt not support yet.\n");
-}
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
index a064639..6c7a327 100644
--- a/arch/riscv/cpu/qemu/cpu.c
+++ b/arch/riscv/cpu/qemu/cpu.c
@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <command.h>
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -20,10 +19,3 @@ int cleanup_before_linux(void)
 
 	return 0;
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	printf("reset unsupported yet\n");
-
-	return 0;
-}
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index cc562f9..b58db89 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o
 obj-y	+= interrupts.o
+obj-y	+= reset.o
 obj-y   += setjmp.o
 
 # For building EFI apps
diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
new file mode 100644
index 0000000..5d9b99c
--- /dev/null
+++ b/arch/riscv/lib/reset.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("reset unsupported yet\n");
+
+	return 0;
+}
-- 
2.7.4

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

[Bin Meng]

Hi Rick,

On Tue, Sep 11, 2018 at 12:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This series adds QEMU RISC-V 'virt' board target support, with the
> hope of helping people easily test U-Boot on RISC-V.
>
> Some existing RISC-V codes have been changed to make it easily to
> support new targets. Some spotted coding style issues are fixed.
>
> This series is available at u-boot-x86/riscv-working for testing.
>
> Resend v2 to rebase on top of v2018.09 release with Tom's tree on
> github, as the git.denx.de is still out of sync ...
>
> Changes in v2:
> - Change Linux kernel entry parameters' type to support 32/64 bit
> - new patch to remove CSR read/write defines in encoding.h
> - new patch to pass mhartid CSR value to kernel
> - new patch to move do_reset() to a common place

Any comments for the v2?

Regards,
Bin

[U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> It's RISC-V that is the official name, not RISCV.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This was copied from ARM, and does not apply to RISC-V. While we
> are here, bootm.h is eventually removed as its content is only
> the inclusion of setup.h.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The first argument of Linux kernel is the risc-v core hart id,
> from which the kernel is booted from. It is not the mach_id,
> which seems to be copied from arm.
> 
> While we are here, this also changes the Linux kernel entry
> parameters' type to support both 32-bit and 64-bit.
> 
> Note the hart id is hardcoded to zero for now, and we should
> change to fill in it with the value read from mhartid CSR of
> the hart which this routine is currently running on.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Since the mach_id is not used by RISC-V, remove it.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The linker script can be shared by all RISC-V targets. Move it to
> a common place.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are several coding style issues in the linker script. Fix them.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> At present the compiler flag against which architecture and abi
> variant the riscv image is built for is not explicitly indicated
> which means the default compiler configuration is used. But this
> does not work if we want to build a different target (eg: 32-bit
> riscv images using a toolchain configured for 64-bit riscv).
> 
> Fix this by explicitly passing -march and -mabi to the compiler.
> Since generically we don't use floating point in U-Boot, specify
> the RV[32|64]IMA ISA and software floating ABI.
> 
> This also fix some alignment coding style issues.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds a helper routine to print CPU information. Currently
> it prints all the instruction set extensions that the processor
> core supports.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
> Changes in v2: None
> 
>  arch/riscv/Makefile          |   1 +
>  arch/riscv/cpu/Makefile      |   5 ++
>  arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
>  arch/riscv/include/asm/csr.h | 124
> +++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 179 insertions(+)
>  create mode 100644 arch/riscv/cpu/Makefile
>  create mode 100644 arch/riscv/cpu/cpu.c
>  create mode 100644 arch/riscv/include/asm/csr.h
> 
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 084888a..af432e1 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -5,5 +5,6 @@
>  
>  head-y := arch/riscv/cpu/$(CPU)/start.o
>  
> +libs-y += arch/riscv/cpu/
>  libs-y += arch/riscv/cpu/$(CPU)/
>  libs-y += arch/riscv/lib/
> diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
> new file mode 100644
> index 0000000..63de163
> --- /dev/null
> +++ b/arch/riscv/cpu/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> +
> +obj-y += cpu.o
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> new file mode 100644
> index 0000000..ae57fb8
> --- /dev/null
> +++ b/arch/riscv/cpu/cpu.c
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> + */
> +
> +#include <common.h>
> +#include <asm/csr.h>
> +
> +enum {
> +	ISA_INVALID = 0,
> +	ISA_32BIT,
> +	ISA_64BIT,
> +	ISA_128BIT
> +};
> +
> +static const char * const isa_bits[] = {
> +	[ISA_INVALID] = NULL,
> +	[ISA_32BIT]   = "32",
> +	[ISA_64BIT]   = "64",
> +	[ISA_128BIT]  = "128"
> +};
> +
> +static inline bool supports_extension(char ext)
> +{
> +	return csr_read(misa) & (1 << (ext - 'a'));
> +}
> +
> +int print_cpuinfo(void)
> +{
> +	char name[32];
> +	char *s = name;
> +	int bit;
> +
> +	s += sprintf(name, "rv");
> +	bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
> +	s += sprintf(s, isa_bits[bit]);
> +
> +	supports_extension('i') ? *s++ = 'i' : 'r';
> +	supports_extension('m') ? *s++ = 'm' : 'i';
> +	supports_extension('a') ? *s++ = 'a' : 's';
> +	supports_extension('f') ? *s++ = 'f' : 'c';
> +	supports_extension('d') ? *s++ = 'd' : '-';
> +	supports_extension('c') ? *s++ = 'c' : 'v';
> +	*s++ = '\0';

Why are you not using the ISA string "riscv,isa" from the device tree?
This way, the code is not limited to machine mode and we do not have
update it if the set of extensions to check for changes.

Thanks,
Lukas

> +
> +	printf("CPU:   %s\n", name);
> +
> +	return 0;
> +}
> diff --git a/arch/riscv/include/asm/csr.h
> b/arch/riscv/include/asm/csr.h
> new file mode 100644
> index 0000000..50fccea
> --- /dev/null
> +++ b/arch/riscv/include/asm/csr.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2015 Regents of the University of California
> + *
> + * Taken from Linux arch/riscv/include/asm/csr.h
> + */
> +
> +#ifndef _ASM_RISCV_CSR_H
> +#define _ASM_RISCV_CSR_H
> +
> +/* Status register flags */
> +#define SR_SIE		_AC(0x00000002, UL) /* Supervisor
> Interrupt Enable */
> +#define SR_SPIE		_AC(0x00000020, UL) /* Previous
> Supervisor IE */
> +#define SR_SPP		_AC(0x00000100, UL) /* Previously
> Supervisor */
> +#define SR_SUM		_AC(0x00040000, UL) /* Supervisor
> access User Memory */
> +
> +#define SR_FS		_AC(0x00006000, UL) /* Floating-point
> Status */
> +#define SR_FS_OFF	_AC(0x00000000, UL)
> +#define SR_FS_INITIAL	_AC(0x00002000, UL)
> +#define SR_FS_CLEAN	_AC(0x00004000, UL)
> +#define SR_FS_DIRTY	_AC(0x00006000, UL)
> +
> +#define SR_XS		_AC(0x00018000, UL) /* Extension Status
> */
> +#define SR_XS_OFF	_AC(0x00000000, UL)
> +#define SR_XS_INITIAL	_AC(0x00008000, UL)
> +#define SR_XS_CLEAN	_AC(0x00010000, UL)
> +#define SR_XS_DIRTY	_AC(0x00018000, UL)
> +
> +#ifndef CONFIG_64BIT
> +#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
> +#else
> +#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS
> dirty */
> +#endif
> +
> +/* SATP flags */
> +#if __riscv_xlen == 32
> +#define SATP_PPN	_AC(0x003FFFFF, UL)
> +#define SATP_MODE_32	_AC(0x80000000, UL)
> +#define SATP_MODE	SATP_MODE_32
> +#else
> +#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
> +#define SATP_MODE_39	_AC(0x8000000000000000, UL)
> +#define SATP_MODE	SATP_MODE_39
> +#endif
> +
> +/* Interrupt Enable and Interrupt Pending flags */
> +#define SIE_SSIE	_AC(0x00000002, UL) /* Software Interrupt
> Enable */
> +#define SIE_STIE	_AC(0x00000020, UL) /* Timer Interrupt Enable
> */
> +
> +#define EXC_INST_MISALIGNED	0
> +#define EXC_INST_ACCESS		1
> +#define EXC_BREAKPOINT		3
> +#define EXC_LOAD_ACCESS		5
> +#define EXC_STORE_ACCESS	7
> +#define EXC_SYSCALL		8
> +#define EXC_INST_PAGE_FAULT	12
> +#define EXC_LOAD_PAGE_FAULT	13
> +#define EXC_STORE_PAGE_FAULT	15
> +
> +#ifndef __ASSEMBLY__
> +
> +#define csr_swap(csr, val)					\
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrrw %0, " #csr ", %1"		\
> +			      : "=r" (__v) : "rK" (__v)		\
> +			      : "memory");			\
> +	__v;							\
> +})
> +
> +#define csr_read(csr)						
> \
> +({								\
> +	register unsigned long __v;				\
> +	__asm__ __volatile__ ("csrr %0, " #csr			\
> +			      : "=r" (__v) :			\
> +			      : "memory");			\
> +	__v;							\
> +})
> +
> +#define csr_write(csr, val)					\
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrw " #csr ", %0"		\
> +			      : : "rK" (__v)			\
> +			      : "memory");			\
> +})
> +
> +#define csr_read_set(csr, val)					
> \
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrrs %0, " #csr ", %1"		\
> +			      : "=r" (__v) : "rK" (__v)		\
> +			      : "memory");			\
> +	__v;							\
> +})
> +
> +#define csr_set(csr, val)					\
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrs " #csr ", %0"		\
> +			      : : "rK" (__v)			\
> +			      : "memory");			\
> +})
> +
> +#define csr_read_clear(csr, val)				\
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrrc %0, " #csr ", %1"		\
> +			      : "=r" (__v) : "rK" (__v)		\
> +			      : "memory");			\
> +	__v;							\
> +})
> +
> +#define csr_clear(csr, val)					\
> +({								\
> +	unsigned long __v = (unsigned long)(val);		\
> +	__asm__ __volatile__ ("csrc " #csr ", %0"		\
> +			      : : "rK" (__v)			\
> +			      : "memory");			\
> +})
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_RISCV_CSR_H */

[U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There is no reason to keep two versions of CSR read/write defines
> in encoding.h. We already have one set of defines in csr.h, which
> is from Linux kernel, and let's drop the one in encoding.h.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> So far this is hardcoded to zero, and we should read the value from
> mhartid CSR and pass it to Linux kernel.
> 
> Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
> common for all RISC-V targets.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are quite a lot of mixed tabs and spaces in the ae350.dts.
> Clean them up.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL

[Auer, Lukas]

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> RISC-V is a pretty new architecture and should support DM and
> OF_CONTROL by default.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds QEMU RISC-V 'virt' board target support, with the hope of
> helping people easily test U-Boot on RISC-V.
> 
> The QEMU virt machine models a generic RISC-V virtual machine with
> support for the VirtIO standard networking and block storage devices.
> It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
> it also uses device-tree to pass configuration information to guest
> software. It implements RISC-V privileged architecture spec v1.10.
> 
> Both 32-bit and 64-bit builds are supported. Support is pretty much
> preliminary, only booting to U-Boot shell with the UART driver on
> a single core. Booting Linux is not supported yet.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> ---

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[snip]

> 
> diff --git a/board/emulation/qemu-riscv/Kconfig
> b/board/emulation/qemu-riscv/Kconfig
> new file mode 100644
> index 0000000..029f5efb
> --- /dev/null
> +++ b/board/emulation/qemu-riscv/Kconfig
> @@ -0,0 +1,21 @@
> +if TARGET_QEMU_VIRT
> +
> +config SYS_BOARD
> +	default "qemu-riscv"
> +
> +config SYS_VENDOR
> +	default "emulation"
> +
> +config SYS_CPU
> +	default "qemu"
> +
> +config SYS_CONFIG_NAME
> +	default "qemu-riscv"
> +
> +config SYS_TEXT_BASE
> +	default 0x80000000
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +	def_bool y
> +

Out of curiosity, what is BOARD_SPECIFIC_OPTIONS used for? I see that
other boards have included it as well, but I don't see it actually used
anywhere.

Thanks,
Lukas

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> We don't have a reset method on any RISC-V board yet. Instead of
> adding the same 'unsupported' message for each CPU variant it might
> make more sense to add a generic do_reset function for all CPU
> variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).
> 
> Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> ---
> 
> Changes in v2:
> - new patch to move do_reset() to a common place
> 
>  arch/riscv/cpu/ax25/cpu.c |  9 ---------
>  arch/riscv/cpu/qemu/cpu.c |  8 --------
>  arch/riscv/lib/Makefile   |  1 +
>  arch/riscv/lib/reset.c    | 14 ++++++++++++++
>  4 files changed, 15 insertions(+), 17 deletions(-)
>  create mode 100644 arch/riscv/lib/reset.c
> 
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> index ab05b57..fddcc15 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -6,9 +6,6 @@
>  
>  /* CPU specific code */
>  #include <common.h>
> -#include <command.h>
> -#include <watchdog.h>
> -#include <asm/cache.h>
>  
>  /*
>   * cleanup_before_linux() is called just before we call linux
> @@ -24,9 +21,3 @@ int cleanup_before_linux(void)
>  
>  	return 0;
>  }
> -
> -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[])
> -{
> -	disable_interrupts();
> -	panic("ax25-ae350 wdt not support yet.\n");
> -}
> diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
> index a064639..6c7a327 100644
> --- a/arch/riscv/cpu/qemu/cpu.c
> +++ b/arch/riscv/cpu/qemu/cpu.c
> @@ -4,7 +4,6 @@
>   */
>  
>  #include <common.h>
> -#include <command.h>
>  
>  /*
>   * cleanup_before_linux() is called just before we call linux
> @@ -20,10 +19,3 @@ int cleanup_before_linux(void)
>  
>  	return 0;
>  }
> -
> -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[])
> -{
> -	printf("reset unsupported yet\n");
> -
> -	return 0;
> -}
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index cc562f9..b58db89 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
>  obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y	+= cache.o
>  obj-y	+= interrupts.o
> +obj-y	+= reset.o
>  obj-y   += setjmp.o
>  
>  # For building EFI apps
> diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> new file mode 100644
> index 0000000..5d9b99c
> --- /dev/null
> +++ b/arch/riscv/lib/reset.c
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[])
> +{
> +	printf("reset unsupported yet\n");
> +
> +	return 0;
> +}

Thanks for adding this patch!
I see one possible problem with it. The way you implemented it, arch /
board code can't overwrite the function to add a reset method. How
about something like this?

- do_reset() only prints "resetting..." and then calls cpu_reset()
- reset.c includes a weak cpu_reset() function that prints the warning
you currently have in this patch (by the way, it should say "reset not
supported yet"). It might also make sense to print the warning with the
panic() function and define PANIC_HANG, so that u-boot is halted on
resets. cpu_reset() can then be defined by boards that have an actual
reset method.

Thanks,
Lukas

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Bin Meng]

Hi Lukas,

On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > This adds a helper routine to print CPU information. Currently
> > it prints all the instruction set extensions that the processor
> > core supports.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > Changes in v2: None
> >
> >  arch/riscv/Makefile          |   1 +
> >  arch/riscv/cpu/Makefile      |   5 ++
> >  arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
> >  arch/riscv/include/asm/csr.h | 124
> > +++++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 179 insertions(+)
> >  create mode 100644 arch/riscv/cpu/Makefile
> >  create mode 100644 arch/riscv/cpu/cpu.c
> >  create mode 100644 arch/riscv/include/asm/csr.h
> >
> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > index 084888a..af432e1 100644
> > --- a/arch/riscv/Makefile
> > +++ b/arch/riscv/Makefile
> > @@ -5,5 +5,6 @@
> >
> >  head-y := arch/riscv/cpu/$(CPU)/start.o
> >
> > +libs-y += arch/riscv/cpu/
> >  libs-y += arch/riscv/cpu/$(CPU)/
> >  libs-y += arch/riscv/lib/
> > diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
> > new file mode 100644
> > index 0000000..63de163
> > --- /dev/null
> > +++ b/arch/riscv/cpu/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > +
> > +obj-y += cpu.o
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > new file mode 100644
> > index 0000000..ae57fb8
> > --- /dev/null
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -0,0 +1,49 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/csr.h>
> > +
> > +enum {
> > +     ISA_INVALID = 0,
> > +     ISA_32BIT,
> > +     ISA_64BIT,
> > +     ISA_128BIT
> > +};
> > +
> > +static const char * const isa_bits[] = {
> > +     [ISA_INVALID] = NULL,
> > +     [ISA_32BIT]   = "32",
> > +     [ISA_64BIT]   = "64",
> > +     [ISA_128BIT]  = "128"
> > +};
> > +
> > +static inline bool supports_extension(char ext)
> > +{
> > +     return csr_read(misa) & (1 << (ext - 'a'));
> > +}
> > +
> > +int print_cpuinfo(void)
> > +{
> > +     char name[32];
> > +     char *s = name;
> > +     int bit;
> > +
> > +     s += sprintf(name, "rv");
> > +     bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
> > +     s += sprintf(s, isa_bits[bit]);
> > +
> > +     supports_extension('i') ? *s++ = 'i' : 'r';
> > +     supports_extension('m') ? *s++ = 'm' : 'i';
> > +     supports_extension('a') ? *s++ = 'a' : 's';
> > +     supports_extension('f') ? *s++ = 'f' : 'c';
> > +     supports_extension('d') ? *s++ = 'd' : '-';
> > +     supports_extension('c') ? *s++ = 'c' : 'v';
> > +     *s++ = '\0';
>
> Why are you not using the ISA string "riscv,isa" from the device tree?
> This way, the code is not limited to machine mode and we do not have
> update it if the set of extensions to check for changes.

I wanted to use hardware provided information whenever possible.
Reading from DT can be a last resort. I think we wanted to have U-Boot
running in machine mode, no?

Regards,
Bin

Regards,
Bin

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Bin Meng]

Hi Lukas,

On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > We don't have a reset method on any RISC-V board yet. Instead of
> > adding the same 'unsupported' message for each CPU variant it might
> > make more sense to add a generic do_reset function for all CPU
> > variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).
> >
> > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >
> > ---
> >
> > Changes in v2:
> > - new patch to move do_reset() to a common place
> >
> >  arch/riscv/cpu/ax25/cpu.c |  9 ---------
> >  arch/riscv/cpu/qemu/cpu.c |  8 --------
> >  arch/riscv/lib/Makefile   |  1 +
> >  arch/riscv/lib/reset.c    | 14 ++++++++++++++
> >  4 files changed, 15 insertions(+), 17 deletions(-)
> >  create mode 100644 arch/riscv/lib/reset.c
> >
> > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> > index ab05b57..fddcc15 100644
> > --- a/arch/riscv/cpu/ax25/cpu.c
> > +++ b/arch/riscv/cpu/ax25/cpu.c
> > @@ -6,9 +6,6 @@
> >
> >  /* CPU specific code */
> >  #include <common.h>
> > -#include <command.h>
> > -#include <watchdog.h>
> > -#include <asm/cache.h>
> >
> >  /*
> >   * cleanup_before_linux() is called just before we call linux
> > @@ -24,9 +21,3 @@ int cleanup_before_linux(void)
> >
> >       return 0;
> >  }
> > -
> > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > argv[])
> > -{
> > -     disable_interrupts();
> > -     panic("ax25-ae350 wdt not support yet.\n");
> > -}
> > diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
> > index a064639..6c7a327 100644
> > --- a/arch/riscv/cpu/qemu/cpu.c
> > +++ b/arch/riscv/cpu/qemu/cpu.c
> > @@ -4,7 +4,6 @@
> >   */
> >
> >  #include <common.h>
> > -#include <command.h>
> >
> >  /*
> >   * cleanup_before_linux() is called just before we call linux
> > @@ -20,10 +19,3 @@ int cleanup_before_linux(void)
> >
> >       return 0;
> >  }
> > -
> > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > argv[])
> > -{
> > -     printf("reset unsupported yet\n");
> > -
> > -     return 0;
> > -}
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index cc562f9..b58db89 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >  obj-$(CONFIG_CMD_GO) += boot.o
> >  obj-y        += cache.o
> >  obj-y        += interrupts.o
> > +obj-y        += reset.o
> >  obj-y   += setjmp.o
> >
> >  # For building EFI apps
> > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> > new file mode 100644
> > index 0000000..5d9b99c
> > --- /dev/null
> > +++ b/arch/riscv/lib/reset.c
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <command.h>
> > +
> > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > argv[])
> > +{
> > +     printf("reset unsupported yet\n");
> > +
> > +     return 0;
> > +}
>
> Thanks for adding this patch!
> I see one possible problem with it. The way you implemented it, arch /
> board code can't overwrite the function to add a reset method. How
> about something like this?
>

Thanks for your review and comments. I believe current implementation
in this patch is an interim approach, for now to save some duplicates.
The problem you mentioned can be resolved by implementing a SYSRESET
uclass driver for that CPU/board in the future.

> - do_reset() only prints "resetting..." and then calls cpu_reset()
> - reset.c includes a weak cpu_reset() function that prints the warning
> you currently have in this patch (by the way, it should say "reset not
> supported yet"). It might also make sense to print the warning with the
> panic() function and define PANIC_HANG, so that u-boot is halted on
> resets. cpu_reset() can then be defined by boards that have an actual
> reset method.

Regards,
Bin

[U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support

[Bin Meng]

Hi Lukas,

On Mon, Sep 17, 2018 at 5:02 AM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > This adds QEMU RISC-V 'virt' board target support, with the hope of
> > helping people easily test U-Boot on RISC-V.
> >
> > The QEMU virt machine models a generic RISC-V virtual machine with
> > support for the VirtIO standard networking and block storage devices.
> > It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
> > it also uses device-tree to pass configuration information to guest
> > software. It implements RISC-V privileged architecture spec v1.10.
> >
> > Both 32-bit and 64-bit builds are supported. Support is pretty much
> > preliminary, only booting to U-Boot shell with the UART driver on
> > a single core. Booting Linux is not supported yet.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >
> > ---
>
> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>
> [snip]
>
> >
> > diff --git a/board/emulation/qemu-riscv/Kconfig
> > b/board/emulation/qemu-riscv/Kconfig
> > new file mode 100644
> > index 0000000..029f5efb
> > --- /dev/null
> > +++ b/board/emulation/qemu-riscv/Kconfig
> > @@ -0,0 +1,21 @@
> > +if TARGET_QEMU_VIRT
> > +
> > +config SYS_BOARD
> > +     default "qemu-riscv"
> > +
> > +config SYS_VENDOR
> > +     default "emulation"
> > +
> > +config SYS_CPU
> > +     default "qemu"
> > +
> > +config SYS_CONFIG_NAME
> > +     default "qemu-riscv"
> > +
> > +config SYS_TEXT_BASE
> > +     default 0x80000000
> > +
> > +config BOARD_SPECIFIC_OPTIONS # dummy
> > +     def_bool y
> > +
>
> Out of curiosity, what is BOARD_SPECIFIC_OPTIONS used for? I see that
> other boards have included it as well, but I don't see it actually used
> anywhere.

This option is used to select or imply some board-specific options,
mostly drivers, so that we can avoid specifying them in the board
defconfig files. I think I should have at least moved the
CONFIG_SYS_NS16550 here. I am also working on virtio drivers, and once
they are done, these drivers can be implied here too.

Regards,
Bin

[U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-17 at 13:18 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Mon, Sep 17, 2018 at 5:02 AM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> > 
> > Hi Bin,
> > 
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds QEMU RISC-V 'virt' board target support, with the hope
> > > of
> > > helping people easily test U-Boot on RISC-V.
> > > 
> > > The QEMU virt machine models a generic RISC-V virtual machine
> > > with
> > > support for the VirtIO standard networking and block storage
> > > devices.
> > > It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
> > > it also uses device-tree to pass configuration information to
> > > guest
> > > software. It implements RISC-V privileged architecture spec
> > > v1.10.
> > > 
> > > Both 32-bit and 64-bit builds are supported. Support is pretty
> > > much
> > > preliminary, only booting to U-Boot shell with the UART driver on
> > > a single core. Booting Linux is not supported yet.
> > > 
> > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > 
> > > ---
> > 
> > Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > 
> > [snip]
> > 
> > > 
> > > diff --git a/board/emulation/qemu-riscv/Kconfig
> > > b/board/emulation/qemu-riscv/Kconfig
> > > new file mode 100644
> > > index 0000000..029f5efb
> > > --- /dev/null
> > > +++ b/board/emulation/qemu-riscv/Kconfig
> > > @@ -0,0 +1,21 @@
> > > +if TARGET_QEMU_VIRT
> > > +
> > > +config SYS_BOARD
> > > +     default "qemu-riscv"
> > > +
> > > +config SYS_VENDOR
> > > +     default "emulation"
> > > +
> > > +config SYS_CPU
> > > +     default "qemu"
> > > +
> > > +config SYS_CONFIG_NAME
> > > +     default "qemu-riscv"
> > > +
> > > +config SYS_TEXT_BASE
> > > +     default 0x80000000
> > > +
> > > +config BOARD_SPECIFIC_OPTIONS # dummy
> > > +     def_bool y
> > > +
> > 
> > Out of curiosity, what is BOARD_SPECIFIC_OPTIONS used for? I see
> > that
> > other boards have included it as well, but I don't see it actually
> > used
> > anywhere.
> 
> This option is used to select or imply some board-specific options,
> mostly drivers, so that we can avoid specifying them in the board
> defconfig files. I think I should have at least moved the
> CONFIG_SYS_NS16550 here. I am also working on virtio drivers, and
> once
> they are done, these drivers can be implied here too.
> 
> Regards,
> Bin

That makes sense and is a nice way of implementing this. Thanks for the
description!

Thanks,
Lukas

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> > 
> > Hi Bin,
> > 
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds a helper routine to print CPU information. Currently
> > > it prints all the instruction set extensions that the processor
> > > core supports.
> > > 
> > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > ---
> > > 
> > > Changes in v2: None
> > > 
> > >  arch/riscv/Makefile          |   1 +
> > >  arch/riscv/cpu/Makefile      |   5 ++
> > >  arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
> > >  arch/riscv/include/asm/csr.h | 124
> > > +++++++++++++++++++++++++++++++++++++++++++
> > >  4 files changed, 179 insertions(+)
> > >  create mode 100644 arch/riscv/cpu/Makefile
> > >  create mode 100644 arch/riscv/cpu/cpu.c
> > >  create mode 100644 arch/riscv/include/asm/csr.h
> > > 
> > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > > index 084888a..af432e1 100644
> > > --- a/arch/riscv/Makefile
> > > +++ b/arch/riscv/Makefile
> > > @@ -5,5 +5,6 @@
> > > 
> > >  head-y := arch/riscv/cpu/$(CPU)/start.o
> > > 
> > > +libs-y += arch/riscv/cpu/
> > >  libs-y += arch/riscv/cpu/$(CPU)/
> > >  libs-y += arch/riscv/lib/
> > > diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
> > > new file mode 100644
> > > index 0000000..63de163
> > > --- /dev/null
> > > +++ b/arch/riscv/cpu/Makefile
> > > @@ -0,0 +1,5 @@
> > > +# SPDX-License-Identifier: GPL-2.0+
> > > +#
> > > +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > +
> > > +obj-y += cpu.o
> > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > new file mode 100644
> > > index 0000000..ae57fb8
> > > --- /dev/null
> > > +++ b/arch/riscv/cpu/cpu.c
> > > @@ -0,0 +1,49 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <asm/csr.h>
> > > +
> > > +enum {
> > > +     ISA_INVALID = 0,
> > > +     ISA_32BIT,
> > > +     ISA_64BIT,
> > > +     ISA_128BIT
> > > +};
> > > +
> > > +static const char * const isa_bits[] = {
> > > +     [ISA_INVALID] = NULL,
> > > +     [ISA_32BIT]   = "32",
> > > +     [ISA_64BIT]   = "64",
> > > +     [ISA_128BIT]  = "128"
> > > +};
> > > +
> > > +static inline bool supports_extension(char ext)
> > > +{
> > > +     return csr_read(misa) & (1 << (ext - 'a'));
> > > +}
> > > +
> > > +int print_cpuinfo(void)
> > > +{
> > > +     char name[32];
> > > +     char *s = name;
> > > +     int bit;
> > > +
> > > +     s += sprintf(name, "rv");
> > > +     bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
> > > +     s += sprintf(s, isa_bits[bit]);
> > > +
> > > +     supports_extension('i') ? *s++ = 'i' : 'r';
> > > +     supports_extension('m') ? *s++ = 'm' : 'i';
> > > +     supports_extension('a') ? *s++ = 'a' : 's';
> > > +     supports_extension('f') ? *s++ = 'f' : 'c';
> > > +     supports_extension('d') ? *s++ = 'd' : '-';
> > > +     supports_extension('c') ? *s++ = 'c' : 'v';
> > > +     *s++ = '\0';
> > 
> > Why are you not using the ISA string "riscv,isa" from the device
> > tree?
> > This way, the code is not limited to machine mode and we do not
> > have
> > update it if the set of extensions to check for changes.
> 
> I wanted to use hardware provided information whenever possible.
> Reading from DT can be a last resort. I think we wanted to have U-
> Boot
> running in machine mode, no?
> 
> Regards,
> Bin
> 

Ok, I see. I don't entirely like that this has to be updated if we want
to display new extensions and it's currently actually missing the 'u'
(user) and 's' (supervisor) extensions, which are present in the misa
of RISC-V QEMU. It is fine for now, I think.

Yes, we want to run u-boot in machine mode for now, especially if we
want to add an SBI implementation to u-boot. Not much is needed to run
it in supervisor mode though, which is why I mentioned this. It also
allows us to use an SBI implementation external to u-boot, should we
want / need that.

Thanks,
Lukas


Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Auer, Lukas]

Hi Bin,

On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> > 
> > Hi Bin,
> > 
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > We don't have a reset method on any RISC-V board yet. Instead of
> > > adding the same 'unsupported' message for each CPU variant it
> > > might
> > > make more sense to add a generic do_reset function for all CPU
> > > variants to lib/, similar to the one for ARM
> > > (arch/arm/lib/reset.c).
> > > 
> > > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > 
> > > ---
> > > 
> > > Changes in v2:
> > > - new patch to move do_reset() to a common place
> > > 
> > >  arch/riscv/cpu/ax25/cpu.c |  9 ---------
> > >  arch/riscv/cpu/qemu/cpu.c |  8 --------
> > >  arch/riscv/lib/Makefile   |  1 +
> > >  arch/riscv/lib/reset.c    | 14 ++++++++++++++
> > >  4 files changed, 15 insertions(+), 17 deletions(-)
> > >  create mode 100644 arch/riscv/lib/reset.c
> > > 
> > > diff --git a/arch/riscv/cpu/ax25/cpu.c
> > > b/arch/riscv/cpu/ax25/cpu.c
> > > index ab05b57..fddcc15 100644
> > > --- a/arch/riscv/cpu/ax25/cpu.c
> > > +++ b/arch/riscv/cpu/ax25/cpu.c
> > > @@ -6,9 +6,6 @@
> > > 
> > >  /* CPU specific code */
> > >  #include <common.h>
> > > -#include <command.h>
> > > -#include <watchdog.h>
> > > -#include <asm/cache.h>
> > > 
> > >  /*
> > >   * cleanup_before_linux() is called just before we call linux
> > > @@ -24,9 +21,3 @@ int cleanup_before_linux(void)
> > > 
> > >       return 0;
> > >  }
> > > -
> > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > argv[])
> > > -{
> > > -     disable_interrupts();
> > > -     panic("ax25-ae350 wdt not support yet.\n");
> > > -}
> > > diff --git a/arch/riscv/cpu/qemu/cpu.c
> > > b/arch/riscv/cpu/qemu/cpu.c
> > > index a064639..6c7a327 100644
> > > --- a/arch/riscv/cpu/qemu/cpu.c
> > > +++ b/arch/riscv/cpu/qemu/cpu.c
> > > @@ -4,7 +4,6 @@
> > >   */
> > > 
> > >  #include <common.h>
> > > -#include <command.h>
> > > 
> > >  /*
> > >   * cleanup_before_linux() is called just before we call linux
> > > @@ -20,10 +19,3 @@ int cleanup_before_linux(void)
> > > 
> > >       return 0;
> > >  }
> > > -
> > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > argv[])
> > > -{
> > > -     printf("reset unsupported yet\n");
> > > -
> > > -     return 0;
> > > -}
> > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > index cc562f9..b58db89 100644
> > > --- a/arch/riscv/lib/Makefile
> > > +++ b/arch/riscv/lib/Makefile
> > > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> > >  obj-$(CONFIG_CMD_GO) += boot.o
> > >  obj-y        += cache.o
> > >  obj-y        += interrupts.o
> > > +obj-y        += reset.o
> > >  obj-y   += setjmp.o
> > > 
> > >  # For building EFI apps
> > > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> > > new file mode 100644
> > > index 0000000..5d9b99c
> > > --- /dev/null
> > > +++ b/arch/riscv/lib/reset.c
> > > @@ -0,0 +1,14 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <command.h>
> > > +
> > > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > argv[])
> > > +{
> > > +     printf("reset unsupported yet\n");
> > > +
> > > +     return 0;
> > > +}
> > 
> > Thanks for adding this patch!
> > I see one possible problem with it. The way you implemented it,
> > arch /
> > board code can't overwrite the function to add a reset method. How
> > about something like this?
> > 
> 
> Thanks for your review and comments. I believe current implementation
> in this patch is an interim approach, for now to save some
> duplicates.
> The problem you mentioned can be resolved by implementing a SYSRESET
> uclass driver for that CPU/board in the future.
> 

That's true, still, two minor things I would consider to change.

- A simple wording changes to make it clear that the reset is not only
not available, but u-boot actually tried to reset the system. So
something like this: "Resetting... reset not supported yet".

- I don't know how much of an issue it is that u-boot keeps running
after a reset. I would tend to use panic() together with PANIC_HANG, to
make sure u-boot halts. You know u-boot better than me, what do you
think?

Thanks,
Lukas


Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

> > - do_reset() only prints "resetting..." and then calls cpu_reset()
> > - reset.c includes a weak cpu_reset() function that prints the
> > warning
> > you currently have in this patch (by the way, it should say "reset
> > not
> > supported yet"). It might also make sense to print the warning with
> > the
> > panic() function and define PANIC_HANG, so that u-boot is halted on
> > resets. cpu_reset() can then be defined by boards that have an
> > actual
> > reset method.
> 
> Regards,
> Bin

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Bin Meng]

Hi Lukas,

On Tue, Sep 18, 2018 at 6:01 AM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
> > <lukas.auer@aisec.fraunhofer.de> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > > We don't have a reset method on any RISC-V board yet. Instead of
> > > > adding the same 'unsupported' message for each CPU variant it
> > > > might
> > > > make more sense to add a generic do_reset function for all CPU
> > > > variants to lib/, similar to the one for ARM
> > > > (arch/arm/lib/reset.c).
> > > >
> > > > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > >
> > > > ---
> > > >
> > > > Changes in v2:
> > > > - new patch to move do_reset() to a common place
> > > >
> > > >  arch/riscv/cpu/ax25/cpu.c |  9 ---------
> > > >  arch/riscv/cpu/qemu/cpu.c |  8 --------
> > > >  arch/riscv/lib/Makefile   |  1 +
> > > >  arch/riscv/lib/reset.c    | 14 ++++++++++++++
> > > >  4 files changed, 15 insertions(+), 17 deletions(-)
> > > >  create mode 100644 arch/riscv/lib/reset.c
> > > >
> > > > diff --git a/arch/riscv/cpu/ax25/cpu.c
> > > > b/arch/riscv/cpu/ax25/cpu.c
> > > > index ab05b57..fddcc15 100644
> > > > --- a/arch/riscv/cpu/ax25/cpu.c
> > > > +++ b/arch/riscv/cpu/ax25/cpu.c
> > > > @@ -6,9 +6,6 @@
> > > >
> > > >  /* CPU specific code */
> > > >  #include <common.h>
> > > > -#include <command.h>
> > > > -#include <watchdog.h>
> > > > -#include <asm/cache.h>
> > > >
> > > >  /*
> > > >   * cleanup_before_linux() is called just before we call linux
> > > > @@ -24,9 +21,3 @@ int cleanup_before_linux(void)
> > > >
> > > >       return 0;
> > > >  }
> > > > -
> > > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > > argv[])
> > > > -{
> > > > -     disable_interrupts();
> > > > -     panic("ax25-ae350 wdt not support yet.\n");
> > > > -}
> > > > diff --git a/arch/riscv/cpu/qemu/cpu.c
> > > > b/arch/riscv/cpu/qemu/cpu.c
> > > > index a064639..6c7a327 100644
> > > > --- a/arch/riscv/cpu/qemu/cpu.c
> > > > +++ b/arch/riscv/cpu/qemu/cpu.c
> > > > @@ -4,7 +4,6 @@
> > > >   */
> > > >
> > > >  #include <common.h>
> > > > -#include <command.h>
> > > >
> > > >  /*
> > > >   * cleanup_before_linux() is called just before we call linux
> > > > @@ -20,10 +19,3 @@ int cleanup_before_linux(void)
> > > >
> > > >       return 0;
> > > >  }
> > > > -
> > > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > > argv[])
> > > > -{
> > > > -     printf("reset unsupported yet\n");
> > > > -
> > > > -     return 0;
> > > > -}
> > > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > > index cc562f9..b58db89 100644
> > > > --- a/arch/riscv/lib/Makefile
> > > > +++ b/arch/riscv/lib/Makefile
> > > > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> > > >  obj-$(CONFIG_CMD_GO) += boot.o
> > > >  obj-y        += cache.o
> > > >  obj-y        += interrupts.o
> > > > +obj-y        += reset.o
> > > >  obj-y   += setjmp.o
> > > >
> > > >  # For building EFI apps
> > > > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> > > > new file mode 100644
> > > > index 0000000..5d9b99c
> > > > --- /dev/null
> > > > +++ b/arch/riscv/lib/reset.c
> > > > @@ -0,0 +1,14 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <command.h>
> > > > +
> > > > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> > > > argv[])
> > > > +{
> > > > +     printf("reset unsupported yet\n");
> > > > +
> > > > +     return 0;
> > > > +}
> > >
> > > Thanks for adding this patch!
> > > I see one possible problem with it. The way you implemented it,
> > > arch /
> > > board code can't overwrite the function to add a reset method. How
> > > about something like this?
> > >
> >
> > Thanks for your review and comments. I believe current implementation
> > in this patch is an interim approach, for now to save some
> > duplicates.
> > The problem you mentioned can be resolved by implementing a SYSRESET
> > uclass driver for that CPU/board in the future.
> >
>
> That's true, still, two minor things I would consider to change.
>
> - A simple wording changes to make it clear that the reset is not only
> not available, but u-boot actually tried to reset the system. So
> something like this: "Resetting... reset not supported yet".
>

Sure, will reword this in v3.

 - I don't know how much of an issue it is that u-boot keeps running
> after a reset. I would tend to use panic() together with PANIC_HANG, to
> make sure u-boot halts. You know u-boot better than me, what do you
> think?
>

Yes, I think using hang() can be a good choice for now.

Regards,
Bin

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Bin Meng]

Hi Lukas,

On Tue, Sep 18, 2018 at 5:59 AM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
> > <lukas.auer@aisec.fraunhofer.de> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > > This adds a helper routine to print CPU information. Currently
> > > > it prints all the instruction set extensions that the processor
> > > > core supports.
> > > >
> > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > > ---
> > > >
> > > > Changes in v2: None
> > > >
> > > >  arch/riscv/Makefile          |   1 +
> > > >  arch/riscv/cpu/Makefile      |   5 ++
> > > >  arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
> > > >  arch/riscv/include/asm/csr.h | 124
> > > > +++++++++++++++++++++++++++++++++++++++++++
> > > >  4 files changed, 179 insertions(+)
> > > >  create mode 100644 arch/riscv/cpu/Makefile
> > > >  create mode 100644 arch/riscv/cpu/cpu.c
> > > >  create mode 100644 arch/riscv/include/asm/csr.h
> > > >
> > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > > > index 084888a..af432e1 100644
> > > > --- a/arch/riscv/Makefile
> > > > +++ b/arch/riscv/Makefile
> > > > @@ -5,5 +5,6 @@
> > > >
> > > >  head-y := arch/riscv/cpu/$(CPU)/start.o
> > > >
> > > > +libs-y += arch/riscv/cpu/
> > > >  libs-y += arch/riscv/cpu/$(CPU)/
> > > >  libs-y += arch/riscv/lib/
> > > > diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
> > > > new file mode 100644
> > > > index 0000000..63de163
> > > > --- /dev/null
> > > > +++ b/arch/riscv/cpu/Makefile
> > > > @@ -0,0 +1,5 @@
> > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > +#
> > > > +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > +
> > > > +obj-y += cpu.o
> > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > > new file mode 100644
> > > > index 0000000..ae57fb8
> > > > --- /dev/null
> > > > +++ b/arch/riscv/cpu/cpu.c
> > > > @@ -0,0 +1,49 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <asm/csr.h>
> > > > +
> > > > +enum {
> > > > +     ISA_INVALID = 0,
> > > > +     ISA_32BIT,
> > > > +     ISA_64BIT,
> > > > +     ISA_128BIT
> > > > +};
> > > > +
> > > > +static const char * const isa_bits[] = {
> > > > +     [ISA_INVALID] = NULL,
> > > > +     [ISA_32BIT]   = "32",
> > > > +     [ISA_64BIT]   = "64",
> > > > +     [ISA_128BIT]  = "128"
> > > > +};
> > > > +
> > > > +static inline bool supports_extension(char ext)
> > > > +{
> > > > +     return csr_read(misa) & (1 << (ext - 'a'));
> > > > +}
> > > > +
> > > > +int print_cpuinfo(void)
> > > > +{
> > > > +     char name[32];
> > > > +     char *s = name;
> > > > +     int bit;
> > > > +
> > > > +     s += sprintf(name, "rv");
> > > > +     bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
> > > > +     s += sprintf(s, isa_bits[bit]);
> > > > +
> > > > +     supports_extension('i') ? *s++ = 'i' : 'r';
> > > > +     supports_extension('m') ? *s++ = 'm' : 'i';
> > > > +     supports_extension('a') ? *s++ = 'a' : 's';
> > > > +     supports_extension('f') ? *s++ = 'f' : 'c';
> > > > +     supports_extension('d') ? *s++ = 'd' : '-';
> > > > +     supports_extension('c') ? *s++ = 'c' : 'v';
> > > > +     *s++ = '\0';
> > >
> > > Why are you not using the ISA string "riscv,isa" from the device
> > > tree?
> > > This way, the code is not limited to machine mode and we do not
> > > have
> > > update it if the set of extensions to check for changes.
> >
> > I wanted to use hardware provided information whenever possible.
> > Reading from DT can be a last resort. I think we wanted to have U-
> > Boot
> > running in machine mode, no?
> >
> > Regards,
> > Bin
> >
>
> Ok, I see. I don't entirely like that this has to be updated if we want
> to display new extensions and it's currently actually missing the 'u'
> (user) and 's' (supervisor) extensions, which are present in the misa
> of RISC-V QEMU. It is fine for now, I think.
>

Yes, let's leave this for now. Currently it seems only prints "GC"
extension is enough (IMAFDC).

> Yes, we want to run u-boot in machine mode for now, especially if we
> want to add an SBI implementation to u-boot. Not much is needed to run
> it in supervisor mode though, which is why I mentioned this. It also
> allows us to use an SBI implementation external to u-boot, should we
> want / need that.
>

Let's see how things go. My personal preference would be only using
U-Boot though :)

Regards,
Bin

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

[Auer, Lukas]

Hi Bin,

On Tue, 2018-09-18 at 16:53 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Tue, Sep 18, 2018 at 5:59 AM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> > 
> > Hi Bin,
> > 
> > On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > > 
> > > On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
> > > <lukas.auer@aisec.fraunhofer.de> wrote:
> > > > 
> > > > Hi Bin,
> > > > 
> > > > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > > > This adds a helper routine to print CPU information.
> > > > > Currently
> > > > > it prints all the instruction set extensions that the
> > > > > processor
> > > > > core supports.
> > > > > 
> > > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > > > ---
> > > > > 
> > > > > Changes in v2: None
> > > > > 
> > > > >  arch/riscv/Makefile          |   1 +
> > > > >  arch/riscv/cpu/Makefile      |   5 ++
> > > > >  arch/riscv/cpu/cpu.c         |  49 +++++++++++++++++
> > > > >  arch/riscv/include/asm/csr.h | 124
> > > > > +++++++++++++++++++++++++++++++++++++++++++
> > > > >  4 files changed, 179 insertions(+)
> > > > >  create mode 100644 arch/riscv/cpu/Makefile
> > > > >  create mode 100644 arch/riscv/cpu/cpu.c
> > > > >  create mode 100644 arch/riscv/include/asm/csr.h
> > > > > 
> > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > > > > index 084888a..af432e1 100644
> > > > > --- a/arch/riscv/Makefile
> > > > > +++ b/arch/riscv/Makefile
> > > > > @@ -5,5 +5,6 @@
> > > > > 
> > > > >  head-y := arch/riscv/cpu/$(CPU)/start.o
> > > > > 
> > > > > +libs-y += arch/riscv/cpu/
> > > > >  libs-y += arch/riscv/cpu/$(CPU)/
> > > > >  libs-y += arch/riscv/lib/
> > > > > diff --git a/arch/riscv/cpu/Makefile
> > > > > b/arch/riscv/cpu/Makefile
> > > > > new file mode 100644
> > > > > index 0000000..63de163
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/cpu/Makefile
> > > > > @@ -0,0 +1,5 @@
> > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > +#
> > > > > +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > > +
> > > > > +obj-y += cpu.o
> > > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > > > new file mode 100644
> > > > > index 0000000..ae57fb8
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/cpu/cpu.c
> > > > > @@ -0,0 +1,49 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > > + */
> > > > > +
> > > > > +#include <common.h>
> > > > > +#include <asm/csr.h>
> > > > > +
> > > > > +enum {
> > > > > +     ISA_INVALID = 0,
> > > > > +     ISA_32BIT,
> > > > > +     ISA_64BIT,
> > > > > +     ISA_128BIT
> > > > > +};
> > > > > +
> > > > > +static const char * const isa_bits[] = {
> > > > > +     [ISA_INVALID] = NULL,
> > > > > +     [ISA_32BIT]   = "32",
> > > > > +     [ISA_64BIT]   = "64",
> > > > > +     [ISA_128BIT]  = "128"
> > > > > +};
> > > > > +
> > > > > +static inline bool supports_extension(char ext)
> > > > > +{
> > > > > +     return csr_read(misa) & (1 << (ext - 'a'));
> > > > > +}
> > > > > +
> > > > > +int print_cpuinfo(void)
> > > > > +{
> > > > > +     char name[32];
> > > > > +     char *s = name;
> > > > > +     int bit;
> > > > > +
> > > > > +     s += sprintf(name, "rv");
> > > > > +     bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
> > > > > +     s += sprintf(s, isa_bits[bit]);
> > > > > +
> > > > > +     supports_extension('i') ? *s++ = 'i' : 'r';
> > > > > +     supports_extension('m') ? *s++ = 'm' : 'i';
> > > > > +     supports_extension('a') ? *s++ = 'a' : 's';
> > > > > +     supports_extension('f') ? *s++ = 'f' : 'c';
> > > > > +     supports_extension('d') ? *s++ = 'd' : '-';
> > > > > +     supports_extension('c') ? *s++ = 'c' : 'v';
> > > > > +     *s++ = '\0';
> > > > 
> > > > Why are you not using the ISA string "riscv,isa" from the
> > > > device
> > > > tree?
> > > > This way, the code is not limited to machine mode and we do not
> > > > have
> > > > update it if the set of extensions to check for changes.
> > > 
> > > I wanted to use hardware provided information whenever possible.
> > > Reading from DT can be a last resort. I think we wanted to have
> > > U-
> > > Boot
> > > running in machine mode, no?
> > > 
> > > Regards,
> > > Bin
> > > 
> > 
> > Ok, I see. I don't entirely like that this has to be updated if we
> > want
> > to display new extensions and it's currently actually missing the
> > 'u'
> > (user) and 's' (supervisor) extensions, which are present in the
> > misa
> > of RISC-V QEMU. It is fine for now, I think.
> > 
> 
> Yes, let's leave this for now. Currently it seems only prints "GC"
> extension is enough (IMAFDC).
> 

That makes sense.

> > Yes, we want to run u-boot in machine mode for now, especially if
> > we
> > want to add an SBI implementation to u-boot. Not much is needed to
> > run
> > it in supervisor mode though, which is why I mentioned this. It
> > also
> > allows us to use an SBI implementation external to u-boot, should
> > we
> > want / need that.
> > 
> 
> Let's see how things go. My personal preference would be only using
> U-Boot though :)
> 
> Regards,
> Bin

Yes that certainly is the best solution, at least for now. :) I think a
separate SBI implementation only starts to make sense, if it becomes a
lot more complicated / feature-rich than it is now.

Thanks,
Lukas

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Auer, Lukas]

Hi Bin,

On Tue, 2018-09-18 at 16:50 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Tue, Sep 18, 2018 at 6:01 AM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> > 
> > Hi Bin,
> > 
> > On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > > 
> > > On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
> > > <lukas.auer@aisec.fraunhofer.de> wrote:
> > > > 
> > > > Hi Bin,
> > > > 
> > > > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > > > We don't have a reset method on any RISC-V board yet. Instead
> > > > > of
> > > > > adding the same 'unsupported' message for each CPU variant it
> > > > > might
> > > > > make more sense to add a generic do_reset function for all
> > > > > CPU
> > > > > variants to lib/, similar to the one for ARM
> > > > > (arch/arm/lib/reset.c).
> > > > > 
> > > > > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > > > 
> > > > > ---
> > > > > 
> > > > > Changes in v2:
> > > > > - new patch to move do_reset() to a common place
> > > > > 
> > > > >  arch/riscv/cpu/ax25/cpu.c |  9 ---------
> > > > >  arch/riscv/cpu/qemu/cpu.c |  8 --------
> > > > >  arch/riscv/lib/Makefile   |  1 +
> > > > >  arch/riscv/lib/reset.c    | 14 ++++++++++++++
> > > > >  4 files changed, 15 insertions(+), 17 deletions(-)
> > > > >  create mode 100644 arch/riscv/lib/reset.c
> > > > > 
> > > > > diff --git a/arch/riscv/cpu/ax25/cpu.c
> > > > > b/arch/riscv/cpu/ax25/cpu.c
> > > > > index ab05b57..fddcc15 100644
> > > > > --- a/arch/riscv/cpu/ax25/cpu.c
> > > > > +++ b/arch/riscv/cpu/ax25/cpu.c
> > > > > @@ -6,9 +6,6 @@
> > > > > 
> > > > >  /* CPU specific code */
> > > > >  #include <common.h>
> > > > > -#include <command.h>
> > > > > -#include <watchdog.h>
> > > > > -#include <asm/cache.h>
> > > > > 
> > > > >  /*
> > > > >   * cleanup_before_linux() is called just before we call
> > > > > linux
> > > > > @@ -24,9 +21,3 @@ int cleanup_before_linux(void)
> > > > > 
> > > > >       return 0;
> > > > >  }
> > > > > -
> > > > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
> > > > > const
> > > > > argv[])
> > > > > -{
> > > > > -     disable_interrupts();
> > > > > -     panic("ax25-ae350 wdt not support yet.\n");
> > > > > -}
> > > > > diff --git a/arch/riscv/cpu/qemu/cpu.c
> > > > > b/arch/riscv/cpu/qemu/cpu.c
> > > > > index a064639..6c7a327 100644
> > > > > --- a/arch/riscv/cpu/qemu/cpu.c
> > > > > +++ b/arch/riscv/cpu/qemu/cpu.c
> > > > > @@ -4,7 +4,6 @@
> > > > >   */
> > > > > 
> > > > >  #include <common.h>
> > > > > -#include <command.h>
> > > > > 
> > > > >  /*
> > > > >   * cleanup_before_linux() is called just before we call
> > > > > linux
> > > > > @@ -20,10 +19,3 @@ int cleanup_before_linux(void)
> > > > > 
> > > > >       return 0;
> > > > >  }
> > > > > -
> > > > > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
> > > > > const
> > > > > argv[])
> > > > > -{
> > > > > -     printf("reset unsupported yet\n");
> > > > > -
> > > > > -     return 0;
> > > > > -}
> > > > > diff --git a/arch/riscv/lib/Makefile
> > > > > b/arch/riscv/lib/Makefile
> > > > > index cc562f9..b58db89 100644
> > > > > --- a/arch/riscv/lib/Makefile
> > > > > +++ b/arch/riscv/lib/Makefile
> > > > > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> > > > >  obj-$(CONFIG_CMD_GO) += boot.o
> > > > >  obj-y        += cache.o
> > > > >  obj-y        += interrupts.o
> > > > > +obj-y        += reset.o
> > > > >  obj-y   += setjmp.o
> > > > > 
> > > > >  # For building EFI apps
> > > > > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> > > > > new file mode 100644
> > > > > index 0000000..5d9b99c
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/lib/reset.c
> > > > > @@ -0,0 +1,14 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> > > > > + */
> > > > > +
> > > > > +#include <common.h>
> > > > > +#include <command.h>
> > > > > +
> > > > > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
> > > > > const
> > > > > argv[])
> > > > > +{
> > > > > +     printf("reset unsupported yet\n");
> > > > > +
> > > > > +     return 0;
> > > > > +}
> > > > 
> > > > Thanks for adding this patch!
> > > > I see one possible problem with it. The way you implemented it,
> > > > arch /
> > > > board code can't overwrite the function to add a reset method.
> > > > How
> > > > about something like this?
> > > > 
> > > 
> > > Thanks for your review and comments. I believe current
> > > implementation
> > > in this patch is an interim approach, for now to save some
> > > duplicates.
> > > The problem you mentioned can be resolved by implementing a
> > > SYSRESET
> > > uclass driver for that CPU/board in the future.
> > > 
> > 
> > That's true, still, two minor things I would consider to change.
> > 
> > - A simple wording changes to make it clear that the reset is not
> > only
> > not available, but u-boot actually tried to reset the system. So
> > something like this: "Resetting... reset not supported yet".
> > 
> 
> Sure, will reword this in v3.
> 
>  - I don't know how much of an issue it is that u-boot keeps running
> > after a reset. I would tend to use panic() together with
> > PANIC_HANG, to
> > make sure u-boot halts. You know u-boot better than me, what do you
> > think?
> > 
> 
> Yes, I think using hang() can be a good choice for now.
> 
> Regards,
> Bin

Thanks! :)

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

[Rick Chen]

 > Hi Rick,
 >
 > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
 > >
 > > This series adds QEMU RISC-V 'virt' board target support, with the
 > > hope of helping people easily test U-Boot on RISC-V.
 > >
 > > Some existing RISC-V codes have been changed to make it easily to
 > > support new targets. Some spotted coding style issues are fixed.
 > >
 > > This series is available at u-boot-x86/riscv-working for testing.
 > >
 > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on
 > > github, as the git.denx.de is still out of sync ...
 > >
 > > Changes in v2:
 > > - Change Linux kernel entry parameters' type to support 32/64 bit
 > > - new patch to remove CSR read/write defines in encoding.h
 > > - new patch to pass mhartid CSR value to kernel
 > > - new patch to move do_reset() to a common place
 >
 > Any comments for the v2?

Hi Bin

Sorry for late response!

I have reviewed the v2 patch sets, it looks fine.
And also verify the riscv-linux booting feature on ax25-ae350 board
via bootm command.
The verification is OK. :)

B.R

Rick


 >
 > Regards,
 > Bin

[U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling

[Rick Chen]

 > From: Bin Meng [mailto:bmeng.cn at gmail.com]
 > Sent: Tuesday, September 11, 2018 12:55 PM
 > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
 > Cc: Lukas Auer
 > Subject: [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name
 > spelling
 >
 > It's RISC-V that is the official name, not RISCV.
 >
 > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 > ---
 >
 > Changes in v2: None
 >
 >  arch/Kconfig       | 2 +-
 >  arch/riscv/Kconfig | 6 +++---
 >  2 files changed, 4 insertions(+), 4 deletions(-)
 >
 > diff --git a/arch/Kconfig b/arch/Kconfig index bf1b4a9..42c23b5 100644
 > --- a/arch/Kconfig
 > +++ b/arch/Kconfig
 > @@ -60,7 +60,7 @@ config PPC
 >       select SYS_BOOT_GET_KBD
 >
 >  config RISCV
 > -     bool "riscv architecture"
 > +     bool "RISC-V architecture"
 >       select SUPPORT_OF_CONTROL
 >
 >  config SANDBOX
 > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 20a43d8..49f87de
 > 100644
 > --- a/arch/riscv/Kconfig
 > +++ b/arch/riscv/Kconfig
 > @@ -1,4 +1,4 @@
 > -menu "RISCV architecture"
 > +menu "RISC-V architecture"
 >       depends on RISCV
 >
 >  config SYS_ARCH
 > @@ -20,13 +20,13 @@ choice
 >       default CPU_RISCV_32
 >
 >  config CPU_RISCV_32
 > -     bool "RISCV 32 bit"
 > +     bool "RISC-V 32-bit"
 >       select 32BIT
 >       help
 >         Choose this option to build an U-Boot for RISCV32 architecture.
 >
 >  config CPU_RISCV_64
 > -     bool "RISCV 64 bit"
 > +     bool "RISC-V 64-bit"
 >       select 64BIT
 >       help
 >         Choose this option to build an U-Boot for RISCV64 architecture.
 > --
 > 2.7.4

Reviewed-by: Rick Chen <rick@andestech.com>

[U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id

[Rick Chen]

 > From: Bin Meng [mailto:bmeng.cn at gmail.com]
 > Sent: Tuesday, September 11, 2018 12:55 PM
 > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
 > Cc: Lukas Auer
 > Subject: [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st
kernel argument
 > to hart id
 >
 > The first argument of Linux kernel is the risc-v core hart id, from
which the kernel
 > is booted from. It is not the mach_id, which seems to be copied from arm.
 >
 > While we are here, this also changes the Linux kernel entry
parameters' type to
 > support both 32-bit and 64-bit.
 >
 > Note the hart id is hardcoded to zero for now, and we should change
to fill in it
 > with the value read from mhartid CSR of the hart which this routine
is currently
 > running on.
 >
 > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 >
 > ---
 >
 > Changes in v2:
 > - Change Linux kernel entry parameters' type to support 32/64 bit
 >
 >  arch/riscv/lib/bootm.c | 18 +++++-------------
 >  1 file changed, 5 insertions(+), 13 deletions(-)
 >
 > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index
 > 6662aff..6893108 100644
 > --- a/arch/riscv/lib/bootm.c
 > +++ b/arch/riscv/lib/bootm.c
 > @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob)
 >
 >  int do_bootm_linux(int flag, int argc, char *argv[],
bootm_headers_t *images)
 > {
 > -     bd_t    *bd = gd->bd;
 > -     char    *s;
 > -     int     machid = bd->bi_arch_number;
 > -     void    (*theKernel)(int arch, uint params);
 > +     void    (*kernel)(ulong hart, void *dtb);
 >
 >       /*
 >        * allow the PREP bootm subcommand, it is required for bootm to work
 > @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[],
 > bootm_headers_t *images)
 >       if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 >               return 1;
 >
 > -     theKernel = (void (*)(int, uint))images->ep;
 > -
 > -     s = env_get("machid");
 > -     if (s) {
 > -             machid = simple_strtoul(s, NULL, 16);
 > -             printf("Using machid 0x%x from environment\n", machid);
 > -     }
 > +     kernel = (void (*)(ulong, void *))images->ep;
 >
 >       bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 >
 >       debug("## Transferring control to Linux (at address %08lx) ...\n",
 > -            (ulong)theKernel);
 > +            (ulong)kernel);
 >
 >       if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {  #ifdef
 > CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc,
 > char *argv[], bootm_headers_t *images)
 >       printf("\nStarting kernel ...\n\n");
 >
 >       cleanup_before_linux();
 > +     /* TODO: hardcode the hart id to zero for now */
 >       if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
 > -             theKernel(machid, (unsigned long)images->ft_addr);
 > +             kernel(0, images->ft_addr);
 >
 >       /* does not return */
 >

Reviewed-by: Rick Chen <rick@andestech.com>

 > --
 > 2.7.4

[U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h

[Rick Chen]

 > From: Bin Meng [mailto:bmeng.cn at gmail.com]
 > Sent: Tuesday, September 11, 2018 12:55 PM
 > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
 > Cc: Lukas Auer
 > Subject: [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in
 > encoding.h
 >
 > There is no reason to keep two versions of CSR read/write defines
in encoding.h.
 > We already have one set of defines in csr.h, which is from Linux
kernel, and let's
 > drop the one in encoding.h.
 >
 > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 >
 > ---
 >
 > Changes in v2:
 > - new patch to remove CSR read/write defines in encoding.h
 >
 >  arch/riscv/include/asm/encoding.h | 50
++++-----------------------------------
 >  1 file changed, 4 insertions(+), 46 deletions(-)
 >
 > diff --git a/arch/riscv/include/asm/encoding.h
 > b/arch/riscv/include/asm/encoding.h
 > index f237a72..9ea50ce 100644
 > --- a/arch/riscv/include/asm/encoding.h
 > +++ b/arch/riscv/include/asm/encoding.h
 > @@ -128,6 +128,7 @@
 >       ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 >
 >  #ifdef __riscv
 > +
 >  #ifdef CONFIG_64BIT
 >  # define MSTATUS_SD MSTATUS64_SD
 >  # define SSTATUS_SD SSTATUS64_SD
 > @@ -141,53 +142,10 @@
 >  # define MCAUSE_INT MCAUSE32_INT
 >  # define MCAUSE_CAUSE MCAUSE32_CAUSE
 >  #endif
 > +
 >  #define RISCV_PGSHIFT 12
 >  #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
 >
 > -#ifndef __ASSEMBLER__
 > -
 > -#ifdef __GNUC__
 > -
 > -#define read_csr(reg) ({ unsigned long __tmp; \
 > -     asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
 > -     __tmp; })
 > -
 > -#define write_csr(reg, _val) ({ \
 > -typeof(_val) (val) = (_val); \
 > -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
 > -     asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
 > -else \
 > -     asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
 > -
 > -#define swap_csr(reg, _val) ({ unsigned long __tmp; \
 > -typeof(_val) (val) = (_val); \
 > -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
 > -     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
 > -else \
 > -     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
 > -     __tmp; })
 > -
 > -#define set_csr(reg, _bit) ({ unsigned long __tmp; \
 > -typeof(_bit) (bit) = (_bit); \
 > -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
 > -     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 > -else \
 > -     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 > -     __tmp; })
 > -
 > -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
 > -typeof(_bit) (bit) = (_bit); \
 > -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
 > -     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 > -else \
 > -     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 > -     __tmp; })
 > -
 > -#define rdtime() read_csr(time)
 > -#define rdcycle() read_csr(cycle)
 > -#define rdinstret() read_csr(instret)
 > +#endif /* __riscv */
 >
 > -#endif
 > -#endif
 > -#endif
 > -#endif
 > +#endif /* RISCV_CSR_ENCODING_H */

Reviewed-by: Rick Chen <rick@andestech.com>

 > --
 > 2.7.4

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

[Bin Meng]

Hi Rick,

On Thu, Sep 20, 2018 at 11:00 AM Rick Chen <rickchen36@gmail.com> wrote:
>
>  > Hi Rick,
>  >
>  > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>  > >
>  > > This series adds QEMU RISC-V 'virt' board target support, with the
>  > > hope of helping people easily test U-Boot on RISC-V.
>  > >
>  > > Some existing RISC-V codes have been changed to make it easily to
>  > > support new targets. Some spotted coding style issues are fixed.
>  > >
>  > > This series is available at u-boot-x86/riscv-working for testing.
>  > >
>  > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on
>  > > github, as the git.denx.de is still out of sync ...
>  > >
>  > > Changes in v2:
>  > > - Change Linux kernel entry parameters' type to support 32/64 bit
>  > > - new patch to remove CSR read/write defines in encoding.h
>  > > - new patch to pass mhartid CSR value to kernel
>  > > - new patch to move do_reset() to a common place
>  >
>  > Any comments for the v2?
>
> Hi Bin
>
> Sorry for late response!
>
> I have reviewed the v2 patch sets, it looks fine.
> And also verify the riscv-linux booting feature on ax25-ae350 board
> via bootm command.
> The verification is OK. :)

Thank you. I will prepare and resend a v3 with all these tags added
from you and Lukas, and hopefully the v3 can be applied without any
problem.

Regards,
Bin

[U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel

[Rick Chen]

 > From: Bin Meng [mailto:bmeng.cn at gmail.com]
 > Sent: Tuesday, September 11, 2018 12:55 PM
 > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
 > Cc: Lukas Auer
 > Subject: [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR
value to kernel
 >
 > So far this is hardcoded to zero, and we should read the value from
mhartid CSR
 > and pass it to Linux kernel.
 >
 > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
 > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 >
 > ---
 >
 > Changes in v2:
 > - new patch to pass mhartid CSR value to kernel
 >
 >  arch/riscv/lib/bootm.c | 5 +++--
 >  1 file changed, 3 insertions(+), 2 deletions(-)
 >
> > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index
 > 6893108..a7a9fb9 100644
 > --- a/arch/riscv/lib/bootm.c
 > +++ b/arch/riscv/lib/bootm.c
 > @@ -11,6 +11,7 @@
 >  #include <image.h>
 >  #include <u-boot/zlib.h>
 >  #include <asm/byteorder.h>
 > +#include <asm/csr.h>
 >
 >  DECLARE_GLOBAL_DATA_PTR;
 >
 > @@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[],
 > bootm_headers_t *images)
 >       printf("\nStarting kernel ...\n\n");
 >
 >       cleanup_before_linux();
 > -     /* TODO: hardcode the hart id to zero for now */
 > +
 >       if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
 > -             kernel(0, images->ft_addr);
 > +             kernel(csr_read(mhartid), images->ft_addr);
 >
 >       /* does not return */
 >

Reviewed-by: Rick Chen <rick@andestech.com>

> > --
 > 2.7.4

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

[Rick Chen]

 > From: Bin Meng [mailto:bmeng.cn at gmail.com]
 > Sent: Tuesday, September 11, 2018 12:55 PM
 > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
 > Cc: Lukas Auer
 > Subject: [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place
 >
 > We don't have a reset method on any RISC-V board yet. Instead of adding the
 > same 'unsupported' message for each CPU variant it might make more sense to
 > add a generic do_reset function for all CPU variants to lib/,
similar to the one for
 > ARM (arch/arm/lib/reset.c).
 >
 > Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
 > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 >
 > ---
 >
 > Changes in v2:
 > - new patch to move do_reset() to a common place
 >
 >  arch/riscv/cpu/ax25/cpu.c |  9 ---------
arch/riscv/cpu/qemu/cpu.c |  8 --------
 >  arch/riscv/lib/Makefile   |  1 +
 >  arch/riscv/lib/reset.c    | 14 ++++++++++++++
 >  4 files changed, 15 insertions(+), 17 deletions(-)  create mode 100644
 > arch/riscv/lib/reset.c
 >
 > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index
 > ab05b57..fddcc15 100644
 > --- a/arch/riscv/cpu/ax25/cpu.c
 > +++ b/arch/riscv/cpu/ax25/cpu.c
 > @@ -6,9 +6,6 @@
 >
 >  /* CPU specific code */
 >  #include <common.h>
 > -#include <command.h>
 > -#include <watchdog.h>
 > -#include <asm/cache.h>
 >
 >  /*
 >   * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3
 > @@ int cleanup_before_linux(void)
 >
 >       return 0;
 >  }
 > -
 > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{
 > -     disable_interrupts();
 > -     panic("ax25-ae350 wdt not support yet.\n");
 > -}
 > diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index
 > a064639..6c7a327 100644
 > --- a/arch/riscv/cpu/qemu/cpu.c
 > +++ b/arch/riscv/cpu/qemu/cpu.c
 > @@ -4,7 +4,6 @@
 >   */
 >
 >  #include <common.h>
 > -#include <command.h>
 >
 >  /*
 >   * cleanup_before_linux() is called just before we call linux @@
-20,10 +19,3
 > @@ int cleanup_before_linux(void)
 >
 >       return 0;
 >  }
 > -
 > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{
 > -     printf("reset unsupported yet\n");
 > -
 > -     return 0;
 > -}
 > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
 > cc562f9..b58db89 100644
 > --- a/arch/riscv/lib/Makefile
 > +++ b/arch/riscv/lib/Makefile
 > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 >  obj-$(CONFIG_CMD_GO) += boot.o
 >  obj-y        += cache.o
 >  obj-y        += interrupts.o
 > +obj-y        += reset.o
 >  obj-y   += setjmp.o
 >
 >  # For building EFI apps
 > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new
file mode 100644
 > index 0000000..5d9b99c
 > --- /dev/null
 > +++ b/arch/riscv/lib/reset.c
 > @@ -0,0 +1,14 @@
 > +// SPDX-License-Identifier: GPL-2.0+
 > +/*
 > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>  */
 > +
 > +#include <common.h>
 > +#include <command.h>
 > +
 > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 > +{
 > +     printf("reset unsupported yet\n");
 > +
 > +     return 0;
 > +}

Reviewed-by: Rick Chen <rick@andestech.com>

 > --
 > 2.7.4