Re: SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma)

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Hello everyone,

On 16.06.22 17:54, Ahmad Fatoum wrote:
> Hello Peter,
> 
> Hardware has found its way to my desk that has the same issue
> that you experienced. Disabling NAND DMA also fixed the display
> FIFO underflow, but on another variant, it didn't help and we
> need to dig deeper. Were there perhaps any new findings since
> this thread concluded in 2018?

We've since looked deeper into this and found that changing the
AHB port of the LCDC worked around the issue. The other AHB port
connects to a different DDR port and presumably the DDR port
scheduling is less disadvantageous to the LCDC than the
interconnect arbitration on the DDR port shared with the
DMA controller used for NAND.

> On 25.05.18 16:51, Tudor Ambarus wrote:
>> Hi, Peter,
>>
>> On 04/11/2018 06:34 PM, Nicolas Ferre wrote:
>>> I'll try to move forward with your detailed explanation and with my 
>>> contacts within the "product" team internally.
>>
>> We have talked with the hardware team, looks like there is an error in
>> the description of the Master to Slave Access matrix. CPU accesses DDR2
>> port0 through AXI matrix and not AHB. There is no conflict between CPU
>> and LCDC DMA when accessing DDR2 ports. This explains why using CPU
>> helps.
> 
> @Tudor, @Nicolas, Like Peter, I also have a lot of 3s (i.e. highest
> priority for all DMA masters with access to a given slave) preset in
> my matrix configuration. It seems not possible to change these priorities.

I tested again and changing priorities was possible, just not for
the first LCDC master. That one was at the lowest priority and
the best one can do is decreasing other master priorities, but
this did not resolve the issue.

I also tried other things like breaking burst length and setting
default master for the port, but nothing I configured in the MATRIX
registers helped.

> I have yet to try more of the suggestions in this thread. Has there been
> a reply from your hardware team, if there are constraints regarding when
> it's allowed to change MATRIX_PRBS9/10 on the SAMA5D3?

While I have a workaround now, the proper way would still be configuring
PRBS9. @Tudor, @Nicolas, do you know why changing the LCDC bit in that
register is not possible on the SAMA5D3? I tried setting it prior to
Linux boot (and LCDC enabling), but it did not help.

Thanks,
Ahmad

> 
> Thanks in advance,
> Ahmad
> 
> 
>>
>> The slave numbers from "Table 14-3 Master to Slave Access" are wrong.
>> The 7th row  should be removed and all the other rows from below it,
>> shifted up with one level (DDR2 Port 1 is Slave no 7, DDR2 port 2 is
>> Slave no 8, ... , APB1 is slave no 11).
>>
>> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th
>> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND
>> (7th slave).
>>
>> Also, some information about your configuration is useful. Can you
>> please tell us what NAND DMA configuration did you use?  Are you using
>> NAND storage for the videos that you are playing on the LCD screen?
>>
>> Thanks,
>> ta
> 
> 


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