From: Eugen Hristev <eugen.hristev@microchip.com> To: Peter Rosin <peda@axentia.se> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>, Richard Weinberger <richard@nod.at>, Tudor Ambarus <tudor.ambarus@microchip.com>, Josh Wu <rainyfeeling@outlook.com>, Boris Brezillon <boris.brezillon@bootlin.com>, <linux-kernel@vger.kernel.org>, Marek Vasut <marek.vasut@gmail.com>, Ludovic Desroches <ludovic.desroches@microchip.com>, <linux-mtd@lists.infradead.org>, Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>, Brian Norris <computersforpeace@gmail.com>, David Woodhouse <dwmw2@infradead.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Date: Tue, 29 May 2018 10:25:04 +0300 [thread overview] Message-ID: <2726a7b0-56b2-bb7f-ad4a-2a3139ebbb03@microchip.com> (raw) In-Reply-To: <9ae5fc1d-9f02-9742-f801-2252389294eb@axentia.se> On 29.05.2018 10:10, Peter Rosin wrote: > On 2018-05-29 08:30, Eugen Hristev wrote: >> >> >> On 28.05.2018 13:10, Peter Rosin wrote: >>> On 2018-05-28 00:11, Peter Rosin wrote: >>>> On 2018-05-27 11:18, Peter Rosin wrote: >>>>> On 2018-05-25 16:51, Tudor Ambarus wrote: >>>>>> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th >>>>>> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND >>>>>> (7th slave). >>>>> >>>>> Exactly how do I accomplish that? >>>>> >>>>> I can see how I can move the LCD between slave DDR port 2 and 3 by >>>>> selecting LCDC DMA master 8 or 9 (but according to the above it should >>>>> not matter). The big question is how I control what slave the NAND flash >>>>> is going to use? I find nothing in the datasheet, and the code is also >>>>> non-transparent enough for me to figure it out by myself without >>>>> throwing out this question first... >> >> >> [...] >> >>>> and the output is >>>> >>>> atmel-nand-controller 10000000.ebi:nand-controller: using dma0chan5 for DMA transfers >>>> >>>> So, DMA controller 0 is in use. I still don't know if IF0, IF1 or IF2 is used >>>> or how to find out. I guess IF2 is not in use since that does not allow any >>>> DDR2 port as slave... >> >> Hello Peter, >> >> Thank you for all the information, I will chip in to help a little bit. >> The Master/channel is described in the device tree. The channel has a >> controller, a mem/periph interface and a periph ID, plus a FIFO >> configuration. >> >> The dma chan number reported in the dmesg is just software. > > Got that, that was why I added the various additional traces in that > horrid patch in the mail you are responding to :-) > >> Here is an >> example from DT: >> dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, >> <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; >> >> you can match this with the help from >> Documentation/devicetree/bindings/dma/atmel-dma.txt: >> >> 1. A phandle pointing to the DMA controller. >> >> 2. The memory interface (16 most significant bits), the peripheral >> interface >> (16 less significant bits). >> >> 3. Parameters for the at91 DMA configuration register which are device >> >> dependent: >> >> - bit 7-0: peripheral identifier for the hardware handshaking >> interface. The >> identifier can be different for tx and rx. >> >> - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. >> >> >> So , what was Tudor asking for, is your DT for the ebi node (if you are >> using ebi), or, your NFC SRAM (Nand Flash Controller SRAM) DMA >> devicetree chunk, so, we can figure out which type of DMA are you using. >> >> Normally, the ebi should be connected to both DMA0 and DMA1 on those >> interfaces specified in DT. Which ones you want to use, depends on your >> setup (and contention on the bus/accesses, like in your case, the HLCDC) >> >> Thats why we have multiple choices, to pick the right one for each case. >> In our vanilla DT sama5d3.dtsi we do not have DMA described for ebi >> interface. > > Ahh, *that* NAND DMA configuration. Of course, how silly of me... > > This is a setup based on the at91-linea.dtsi "CPU" board. That dtsi should > have the relevant NAND/DMA info. Also, at91-nattis-2-natte-2.dts describes > the older HW (with a 1024x768 panel) that is also affected, if you want a > full device tree to look at. > > Looks like I didn't make a selection, quoting from at91-linea.dtsi: Ok, so try to force the nand to use DDR port 1 : use DMAC0 or DMAC1 on the interfaces corresponding just to DDR port 1, and see if helps (while leaving HLCDC on both masters - DDR port 2 and 3). One more thing: what are the actual nand commands which you use when you get the glitches? read/write/erase ... ? What happens if you try to minimize the nand access? you also said at some point that only *some* nand accesses cause glitches. Another thing : even if the LCD displays a still image, the DMA still feeds data to the LCD right ? > > &ebi { > pinctrl-0 = <&pinctrl_ebi_nand_addr>; > pinctrl-names = "default"; > status = "okay"; > }; > > &nand_controller { > status = "okay"; > > nand: nand@3 { > reg = <0x3 0x0 0x2>; > atmel,rb = <0>; > nand-bus-width = <8>; > nand-ecc-mode = "hw"; > nand-ecc-strength = <4>; > nand-ecc-step-size = <512>; > nand-on-flash-bbt; > label = "atmel_nand"; > }; > }; > > The reason is probably because the sama5d3xek device-trees didn't at the > time of "fork". Does anybody have any suggestion for some extra properties > to try in the above nodes? > > Further, I forgot that I had actually upstreamed linea support for > at91bootstrap, so relevant NAND timings etc can be found in lpddr1_init() > in > > at91bootstrap/contrib/board/axentia/sama5d3_linea/sama5d3_linea.c > > Cheers, > Peter > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
WARNING: multiple messages have this Message-ID (diff)
From: eugen.hristev@microchip.com (Eugen Hristev) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Date: Tue, 29 May 2018 10:25:04 +0300 [thread overview] Message-ID: <2726a7b0-56b2-bb7f-ad4a-2a3139ebbb03@microchip.com> (raw) In-Reply-To: <9ae5fc1d-9f02-9742-f801-2252389294eb@axentia.se> On 29.05.2018 10:10, Peter Rosin wrote: > On 2018-05-29 08:30, Eugen Hristev wrote: >> >> >> On 28.05.2018 13:10, Peter Rosin wrote: >>> On 2018-05-28 00:11, Peter Rosin wrote: >>>> On 2018-05-27 11:18, Peter Rosin wrote: >>>>> On 2018-05-25 16:51, Tudor Ambarus wrote: >>>>>> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th >>>>>> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND >>>>>> (7th slave). >>>>> >>>>> Exactly how do I accomplish that? >>>>> >>>>> I can see how I can move the LCD between slave DDR port 2 and 3 by >>>>> selecting LCDC DMA master 8 or 9 (but according to the above it should >>>>> not matter). The big question is how I control what slave the NAND flash >>>>> is going to use? I find nothing in the datasheet, and the code is also >>>>> non-transparent enough for me to figure it out by myself without >>>>> throwing out this question first... >> >> >> [...] >> >>>> and the output is >>>> >>>> atmel-nand-controller 10000000.ebi:nand-controller: using dma0chan5 for DMA transfers >>>> >>>> So, DMA controller 0 is in use. I still don't know if IF0, IF1 or IF2 is used >>>> or how to find out. I guess IF2 is not in use since that does not allow any >>>> DDR2 port as slave... >> >> Hello Peter, >> >> Thank you for all the information, I will chip in to help a little bit. >> The Master/channel is described in the device tree. The channel has a >> controller, a mem/periph interface and a periph ID, plus a FIFO >> configuration. >> >> The dma chan number reported in the dmesg is just software. > > Got that, that was why I added the various additional traces in that > horrid patch in the mail you are responding to :-) > >> Here is an >> example from DT: >> dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, >> <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; >> >> you can match this with the help from >> Documentation/devicetree/bindings/dma/atmel-dma.txt: >> >> 1. A phandle pointing to the DMA controller. >> >> 2. The memory interface (16 most significant bits), the peripheral >> interface >> (16 less significant bits). >> >> 3. Parameters for the at91 DMA configuration register which are device >> >> dependent: >> >> - bit 7-0: peripheral identifier for the hardware handshaking >> interface. The >> identifier can be different for tx and rx. >> >> - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. >> >> >> So , what was Tudor asking for, is your DT for the ebi node (if you are >> using ebi), or, your NFC SRAM (Nand Flash Controller SRAM) DMA >> devicetree chunk, so, we can figure out which type of DMA are you using. >> >> Normally, the ebi should be connected to both DMA0 and DMA1 on those >> interfaces specified in DT. Which ones you want to use, depends on your >> setup (and contention on the bus/accesses, like in your case, the HLCDC) >> >> Thats why we have multiple choices, to pick the right one for each case. >> In our vanilla DT sama5d3.dtsi we do not have DMA described for ebi >> interface. > > Ahh, *that* NAND DMA configuration. Of course, how silly of me... > > This is a setup based on the at91-linea.dtsi "CPU" board. That dtsi should > have the relevant NAND/DMA info. Also, at91-nattis-2-natte-2.dts describes > the older HW (with a 1024x768 panel) that is also affected, if you want a > full device tree to look at. > > Looks like I didn't make a selection, quoting from at91-linea.dtsi: Ok, so try to force the nand to use DDR port 1 : use DMAC0 or DMAC1 on the interfaces corresponding just to DDR port 1, and see if helps (while leaving HLCDC on both masters - DDR port 2 and 3). One more thing: what are the actual nand commands which you use when you get the glitches? read/write/erase ... ? What happens if you try to minimize the nand access? you also said at some point that only *some* nand accesses cause glitches. Another thing : even if the LCD displays a still image, the DMA still feeds data to the LCD right ? > > &ebi { > pinctrl-0 = <&pinctrl_ebi_nand_addr>; > pinctrl-names = "default"; > status = "okay"; > }; > > &nand_controller { > status = "okay"; > > nand: nand at 3 { > reg = <0x3 0x0 0x2>; > atmel,rb = <0>; > nand-bus-width = <8>; > nand-ecc-mode = "hw"; > nand-ecc-strength = <4>; > nand-ecc-step-size = <512>; > nand-on-flash-bbt; > label = "atmel_nand"; > }; > }; > > The reason is probably because the sama5d3xek device-trees didn't at the > time of "fork". Does anybody have any suggestion for some extra properties > to try in the above nodes? > > Further, I forgot that I had actually upstreamed linea support for > at91bootstrap, so relevant NAND timings etc can be found in lpddr1_init() > in > > at91bootstrap/contrib/board/axentia/sama5d3_linea/sama5d3_linea.c > > Cheers, > Peter > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
next prev parent reply other threads:[~2018-05-29 7:27 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-29 13:10 [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin 2018-03-29 13:10 ` Peter Rosin 2018-03-29 13:33 ` Boris Brezillon 2018-03-29 13:33 ` Boris Brezillon 2018-03-29 13:37 ` Peter Rosin 2018-03-29 13:37 ` Peter Rosin 2018-03-29 13:44 ` Boris Brezillon 2018-03-29 13:44 ` Boris Brezillon 2018-03-29 14:27 ` Peter Rosin 2018-03-29 14:27 ` Peter Rosin 2018-03-30 21:43 ` Peter Rosin 2018-03-30 21:43 ` Peter Rosin 2018-04-02 12:22 ` Boris Brezillon 2018-04-02 12:22 ` Boris Brezillon 2018-04-02 17:59 ` Peter Rosin 2018-04-02 17:59 ` Peter Rosin 2018-04-02 19:28 ` Boris Brezillon 2018-04-02 19:28 ` Boris Brezillon 2018-04-02 20:20 ` Boris Brezillon 2018-04-02 20:20 ` Boris Brezillon 2018-04-02 20:32 ` Boris Brezillon 2018-04-02 20:32 ` Boris Brezillon 2018-04-03 6:11 ` Peter Rosin 2018-04-03 6:11 ` Peter Rosin 2018-04-03 7:18 ` Boris Brezillon 2018-04-03 7:18 ` Boris Brezillon 2018-04-11 14:44 ` Peter Rosin 2018-04-11 14:44 ` Peter Rosin 2018-04-11 14:59 ` Boris Brezillon 2018-04-11 14:59 ` Boris Brezillon 2018-04-11 15:10 ` Peter Rosin 2018-04-11 15:10 ` Peter Rosin 2018-04-11 15:34 ` Boris Brezillon 2018-04-11 15:34 ` Boris Brezillon 2018-04-11 15:34 ` Nicolas Ferre 2018-04-11 15:34 ` Nicolas Ferre 2018-04-12 7:18 ` Peter Rosin 2018-04-12 7:18 ` Peter Rosin 2018-05-22 18:03 ` Peter Rosin 2018-05-22 18:03 ` Peter Rosin 2018-05-23 10:42 ` Boris Brezillon 2018-05-23 10:42 ` Boris Brezillon 2018-05-25 14:51 ` Tudor Ambarus 2018-05-25 14:51 ` Tudor Ambarus 2018-05-26 17:40 ` Peter Rosin 2018-05-26 17:40 ` Peter Rosin 2018-05-27 9:18 ` Peter Rosin 2018-05-27 9:18 ` Peter Rosin 2018-05-27 22:11 ` Peter Rosin 2018-05-27 22:11 ` Peter Rosin 2018-05-28 10:10 ` Peter Rosin 2018-05-28 10:10 ` Peter Rosin 2018-05-28 14:27 ` Boris Brezillon 2018-05-28 14:27 ` Boris Brezillon 2018-05-28 15:52 ` Peter Rosin 2018-05-28 15:52 ` Peter Rosin 2018-05-28 16:09 ` Boris Brezillon 2018-05-28 16:09 ` Boris Brezillon 2018-05-28 16:09 ` Nicolas Ferre 2018-05-28 16:09 ` Nicolas Ferre 2018-05-29 6:30 ` Eugen Hristev 2018-05-29 6:30 ` Eugen Hristev 2018-05-29 7:10 ` Peter Rosin 2018-05-29 7:10 ` Peter Rosin 2018-05-29 7:25 ` Eugen Hristev [this message] 2018-05-29 7:25 ` Eugen Hristev 2018-05-29 14:49 ` Boris Brezillon 2018-05-29 14:49 ` Boris Brezillon 2018-05-29 15:01 ` Eugen Hristev 2018-05-29 15:01 ` Eugen Hristev 2018-05-29 15:15 ` Boris Brezillon 2018-05-29 15:15 ` Boris Brezillon 2018-05-29 15:21 ` Eugen Hristev 2018-05-29 15:21 ` Eugen Hristev 2018-05-29 15:46 ` Boris Brezillon 2018-05-29 15:46 ` Boris Brezillon 2018-05-29 17:57 ` Boris Brezillon 2018-05-29 17:57 ` Boris Brezillon 2018-05-29 21:37 ` Peter Rosin 2018-05-29 21:37 ` Peter Rosin 2018-06-04 15:46 ` Tudor Ambarus 2018-06-04 15:46 ` Tudor Ambarus 2018-06-04 16:03 ` Boris Brezillon 2018-06-04 16:03 ` Boris Brezillon 2022-06-16 15:54 ` SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma) Ahmad Fatoum 2022-07-25 14:17 ` Ahmad Fatoum 2022-07-28 8:03 ` Tudor.Ambarus 2018-04-03 6:51 ` [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin 2018-04-03 6:51 ` Peter Rosin 2018-04-03 7:15 ` Boris Brezillon 2018-04-03 7:15 ` Boris Brezillon 2018-04-03 7:32 ` Boris Brezillon 2018-04-03 7:32 ` Boris Brezillon 2018-04-03 8:14 ` Peter Rosin 2018-04-03 8:14 ` Peter Rosin 2018-04-03 8:30 ` Boris Brezillon 2018-04-03 8:30 ` Boris Brezillon 2018-04-02 20:23 ` Peter Rosin 2018-04-02 20:23 ` Peter Rosin 2018-04-02 20:35 ` Boris Brezillon 2018-04-02 20:35 ` Boris Brezillon 2018-04-03 7:18 ` Alexandre Belloni 2018-04-03 7:18 ` Alexandre Belloni 2018-04-03 8:37 ` Peter Rosin 2018-04-03 8:37 ` Peter Rosin 2018-03-29 14:20 ` Nicolas Ferre 2018-03-29 14:20 ` Nicolas Ferre 2018-03-29 14:23 ` Peter Rosin 2018-03-29 14:23 ` Peter Rosin 2018-03-29 14:29 ` Boris Brezillon 2018-03-29 14:29 ` Boris Brezillon 2018-06-18 8:39 ` Boris Brezillon 2018-06-18 8:39 ` Boris Brezillon 2018-06-18 14:00 ` Miquel Raynal 2018-06-18 14:00 ` Miquel Raynal 2018-06-25 12:31 ` Miquel Raynal 2018-06-25 12:31 ` Miquel Raynal
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