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From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: Nicolas Ferre <nicolas.ferre@microchip.com>,
	Peter Rosin <peda@axentia.se>,
	Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Josh Wu <rainyfeeling@outlook.com>,
	Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
	<linux-kernel@vger.kernel.org>,
	Boris Brezillon <boris.brezillon@bootlin.com>,
	<linux-mtd@lists.infradead.org>,
	Richard Weinberger <richard@nod.at>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Eugen Hristev <eugen.hristev@microchip.com>
Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
Date: Fri, 25 May 2018 17:51:36 +0300	[thread overview]
Message-ID: <a25ca617-d3da-d401-1ba9-8e5887f8a8e5@microchip.com> (raw)
In-Reply-To: <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com>

Hi, Peter,

On 04/11/2018 06:34 PM, Nicolas Ferre wrote:
> I'll try to move forward with your detailed explanation and with my 
> contacts within the "product" team internally.

We have talked with the hardware team, looks like there is an error in
the description of the Master to Slave Access matrix. CPU accesses DDR2
port0 through AXI matrix and not AHB. There is no conflict between CPU
and LCDC DMA when accessing DDR2 ports. This explains why using CPU
helps.

The slave numbers from "Table 14-3 Master to Slave Access" are wrong.
The 7th row  should be removed and all the other rows from below it,
shifted up with one level (DDR2 Port 1 is Slave no 7, DDR2 port 2 is
Slave no 8, ... , APB1 is slave no 11).

We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th
slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND
(7th slave).

Also, some information about your configuration is useful. Can you
please tell us what NAND DMA configuration did you use?  Are you using
NAND storage for the videos that you are playing on the LCD screen?

Thanks,
ta

WARNING: multiple messages have this Message-ID (diff)
From: tudor.ambarus@microchip.com (Tudor Ambarus)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
Date: Fri, 25 May 2018 17:51:36 +0300	[thread overview]
Message-ID: <a25ca617-d3da-d401-1ba9-8e5887f8a8e5@microchip.com> (raw)
In-Reply-To: <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com>

Hi, Peter,

On 04/11/2018 06:34 PM, Nicolas Ferre wrote:
> I'll try to move forward with your detailed explanation and with my 
> contacts within the "product" team internally.

We have talked with the hardware team, looks like there is an error in
the description of the Master to Slave Access matrix. CPU accesses DDR2
port0 through AXI matrix and not AHB. There is no conflict between CPU
and LCDC DMA when accessing DDR2 ports. This explains why using CPU
helps.

The slave numbers from "Table 14-3 Master to Slave Access" are wrong.
The 7th row  should be removed and all the other rows from below it,
shifted up with one level (DDR2 Port 1 is Slave no 7, DDR2 port 2 is
Slave no 8, ... , APB1 is slave no 11).

We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th
slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND
(7th slave).

Also, some information about your configuration is useful. Can you
please tell us what NAND DMA configuration did you use?  Are you using
NAND storage for the videos that you are playing on the LCD screen?

Thanks,
ta

  parent reply	other threads:[~2018-05-25 14:51 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 13:10 [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin
2018-03-29 13:10 ` Peter Rosin
2018-03-29 13:33 ` Boris Brezillon
2018-03-29 13:33   ` Boris Brezillon
2018-03-29 13:37   ` Peter Rosin
2018-03-29 13:37     ` Peter Rosin
2018-03-29 13:44     ` Boris Brezillon
2018-03-29 13:44       ` Boris Brezillon
2018-03-29 14:27       ` Peter Rosin
2018-03-29 14:27         ` Peter Rosin
2018-03-30 21:43         ` Peter Rosin
2018-03-30 21:43           ` Peter Rosin
2018-04-02 12:22         ` Boris Brezillon
2018-04-02 12:22           ` Boris Brezillon
2018-04-02 17:59           ` Peter Rosin
2018-04-02 17:59             ` Peter Rosin
2018-04-02 19:28             ` Boris Brezillon
2018-04-02 19:28               ` Boris Brezillon
2018-04-02 20:20               ` Boris Brezillon
2018-04-02 20:20                 ` Boris Brezillon
2018-04-02 20:32                 ` Boris Brezillon
2018-04-02 20:32                   ` Boris Brezillon
2018-04-03  6:11                 ` Peter Rosin
2018-04-03  6:11                   ` Peter Rosin
2018-04-03  7:18                   ` Boris Brezillon
2018-04-03  7:18                     ` Boris Brezillon
2018-04-11 14:44                     ` Peter Rosin
2018-04-11 14:44                       ` Peter Rosin
2018-04-11 14:59                       ` Boris Brezillon
2018-04-11 14:59                         ` Boris Brezillon
2018-04-11 15:10                         ` Peter Rosin
2018-04-11 15:10                           ` Peter Rosin
2018-04-11 15:34                           ` Boris Brezillon
2018-04-11 15:34                             ` Boris Brezillon
2018-04-11 15:34                       ` Nicolas Ferre
2018-04-11 15:34                         ` Nicolas Ferre
2018-04-12  7:18                         ` Peter Rosin
2018-04-12  7:18                           ` Peter Rosin
2018-05-22 18:03                         ` Peter Rosin
2018-05-22 18:03                           ` Peter Rosin
2018-05-23 10:42                           ` Boris Brezillon
2018-05-23 10:42                             ` Boris Brezillon
2018-05-25 14:51                         ` Tudor Ambarus [this message]
2018-05-25 14:51                           ` Tudor Ambarus
2018-05-26 17:40                           ` Peter Rosin
2018-05-26 17:40                             ` Peter Rosin
2018-05-27  9:18                           ` Peter Rosin
2018-05-27  9:18                             ` Peter Rosin
2018-05-27 22:11                             ` Peter Rosin
2018-05-27 22:11                               ` Peter Rosin
2018-05-28 10:10                               ` Peter Rosin
2018-05-28 10:10                                 ` Peter Rosin
2018-05-28 14:27                                 ` Boris Brezillon
2018-05-28 14:27                                   ` Boris Brezillon
2018-05-28 15:52                                   ` Peter Rosin
2018-05-28 15:52                                     ` Peter Rosin
2018-05-28 16:09                                     ` Boris Brezillon
2018-05-28 16:09                                       ` Boris Brezillon
2018-05-28 16:09                                     ` Nicolas Ferre
2018-05-28 16:09                                       ` Nicolas Ferre
2018-05-29  6:30                                 ` Eugen Hristev
2018-05-29  6:30                                   ` Eugen Hristev
2018-05-29  7:10                                   ` Peter Rosin
2018-05-29  7:10                                     ` Peter Rosin
2018-05-29  7:25                                     ` Eugen Hristev
2018-05-29  7:25                                       ` Eugen Hristev
2018-05-29 14:49                                   ` Boris Brezillon
2018-05-29 14:49                                     ` Boris Brezillon
2018-05-29 15:01                                     ` Eugen Hristev
2018-05-29 15:01                                       ` Eugen Hristev
2018-05-29 15:15                                       ` Boris Brezillon
2018-05-29 15:15                                         ` Boris Brezillon
2018-05-29 15:21                                         ` Eugen Hristev
2018-05-29 15:21                                           ` Eugen Hristev
2018-05-29 15:46                                           ` Boris Brezillon
2018-05-29 15:46                                             ` Boris Brezillon
2018-05-29 17:57                                             ` Boris Brezillon
2018-05-29 17:57                                               ` Boris Brezillon
2018-05-29 21:37                                               ` Peter Rosin
2018-05-29 21:37                                                 ` Peter Rosin
2018-06-04 15:46                                 ` Tudor Ambarus
2018-06-04 15:46                                   ` Tudor Ambarus
2018-06-04 16:03                                   ` Boris Brezillon
2018-06-04 16:03                                     ` Boris Brezillon
2022-06-16 15:54                           ` SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma) Ahmad Fatoum
2022-07-25 14:17                             ` Ahmad Fatoum
2022-07-28  8:03                               ` Tudor.Ambarus
2018-04-03  6:51                 ` [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin
2018-04-03  6:51                   ` Peter Rosin
2018-04-03  7:15                   ` Boris Brezillon
2018-04-03  7:15                     ` Boris Brezillon
2018-04-03  7:32                     ` Boris Brezillon
2018-04-03  7:32                       ` Boris Brezillon
2018-04-03  8:14                     ` Peter Rosin
2018-04-03  8:14                       ` Peter Rosin
2018-04-03  8:30                       ` Boris Brezillon
2018-04-03  8:30                         ` Boris Brezillon
2018-04-02 20:23               ` Peter Rosin
2018-04-02 20:23                 ` Peter Rosin
2018-04-02 20:35                 ` Boris Brezillon
2018-04-02 20:35                   ` Boris Brezillon
2018-04-03  7:18                 ` Alexandre Belloni
2018-04-03  7:18                   ` Alexandre Belloni
2018-04-03  8:37                   ` Peter Rosin
2018-04-03  8:37                     ` Peter Rosin
2018-03-29 14:20 ` Nicolas Ferre
2018-03-29 14:20   ` Nicolas Ferre
2018-03-29 14:23   ` Peter Rosin
2018-03-29 14:23     ` Peter Rosin
2018-03-29 14:29   ` Boris Brezillon
2018-03-29 14:29     ` Boris Brezillon
2018-06-18  8:39 ` Boris Brezillon
2018-06-18  8:39   ` Boris Brezillon
2018-06-18 14:00   ` Miquel Raynal
2018-06-18 14:00     ` Miquel Raynal
2018-06-25 12:31   ` Miquel Raynal
2018-06-25 12:31     ` Miquel Raynal

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