SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma)

From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Peter Rosin <peda@axentia.se>,
	Tudor Ambarus <tudor.ambarus@microchip.com>,
	nicolas.ferre@microchip.com, boris.brezillon@collabora.com
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	Ludovic Desroches <ludovic.desroches@microchip.com>
Subject: SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma)
Date: Thu, 16 Jun 2022 17:54:54 +0200	[thread overview]
Message-ID: <2c7059f9-13f2-1418-cc66-7a6ed111175f@pengutronix.de> (raw)
In-Reply-To: <a25ca617-d3da-d401-1ba9-8e5887f8a8e5@microchip.com>

Hello Peter,

Hardware has found its way to my desk that has the same issue
that you experienced. Disabling NAND DMA also fixed the display
FIFO underflow, but on another variant, it didn't help and we
need to dig deeper. Were there perhaps any new findings since
this thread concluded in 2018?

On 25.05.18 16:51, Tudor Ambarus wrote:
> Hi, Peter,
> 
> On 04/11/2018 06:34 PM, Nicolas Ferre wrote:
>> I'll try to move forward with your detailed explanation and with my 
>> contacts within the "product" team internally.
> 
> We have talked with the hardware team, looks like there is an error in
> the description of the Master to Slave Access matrix. CPU accesses DDR2
> port0 through AXI matrix and not AHB. There is no conflict between CPU
> and LCDC DMA when accessing DDR2 ports. This explains why using CPU
> helps.

@Tudor, @Nicolas, Like Peter, I also have a lot of 3s (i.e. highest
priority for all DMA masters with access to a given slave) preset in
my matrix configuration. It seems not possible to change these priorities.
I have yet to try more of the suggestions in this thread. Has there been
a reply from your hardware team, if there are constraints regarding when
it's allowed to change MATRIX_PRBS9/10 on the SAMA5D3?

Thanks in advance,
Ahmad

> 
> The slave numbers from "Table 14-3 Master to Slave Access" are wrong.
> The 7th row  should be removed and all the other rows from below it,
> shifted up with one level (DDR2 Port 1 is Slave no 7, DDR2 port 2 is
> Slave no 8, ... , APB1 is slave no 11).
> 
> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th
> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND
> (7th slave).
> 
> Also, some information about your configuration is useful. Can you
> please tell us what NAND DMA configuration did you use?  Are you using
> NAND storage for the videos that you are playing on the LCD screen?
> 
> Thanks,
> ta

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