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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v3 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks
Date: Mon, 14 Dec 2020 12:34:31 -0800	[thread overview]
Message-ID: <1d0407a7fd46da8eb17315fa9450021f13722fed.1607967113.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1607967113.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a2787b1d48..1fc9273cea 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -446,11 +446,13 @@ restart:
             return TRANSLATE_PMP_FAIL;
         }
 
-#if defined(TARGET_RISCV32)
-        target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
-#elif defined(TARGET_RISCV64)
-        target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
-#endif
+        target_ulong pte;
+        if (riscv_cpu_is_32bit(env)) {
+            pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
+        } else {
+            pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
+        }
+
         if (res != MEMTX_OK) {
             return TRANSLATE_FAIL;
         }
-- 
2.29.2



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com
Subject: [PATCH v3 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks
Date: Mon, 14 Dec 2020 12:34:31 -0800	[thread overview]
Message-ID: <1d0407a7fd46da8eb17315fa9450021f13722fed.1607967113.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1607967113.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a2787b1d48..1fc9273cea 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -446,11 +446,13 @@ restart:
             return TRANSLATE_PMP_FAIL;
         }
 
-#if defined(TARGET_RISCV32)
-        target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
-#elif defined(TARGET_RISCV64)
-        target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
-#endif
+        target_ulong pte;
+        if (riscv_cpu_is_32bit(env)) {
+            pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
+        } else {
+            pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
+        }
+
         if (res != MEMTX_OK) {
             return TRANSLATE_FAIL;
         }
-- 
2.29.2



  parent reply	other threads:[~2020-12-14 20:46 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-14 20:33 [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-12-14 20:33 ` Alistair Francis
2020-12-14 20:33 ` [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-14 20:33   ` Alistair Francis
2020-12-15  9:26   ` Bin Meng
2020-12-15  9:26     ` Bin Meng
2020-12-15 16:44     ` Alistair Francis
2020-12-15 16:44       ` Alistair Francis
2020-12-15 21:25       ` Richard Henderson
2020-12-15 21:25         ` Richard Henderson
2020-12-16 18:16         ` Alistair Francis
2020-12-16 18:16           ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 03/15] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 04/15] riscv: virt: " Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 06/15] hw/riscv: virt: " Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 07/15] hw/riscv: spike: " Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 08/15] hw/riscv: sifive_u: " Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-15  9:38   ` Bin Meng
2020-12-15  9:38     ` Bin Meng
2020-12-15 15:13     ` Richard Henderson
2020-12-15 15:13       ` Richard Henderson
2020-12-15 17:15       ` Alistair Francis
2020-12-15 17:15         ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-14 20:34 ` Alistair Francis [this message]
2020-12-14 20:34   ` [PATCH v3 13/15] target/riscv: cpu_helper: " Alistair Francis
2020-12-14 20:34 ` [PATCH v3 14/15] target/riscv: csr: " Alistair Francis
2020-12-14 20:34   ` Alistair Francis
2020-12-15 13:27   ` Bin Meng
2020-12-15 13:27     ` Bin Meng
2020-12-14 20:34 ` [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-14 20:34   ` Alistair Francis

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