From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros
Date: Tue, 15 Dec 2020 09:13:18 -0600 [thread overview]
Message-ID: <97fe497a-06c0-43e4-3144-eee0c439686a@linaro.org> (raw)
In-Reply-To: <CAEUhbmUhKuhEPU=RyRN3CVYDh=oGoQF1e-tSX=jODw4c2Ub1kA@mail.gmail.com>
On 12/15/20 3:38 AM, Bin Meng wrote:
>> #if defined(TARGET_RISCV64)
>> -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
>> +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> return float32_to_int64(frs1, &env->fp_status);
>
> float32_to_int64() returns int64_t, so there is a truncation if
> changing it to target_ulong for 32-bit.
There's not, because this function isn't defined for 32-bit (see first quoted
line). But this point of confusion is exactly what I pointed out vs the
previous revision.
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros
Date: Tue, 15 Dec 2020 09:13:18 -0600 [thread overview]
Message-ID: <97fe497a-06c0-43e4-3144-eee0c439686a@linaro.org> (raw)
In-Reply-To: <CAEUhbmUhKuhEPU=RyRN3CVYDh=oGoQF1e-tSX=jODw4c2Ub1kA@mail.gmail.com>
On 12/15/20 3:38 AM, Bin Meng wrote:
>> #if defined(TARGET_RISCV64)
>> -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
>> +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> return float32_to_int64(frs1, &env->fp_status);
>
> float32_to_int64() returns int64_t, so there is a truncation if
> changing it to target_ulong for 32-bit.
There's not, because this function isn't defined for 32-bit (see first quoted
line). But this point of confusion is exactly what I pointed out vs the
previous revision.
r~
next prev parent reply other threads:[~2020-12-15 15:14 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-14 20:33 [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-12-14 20:33 ` Alistair Francis
2020-12-14 20:33 ` [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-14 20:33 ` Alistair Francis
2020-12-15 9:26 ` Bin Meng
2020-12-15 9:26 ` Bin Meng
2020-12-15 16:44 ` Alistair Francis
2020-12-15 16:44 ` Alistair Francis
2020-12-15 21:25 ` Richard Henderson
2020-12-15 21:25 ` Richard Henderson
2020-12-16 18:16 ` Alistair Francis
2020-12-16 18:16 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 03/15] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 04/15] riscv: virt: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 06/15] hw/riscv: virt: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 07/15] hw/riscv: spike: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 08/15] hw/riscv: sifive_u: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-15 9:38 ` Bin Meng
2020-12-15 9:38 ` Bin Meng
2020-12-15 15:13 ` Richard Henderson [this message]
2020-12-15 15:13 ` Richard Henderson
2020-12-15 17:15 ` Alistair Francis
2020-12-15 17:15 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 13/15] target/riscv: cpu_helper: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-14 20:34 ` [PATCH v3 14/15] target/riscv: csr: " Alistair Francis
2020-12-14 20:34 ` Alistair Francis
2020-12-15 13:27 ` Bin Meng
2020-12-15 13:27 ` Bin Meng
2020-12-14 20:34 ` [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-14 20:34 ` Alistair Francis
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