From: Alistair Francis <alistair23@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Date: Wed, 16 Dec 2020 10:16:07 -0800 [thread overview] Message-ID: <CAKmqyKO-Wk4fVHzq2Gta3AZ+-gg3__-1qS1N9meFKJgxpbV2kw@mail.gmail.com> (raw) In-Reply-To: <759b5711-6b07-819f-4d11-0acf7b6ceed5@linaro.org> On Tue, Dec 15, 2020 at 1:25 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 12/15/20 10:44 AM, Alistair Francis wrote: > > On Tue, Dec 15, 2020 at 1:26 AM Bin Meng <bmeng.cn@gmail.com> wrote: > >> > >> On Tue, Dec 15, 2020 at 4:34 AM Alistair Francis > >> <alistair.francis@wdc.com> wrote: > >>> > >>> Currently the riscv_is_32_bit() function only supports the generic rv32 > >>> CPUs. Extend the function to support the SiFive and LowRISC CPUs as > >>> well. > >>> > >>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > >>> --- > >>> hw/riscv/boot.c | 12 +++++++++++- > >>> 1 file changed, 11 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >>> index d62f3dc758..3c70ac75d7 100644 > >>> --- a/hw/riscv/boot.c > >>> +++ b/hw/riscv/boot.c > >>> @@ -41,7 +41,17 @@ > >>> > >>> bool riscv_is_32_bit(MachineState *machine) > >>> { > >>> - if (!strncmp(machine->cpu_type, "rv32", 4)) { > >>> + /* > >>> + * To determine if the CPU is 32-bit we need to check a few different CPUs. > >>> + * > >>> + * If the CPU starts with rv32 > >>> + * If the CPU is a sifive 3 seriries CPU (E31, U34) > >>> + * If it's the Ibex CPU > >>> + */ > >>> + if (!strncmp(machine->cpu_type, "rv32", 4) || > >>> + (!strncmp(machine->cpu_type, "sifive", 6) && > >>> + machine->cpu_type[8] == '3') || > >>> + !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { > >> > >> This does not look like a scalable way. With more and more CPU added > >> in the future, this may end up with a huge list of strncmps.. > > > > Any better ideas? > > It doesn't appear as if you need to query this before you've instantiated the > cpu. The first dynamic use that I see is create_fdt, which happens after that > point. > > Verified like so: > > $ gdb --args ./qemu-system-riscv64 -M virt > (gdb) b rv64_base_cpu_init > Breakpoint 1 at 0x548390: file ../qemu/target/riscv/cpu.c, line 156. > (gdb) b riscv_is_32_bit > Breakpoint 2 at 0x490dd0: file ../qemu/hw/riscv/boot.c, line 37. > (gdb) run > ... > Thread 1 "qemu-system-ris" hit Breakpoint 1, rv64_base_cpu_init > > >From the machine, you can find the boot cpu, and use the riscv_cpu_is_32bit > helper on that. > > Also, just noticed that the two functions spell "32bit" differently. :-) Thanks for the help Richard. I have added a commit in v4 that changes the function like you mention. The rebased ended up being a little tricky so I added the commit to the end instead. Alistair > > > r~
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Date: Wed, 16 Dec 2020 10:16:07 -0800 [thread overview] Message-ID: <CAKmqyKO-Wk4fVHzq2Gta3AZ+-gg3__-1qS1N9meFKJgxpbV2kw@mail.gmail.com> (raw) In-Reply-To: <759b5711-6b07-819f-4d11-0acf7b6ceed5@linaro.org> On Tue, Dec 15, 2020 at 1:25 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 12/15/20 10:44 AM, Alistair Francis wrote: > > On Tue, Dec 15, 2020 at 1:26 AM Bin Meng <bmeng.cn@gmail.com> wrote: > >> > >> On Tue, Dec 15, 2020 at 4:34 AM Alistair Francis > >> <alistair.francis@wdc.com> wrote: > >>> > >>> Currently the riscv_is_32_bit() function only supports the generic rv32 > >>> CPUs. Extend the function to support the SiFive and LowRISC CPUs as > >>> well. > >>> > >>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > >>> --- > >>> hw/riscv/boot.c | 12 +++++++++++- > >>> 1 file changed, 11 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >>> index d62f3dc758..3c70ac75d7 100644 > >>> --- a/hw/riscv/boot.c > >>> +++ b/hw/riscv/boot.c > >>> @@ -41,7 +41,17 @@ > >>> > >>> bool riscv_is_32_bit(MachineState *machine) > >>> { > >>> - if (!strncmp(machine->cpu_type, "rv32", 4)) { > >>> + /* > >>> + * To determine if the CPU is 32-bit we need to check a few different CPUs. > >>> + * > >>> + * If the CPU starts with rv32 > >>> + * If the CPU is a sifive 3 seriries CPU (E31, U34) > >>> + * If it's the Ibex CPU > >>> + */ > >>> + if (!strncmp(machine->cpu_type, "rv32", 4) || > >>> + (!strncmp(machine->cpu_type, "sifive", 6) && > >>> + machine->cpu_type[8] == '3') || > >>> + !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { > >> > >> This does not look like a scalable way. With more and more CPU added > >> in the future, this may end up with a huge list of strncmps.. > > > > Any better ideas? > > It doesn't appear as if you need to query this before you've instantiated the > cpu. The first dynamic use that I see is create_fdt, which happens after that > point. > > Verified like so: > > $ gdb --args ./qemu-system-riscv64 -M virt > (gdb) b rv64_base_cpu_init > Breakpoint 1 at 0x548390: file ../qemu/target/riscv/cpu.c, line 156. > (gdb) b riscv_is_32_bit > Breakpoint 2 at 0x490dd0: file ../qemu/hw/riscv/boot.c, line 37. > (gdb) run > ... > Thread 1 "qemu-system-ris" hit Breakpoint 1, rv64_base_cpu_init > > >From the machine, you can find the boot cpu, and use the riscv_cpu_is_32bit > helper on that. > > Also, just noticed that the two functions spell "32bit" differently. :-) Thanks for the help Richard. I have added a commit in v4 that changes the function like you mention. The rebased ended up being a little tricky so I added the commit to the end instead. Alistair > > > r~
next prev parent reply other threads:[~2020-12-16 18:17 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-14 20:33 [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis 2020-12-14 20:33 ` Alistair Francis 2020-12-14 20:33 ` [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis 2020-12-14 20:33 ` Alistair Francis 2020-12-15 9:26 ` Bin Meng 2020-12-15 9:26 ` Bin Meng 2020-12-15 16:44 ` Alistair Francis 2020-12-15 16:44 ` Alistair Francis 2020-12-15 21:25 ` Richard Henderson 2020-12-15 21:25 ` Richard Henderson 2020-12-16 18:16 ` Alistair Francis [this message] 2020-12-16 18:16 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 03/15] riscv: spike: Remove target macro conditionals Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 04/15] riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 06/15] hw/riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 07/15] hw/riscv: spike: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 08/15] hw/riscv: sifive_u: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 9:38 ` Bin Meng 2020-12-15 9:38 ` Bin Meng 2020-12-15 15:13 ` Richard Henderson 2020-12-15 15:13 ` Richard Henderson 2020-12-15 17:15 ` Alistair Francis 2020-12-15 17:15 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 13/15] target/riscv: cpu_helper: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 14/15] target/riscv: csr: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 13:27 ` Bin Meng 2020-12-15 13:27 ` Bin Meng 2020-12-14 20:34 ` [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis 2020-12-14 20:34 ` Alistair Francis
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