From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Date: Mon, 14 Dec 2020 12:33:56 -0800 [thread overview] Message-ID: <cover.1607967113.git.alistair.francis@wdc.com> (raw) The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. v3: - Address Richard's comments v2: - Rebase on the latest RISC-V tree Alistair Francis (15): hw/riscv: Expand the is 32-bit check to support more CPUs target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target include/hw/riscv/boot.h | 8 +- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 4 +- hw/riscv/boot.c | 67 +++++++++------ hw/riscv/sifive_u.c | 57 ++++++------ hw/riscv/spike.c | 50 ++++++----- hw/riscv/virt.c | 36 ++++---- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu_helper.c | 12 +-- target/riscv/csr.c | 176 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 16 ++-- 13 files changed, 295 insertions(+), 235 deletions(-) -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Date: Mon, 14 Dec 2020 12:33:56 -0800 [thread overview] Message-ID: <cover.1607967113.git.alistair.francis@wdc.com> (raw) The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. v3: - Address Richard's comments v2: - Rebase on the latest RISC-V tree Alistair Francis (15): hw/riscv: Expand the is 32-bit check to support more CPUs target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target include/hw/riscv/boot.h | 8 +- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 4 +- hw/riscv/boot.c | 67 +++++++++------ hw/riscv/sifive_u.c | 57 ++++++------ hw/riscv/spike.c | 50 ++++++----- hw/riscv/virt.c | 36 ++++---- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu_helper.c | 12 +-- target/riscv/csr.c | 176 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 16 ++-- 13 files changed, 295 insertions(+), 235 deletions(-) -- 2.29.2
next reply other threads:[~2020-12-14 20:35 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-14 20:33 Alistair Francis [this message] 2020-12-14 20:33 ` [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess Alistair Francis 2020-12-14 20:33 ` [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis 2020-12-14 20:33 ` Alistair Francis 2020-12-15 9:26 ` Bin Meng 2020-12-15 9:26 ` Bin Meng 2020-12-15 16:44 ` Alistair Francis 2020-12-15 16:44 ` Alistair Francis 2020-12-15 21:25 ` Richard Henderson 2020-12-15 21:25 ` Richard Henderson 2020-12-16 18:16 ` Alistair Francis 2020-12-16 18:16 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 03/15] riscv: spike: Remove target macro conditionals Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 04/15] riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 06/15] hw/riscv: virt: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 07/15] hw/riscv: spike: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 08/15] hw/riscv: sifive_u: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 9:38 ` Bin Meng 2020-12-15 9:38 ` Bin Meng 2020-12-15 15:13 ` Richard Henderson 2020-12-15 15:13 ` Richard Henderson 2020-12-15 17:15 ` Alistair Francis 2020-12-15 17:15 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 13/15] target/riscv: cpu_helper: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-14 20:34 ` [PATCH v3 14/15] target/riscv: csr: " Alistair Francis 2020-12-14 20:34 ` Alistair Francis 2020-12-15 13:27 ` Bin Meng 2020-12-15 13:27 ` Bin Meng 2020-12-14 20:34 ` [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target Alistair Francis 2020-12-14 20:34 ` Alistair Francis
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