* [PATCH 00/18] Increase minimum requirements for x86 platforms
@ 2017-06-20 15:22 Bruce Richardson
2017-06-20 15:22 ` [PATCH 01/18] mk: require SSE4.2 support on all " Bruce Richardson
` (18 more replies)
0 siblings, 19 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:22 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
This patchset sets the minimum instruction set level for x86 platform to
SSE4.2, up from SSE3. This means that all builds will have SSE4.2 support
included, and we can remove special case manipulation of CFLAGS for the
same. Naturally, this does mean that some machines that previously could
run DPDK now can't do so, but hardware with SSE4.2 has been around for
almost a decade now, so this should not be a major problem.
Bruce Richardson (18):
mk: require SSE4.2 support on all x86 platforms
acl: remove checks for SSE4
distributor: remove checks for SSE4
eal: remove unneeded conditionals for SSE headers
hash: remove checks for SSE4
ip_frag: check for x86 rather than SSE4
net: remove check for SSE4
sched: remove check for SSE4
crypto/aesni_mb: remove check for SSE4
crypto/kasumi: remove check for SSE4
crypto/snow3g: remove check for SSE4
crypto/zuc: remove check for SSE4
net/enic: replace check for SSE4 with check for x86
net/i40e: remove checks for SSE4
net/ixgbe: remove fallback code for non-SSE4 systems
examples/ip_pipeline: remove macro check for SSE4
examples/l3fwd: remove checks for SSE4
examples/performance-thread: remove non-SSE4 fallbacks
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 6 +---
drivers/crypto/kasumi/rte_kasumi_pmd.c | 6 +---
drivers/crypto/snow3g/rte_snow3g_pmd.c | 10 +------
drivers/crypto/zuc/rte_zuc_pmd.c | 10 +------
drivers/net/enic/enic_clsf.c | 2 +-
drivers/net/i40e/Makefile | 5 ----
drivers/net/i40e/i40e_rxtx_vec_sse.c | 6 ----
drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 15 ----------
examples/ip_pipeline/pipeline/hash_func.h | 2 +-
examples/l3fwd-power/main.c | 2 +-
examples/l3fwd-vf/main.c | 2 +-
examples/l3fwd/l3fwd_em.c | 6 ++--
examples/l3fwd/l3fwd_lpm.c | 6 ++--
examples/performance-thread/l3fwd-thread/main.c | 25 -----------------
lib/librte_acl/Makefile | 4 ---
lib/librte_distributor/Makefile | 4 ---
lib/librte_distributor/rte_distributor.c | 6 ++--
lib/librte_eal/common/include/arch/x86/rte_vect.h | 16 +----------
lib/librte_hash/rte_cmp_x86.h | 6 ----
lib/librte_hash/rte_cuckoo_hash.h | 2 +-
lib/librte_hash/rte_fbk_hash.h | 2 +-
lib/librte_hash/rte_hash_crc.h | 34 +++++++----------------
lib/librte_ip_frag/ip_frag_internal.c | 10 +++----
lib/librte_net/rte_net_crc.c | 4 +--
lib/librte_sched/rte_sched.c | 2 +-
lib/librte_table/rte_lru.h | 7 +----
mk/machine/default/rte.vars.mk | 2 +-
mk/machine/native/rte.vars.mk | 3 --
mk/toolchain/icc/rte.toolchain-compat.mk | 2 +-
29 files changed, 38 insertions(+), 169 deletions(-)
--
2.9.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 01/18] mk: require SSE4.2 support on all x86 platforms
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
@ 2017-06-20 15:22 ` Bruce Richardson
2017-06-20 15:22 ` [PATCH 02/18] acl: remove checks for SSE4 Bruce Richardson
` (17 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:22 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: Bruce Richardson, dev
Increase the default baseline from "core2" architecture to "corei7". This
means that all builds will have SSE4.2 support included, and we can remove
special case manipulation of CFLAGS for the same. Naturally, this does mean
that some machines that previously could run DPDK now can't do so, but
hardware with SSE4.2 has been around for almost a decade now, so this
should not be a major problem.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
mk/machine/default/rte.vars.mk | 2 +-
mk/machine/native/rte.vars.mk | 3 ---
mk/toolchain/icc/rte.toolchain-compat.mk | 2 +-
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/mk/machine/default/rte.vars.mk b/mk/machine/default/rte.vars.mk
index a6fb842..71a25bc 100644
--- a/mk/machine/default/rte.vars.mk
+++ b/mk/machine/default/rte.vars.mk
@@ -55,4 +55,4 @@
# CPU_LDFLAGS =
# CPU_ASFLAGS =
-MACHINE_CFLAGS += -march=core2
+MACHINE_CFLAGS += -march=corei7
diff --git a/mk/machine/native/rte.vars.mk b/mk/machine/native/rte.vars.mk
index 7f55b54..f7d98d0 100644
--- a/mk/machine/native/rte.vars.mk
+++ b/mk/machine/native/rte.vars.mk
@@ -63,8 +63,5 @@ MACHINE_CFLAGS = -march=native
# so, set the compilation target to be a corei7, minimum target with SSE4.2.
SSE42_SUPPORT=$(shell $(CC) -march=native -dM -E - </dev/null | grep SSE4_2)
ifeq ($(SSE42_SUPPORT),)
- CPU_SSE42_SUPPORT = $(shell grep SSE4\.2 /var/run/dmesg.boot 2>/dev/null)
- ifneq ($(CPU_SSE42_SUPPORT),)
MACHINE_CFLAGS = -march=corei7
- endif
endif
diff --git a/mk/toolchain/icc/rte.toolchain-compat.mk b/mk/toolchain/icc/rte.toolchain-compat.mk
index 88f1ac9..3c25d18 100644
--- a/mk/toolchain/icc/rte.toolchain-compat.mk
+++ b/mk/toolchain/icc/rte.toolchain-compat.mk
@@ -41,7 +41,7 @@
ICC_MAJOR_VERSION = $(shell icc -dumpversion | cut -f1 -d.)
ifeq ($(shell test $(ICC_MAJOR_VERSION) -lt 12 && echo 1), 1)
- MACHINE_CFLAGS = -xSSE3
+ MACHINE_CFLAGS = -xSSE4.2
$(warning You are not using ICC 12.x or higher. This is neither supported, nor tested.)
else
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 02/18] acl: remove checks for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
2017-06-20 15:22 ` [PATCH 01/18] mk: require SSE4.2 support on all " Bruce Richardson
@ 2017-06-20 15:22 ` Bruce Richardson
2017-06-20 15:22 ` [PATCH 03/18] distributor: " Bruce Richardson
` (16 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:22 UTC (permalink / raw)
To: Konstantin Ananyev; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we now longer
need this check.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_acl/Makefile | 4 ----
1 file changed, 4 deletions(-)
diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile
index e2dacd6..ed58898 100644
--- a/lib/librte_acl/Makefile
+++ b/lib/librte_acl/Makefile
@@ -56,10 +56,6 @@ else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c
else
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c
-#check if flag for SSE4.1 is already on, if not set it up manually
- ifeq ($(findstring RTE_MACHINE_CPUFLAG_SSE4_1,$(CFLAGS)),)
- CFLAGS_acl_run_sse.o += -msse4.1
- endif
endif
#
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 03/18] distributor: remove checks for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
2017-06-20 15:22 ` [PATCH 01/18] mk: require SSE4.2 support on all " Bruce Richardson
2017-06-20 15:22 ` [PATCH 02/18] acl: remove checks for SSE4 Bruce Richardson
@ 2017-06-20 15:22 ` Bruce Richardson
2017-06-20 15:22 ` [PATCH 04/18] eal: remove unneeded conditionals for SSE headers Bruce Richardson
` (15 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:22 UTC (permalink / raw)
To: David Hunt; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we now longer
need this check.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_distributor/Makefile | 4 ----
lib/librte_distributor/rte_distributor.c | 6 ++----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/lib/librte_distributor/Makefile b/lib/librte_distributor/Makefile
index 3ffb911..b417ee7 100644
--- a/lib/librte_distributor/Makefile
+++ b/lib/librte_distributor/Makefile
@@ -46,10 +46,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) := rte_distributor_v20.c
SRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += rte_distributor.c
ifeq ($(CONFIG_RTE_ARCH_X86),y)
SRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += rte_distributor_match_sse.c
-# distributor SIMD algo needs SSE4.2 support
-ifeq ($(findstring RTE_MACHINE_CPUFLAG_SSE4_2,$(CFLAGS)),)
-CFLAGS_rte_distributor_match_sse.o += -msse4.2
-endif
else
SRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += rte_distributor_match_generic.c
endif
diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c
index e4dfa7f..cb21458 100644
--- a/lib/librte_distributor/rte_distributor.c
+++ b/lib/librte_distributor/rte_distributor.c
@@ -656,12 +656,10 @@ rte_distributor_create_v1705(const char *name,
d->num_workers = num_workers;
d->alg_type = alg_type;
+ d->dist_match_fn = RTE_DIST_MATCH_SCALAR;
#if defined(RTE_ARCH_X86)
- if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2))
- d->dist_match_fn = RTE_DIST_MATCH_VECTOR;
- else
+ d->dist_match_fn = RTE_DIST_MATCH_VECTOR;
#endif
- d->dist_match_fn = RTE_DIST_MATCH_SCALAR;
/*
* Set up the backog tags so they're pointing at the second cache
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 04/18] eal: remove unneeded conditionals for SSE headers
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (2 preceding siblings ...)
2017-06-20 15:22 ` [PATCH 03/18] distributor: " Bruce Richardson
@ 2017-06-20 15:22 ` Bruce Richardson
2017-07-04 12:23 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 05/18] hash: remove checks for SSE4 Bruce Richardson
` (14 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:22 UTC (permalink / raw)
To: Konstantin Ananyev; +Cc: Bruce Richardson, dev
Our x86 baseline is to have support for SSE4.2, so therefore there is no
point in conditions around the inclusion of SSE1 - SSE4 headers.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_eal/common/include/arch/x86/rte_vect.h | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/x86/rte_vect.h b/lib/librte_eal/common/include/arch/x86/rte_vect.h
index 1b4b85d..03fc991 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_vect.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_vect.h
@@ -45,21 +45,7 @@
#if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))
-#ifdef __SSE__
-#include <xmmintrin.h>
-#endif
-
-#ifdef __SSE2__
-#include <emmintrin.h>
-#endif
-
-#ifdef __SSE3__
-#include <tmmintrin.h>
-#endif
-
-#if defined(__SSE4_2__) || defined(__SSE4_1__)
-#include <smmintrin.h>
-#endif
+#include <smmintrin.h> /* SSE4 */
#if defined(__AVX__)
#include <immintrin.h>
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 05/18] hash: remove checks for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (3 preceding siblings ...)
2017-06-20 15:22 ` [PATCH 04/18] eal: remove unneeded conditionals for SSE headers Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-07-04 12:22 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 06/18] ip_frag: check for x86 rather than SSE4 Bruce Richardson
` (13 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Pablo de Lara; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
a fallback case to handle selection of algorithm when SSE4 is unavailable.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_hash/rte_cmp_x86.h | 6 ------
lib/librte_hash/rte_cuckoo_hash.h | 2 +-
lib/librte_hash/rte_fbk_hash.h | 2 +-
lib/librte_hash/rte_hash_crc.h | 34 ++++++++++------------------------
4 files changed, 12 insertions(+), 32 deletions(-)
diff --git a/lib/librte_hash/rte_cmp_x86.h b/lib/librte_hash/rte_cmp_x86.h
index e8c484d..704c2de 100644
--- a/lib/librte_hash/rte_cmp_x86.h
+++ b/lib/librte_hash/rte_cmp_x86.h
@@ -37,15 +37,9 @@ rte_hash_k16_cmp_eq(const void *key1, const void *key2, size_t key_len __rte_unu
{
const __m128i k1 = _mm_loadu_si128((const __m128i *) key1);
const __m128i k2 = _mm_loadu_si128((const __m128i *) key2);
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_1
const __m128i x = _mm_xor_si128(k1, k2);
return !_mm_test_all_zeros(x, x);
-#else
- const __m128i x = _mm_cmpeq_epi32(k1, k2);
-
- return _mm_movemask_epi8(x) != 0xffff;
-#endif
}
static int
diff --git a/lib/librte_hash/rte_cuckoo_hash.h b/lib/librte_hash/rte_cuckoo_hash.h
index 1b8ffed..f75392d 100644
--- a/lib/librte_hash/rte_cuckoo_hash.h
+++ b/lib/librte_hash/rte_cuckoo_hash.h
@@ -58,7 +58,7 @@
#endif
/* Hash function used if none is specified */
-#if defined(RTE_MACHINE_CPUFLAG_SSE4_2) || defined(RTE_MACHINE_CPUFLAG_CRC32)
+#if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_CRC32)
#include <rte_hash_crc.h>
#define DEFAULT_HASH_FUNC rte_hash_crc
#else
diff --git a/lib/librte_hash/rte_fbk_hash.h b/lib/librte_hash/rte_fbk_hash.h
index bd46048..c39c097 100644
--- a/lib/librte_hash/rte_fbk_hash.h
+++ b/lib/librte_hash/rte_fbk_hash.h
@@ -55,7 +55,7 @@ extern "C" {
#include <string.h>
#ifndef RTE_FBK_HASH_FUNC_DEFAULT
-#if defined(RTE_MACHINE_CPUFLAG_SSE4_2) || defined(RTE_MACHINE_CPUFLAG_CRC32)
+#if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_CRC32)
#include <rte_hash_crc.h>
/** Default four-byte key hash function if none is specified. */
#define RTE_FBK_HASH_FUNC_DEFAULT rte_hash_crc_4byte
diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index b8a0cbe..3fd00e9 100644
--- a/lib/librte_hash/rte_hash_crc.h
+++ b/lib/librte_hash/rte_hash_crc.h
@@ -387,7 +387,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
return crc;
}
-#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
+#if defined(RTE_ARCH_X86)
static inline uint32_t
crc32c_sse42_u8(uint8_t data, uint32_t init_val)
{
@@ -471,26 +471,12 @@ static uint8_t crc32_alg = CRC32_SW;
static inline void
rte_hash_crc_set_alg(uint8_t alg)
{
- switch (alg) {
-#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
- case CRC32_SSE42_x64:
- if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
- alg = CRC32_SSE42;
-#if __GNUC__ >= 7 && !defined(RTE_TOOLCHAIN_ICC)
- __attribute__ ((fallthrough));
+#if defined(RTE_ARCH_X86)
+ if (alg == CRC32_SSE42_x64 &&
+ !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
+ alg = CRC32_SSE42;
#endif
- case CRC32_SSE42:
- if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2))
- alg = CRC32_SW;
-#if __GNUC__ >= 7 && !defined(RTE_TOOLCHAIN_ICC)
- __attribute__ ((fallthrough));
-#endif
-#endif
- case CRC32_SW:
- crc32_alg = alg;
- default:
- break;
- }
+ crc32_alg = alg;
}
/* Setting the best available algorithm */
@@ -515,7 +501,7 @@ rte_hash_crc_init_alg(void)
static inline uint32_t
rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
+#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u8(data, init_val);
#endif
@@ -538,7 +524,7 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
+#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u16(data, init_val);
#endif
@@ -561,7 +547,7 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
{
-#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
+#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u32(data, init_val);
#endif
@@ -589,7 +575,7 @@ rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
return crc32c_sse42_u64(data, init_val);
#endif
-#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
+#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u64_mimic(data, init_val);
#endif
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 06/18] ip_frag: check for x86 rather than SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (4 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 05/18] hash: remove checks for SSE4 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 07/18] net: remove check for SSE4 Bruce Richardson
` (12 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Konstantin Ananyev; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_ip_frag/ip_frag_internal.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/lib/librte_ip_frag/ip_frag_internal.c b/lib/librte_ip_frag/ip_frag_internal.c
index b679ff4..09b755c 100644
--- a/lib/librte_ip_frag/ip_frag_internal.c
+++ b/lib/librte_ip_frag/ip_frag_internal.c
@@ -34,9 +34,7 @@
#include <stddef.h>
#include <rte_jhash.h>
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
#include <rte_hash_crc.h>
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
#include "ip_frag_common.h"
@@ -94,14 +92,14 @@ ipv4_frag_hash(const struct ip_frag_key *key, uint32_t *v1, uint32_t *v2)
p = (const uint32_t *)&key->src_dst;
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
+#ifdef RTE_ARCH_X86
v = rte_hash_crc_4byte(p[0], PRIME_VALUE);
v = rte_hash_crc_4byte(p[1], v);
v = rte_hash_crc_4byte(key->id, v);
#else
v = rte_jhash_3words(p[0], p[1], key->id, PRIME_VALUE);
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
+#endif /* RTE_ARCH_X86 */
*v1 = v;
*v2 = (v << 7) + (v >> 14);
@@ -115,7 +113,7 @@ ipv6_frag_hash(const struct ip_frag_key *key, uint32_t *v1, uint32_t *v2)
p = (const uint32_t *) &key->src_dst;
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
+#ifdef RTE_ARCH_X86
v = rte_hash_crc_4byte(p[0], PRIME_VALUE);
v = rte_hash_crc_4byte(p[1], v);
v = rte_hash_crc_4byte(p[2], v);
@@ -130,7 +128,7 @@ ipv6_frag_hash(const struct ip_frag_key *key, uint32_t *v1, uint32_t *v2)
v = rte_jhash_3words(p[0], p[1], p[2], PRIME_VALUE);
v = rte_jhash_3words(p[3], p[4], p[5], v);
v = rte_jhash_3words(p[6], p[7], key->id, v);
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
+#endif /* RTE_ARCH_X86 */
*v1 = v;
*v2 = (v << 7) + (v >> 14);
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 07/18] net: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (5 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 06/18] ip_frag: check for x86 rather than SSE4 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-30 9:44 ` Olivier Matz
2017-06-20 15:23 ` [PATCH 08/18] sched: " Bruce Richardson
` (11 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Olivier Matz; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_net/rte_net_crc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c
index 0391c72..a270d6c 100644
--- a/lib/librte_net/rte_net_crc.c
+++ b/lib/librte_net/rte_net_crc.c
@@ -39,9 +39,7 @@
#include <rte_common.h>
#include <rte_net_crc.h>
-#if defined(RTE_ARCH_X86_64) \
- && defined(RTE_MACHINE_CPUFLAG_SSE4_2) \
- && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
+#if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
#define X86_64_SSE42_PCLMULQDQ 1
#endif
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 08/18] sched: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (6 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 07/18] net: remove check for SSE4 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-07-04 12:40 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 09/18] crypto/aesni_mb: " Bruce Richardson
` (10 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Cristian Dumitrescu; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
lib/librte_sched/rte_sched.c | 2 +-
lib/librte_table/rte_lru.h | 7 +------
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c
index 614705d..95c24e3 100644
--- a/lib/librte_sched/rte_sched.c
+++ b/lib/librte_sched/rte_sched.c
@@ -56,7 +56,7 @@
#ifdef RTE_SCHED_VECTOR
#include <rte_vect.h>
-#if defined(__SSE4__)
+#ifdef RTE_ARCH_X86
#define SCHED_VECTOR_SSE4
#endif
diff --git a/lib/librte_table/rte_lru.h b/lib/librte_table/rte_lru.h
index e87e062..1090163 100644
--- a/lib/librte_table/rte_lru.h
+++ b/lib/librte_table/rte_lru.h
@@ -47,18 +47,13 @@ extern "C" {
#endif
#ifndef RTE_TABLE_HASH_LRU_STRATEGY
-#ifdef __SSE4_2__
+#ifdef RTE_ARCH_X86_64
#define RTE_TABLE_HASH_LRU_STRATEGY 2
#else /* if no SSE, use simple scalar version */
#define RTE_TABLE_HASH_LRU_STRATEGY 1
#endif
#endif
-#ifndef RTE_ARCH_X86_64
-#undef RTE_TABLE_HASH_LRU_STRATEGY
-#define RTE_TABLE_HASH_LRU_STRATEGY 1
-#endif
-
#if (RTE_TABLE_HASH_LRU_STRATEGY < 0) || (RTE_TABLE_HASH_LRU_STRATEGY > 3)
#error Invalid value for RTE_TABLE_HASH_LRU_STRATEGY
#endif
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 09/18] crypto/aesni_mb: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (7 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 08/18] sched: " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-23 12:58 ` Declan Doherty
2017-06-20 15:23 ` [PATCH 10/18] crypto/kasumi: " Bruce Richardson
` (9 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Declan Doherty; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 45b25c9..9419dca 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -691,12 +691,8 @@ cryptodev_aesni_mb_create(const char *name,
vector_mode = RTE_AESNI_MB_AVX2;
else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
vector_mode = RTE_AESNI_MB_AVX;
- else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+ else
vector_mode = RTE_AESNI_MB_SSE;
- else {
- MB_LOG_ERR("Vector instructions are not supported by CPU");
- return -EFAULT;
- }
dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct aesni_mb_private), init_params->socket_id);
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 10/18] crypto/kasumi: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (8 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 09/18] crypto/aesni_mb: " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 11/18] crypto/snow3g: " Bruce Richardson
` (8 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Pablo de Lara; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/crypto/kasumi/rte_kasumi_pmd.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/crypto/kasumi/rte_kasumi_pmd.c b/drivers/crypto/kasumi/rte_kasumi_pmd.c
index 9da9e89..ef4e630 100644
--- a/drivers/crypto/kasumi/rte_kasumi_pmd.c
+++ b/drivers/crypto/kasumi/rte_kasumi_pmd.c
@@ -566,12 +566,8 @@ cryptodev_kasumi_create(const char *name,
/* Check CPU for supported vector instruction set */
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
cpu_flags |= RTE_CRYPTODEV_FF_CPU_AVX;
- else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+ else
cpu_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
- else {
- KASUMI_LOG_ERR("Vector instructions are not supported by CPU");
- return -EFAULT;
- }
dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct kasumi_private), init_params->socket_id);
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 11/18] crypto/snow3g: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (9 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 10/18] crypto/kasumi: " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 12/18] crypto/zuc: " Bruce Richardson
` (7 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Pablo de Lara; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/crypto/snow3g/rte_snow3g_pmd.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/crypto/snow3g/rte_snow3g_pmd.c b/drivers/crypto/snow3g/rte_snow3g_pmd.c
index 960956c..1e0bf47 100644
--- a/drivers/crypto/snow3g/rte_snow3g_pmd.c
+++ b/drivers/crypto/snow3g/rte_snow3g_pmd.c
@@ -548,20 +548,12 @@ cryptodev_snow3g_create(const char *name,
{
struct rte_cryptodev *dev;
struct snow3g_private *internals;
- uint64_t cpu_flags = 0;
+ uint64_t cpu_flags = RTE_CRYPTODEV_FF_CPU_SSE;
if (init_params->name[0] == '\0')
snprintf(init_params->name, sizeof(init_params->name),
"%s", name);
- /* Check CPU for supported vector instruction set */
- if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
- cpu_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
- else {
- SNOW3G_LOG_ERR("Vector instructions are not supported by CPU");
- return -EFAULT;
- }
-
dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct snow3g_private), init_params->socket_id);
if (dev == NULL) {
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 12/18] crypto/zuc: remove check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (10 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 11/18] crypto/snow3g: " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 13/18] net/enic: replace check for SSE4 with check for x86 Bruce Richardson
` (6 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Pablo de Lara; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/crypto/zuc/rte_zuc_pmd.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/crypto/zuc/rte_zuc_pmd.c b/drivers/crypto/zuc/rte_zuc_pmd.c
index 1020544..30f289e 100644
--- a/drivers/crypto/zuc/rte_zuc_pmd.c
+++ b/drivers/crypto/zuc/rte_zuc_pmd.c
@@ -448,20 +448,12 @@ cryptodev_zuc_create(const char *name,
{
struct rte_cryptodev *dev;
struct zuc_private *internals;
- uint64_t cpu_flags = 0;
+ uint64_t cpu_flags = RTE_CRYPTODEV_FF_CPU_SSE;
if (init_params->name[0] == '\0')
snprintf(init_params->name, sizeof(init_params->name),
"%s", name);
- /* Check CPU for supported vector instruction set */
- if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
- cpu_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
- else {
- ZUC_LOG_ERR("Vector instructions are not supported by CPU");
- return -EFAULT;
- }
-
dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct zuc_private), init_params->socket_id);
if (dev == NULL) {
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 13/18] net/enic: replace check for SSE4 with check for x86
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (11 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 12/18] crypto/zuc: " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 14/18] net/i40e: remove checks for SSE4 Bruce Richardson
` (5 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: John Daley, Nelson Escobar; +Cc: Bruce Richardson, dev
Since SSE4 is now minimum requirement for x86 platforms we can replace the
check for SSE4 with a check for x86
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/enic/enic_clsf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/enic/enic_clsf.c b/drivers/net/enic/enic_clsf.c
index 9e94afd..9b46142 100644
--- a/drivers/net/enic/enic_clsf.c
+++ b/drivers/net/enic/enic_clsf.c
@@ -57,7 +57,7 @@
#include "vnic_intr.h"
#include "vnic_nic.h"
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
+#ifdef RTE_ARCH_X86
#include <rte_hash_crc.h>
#define DEFAULT_HASH_FUNC rte_hash_crc
#else
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 14/18] net/i40e: remove checks for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (12 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 13/18] net/enic: replace check for SSE4 with check for x86 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 15/18] net/ixgbe: remove fallback code for non-SSE4 systems Bruce Richardson
` (4 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Helin Zhang, Jingjing Wu; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we no longer
need these checks.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/i40e/Makefile | 5 -----
drivers/net/i40e/i40e_rxtx_vec_sse.c | 6 ------
2 files changed, 11 deletions(-)
diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile
index 56f210d..f1b0129 100644
--- a/drivers/net/i40e/Makefile
+++ b/drivers/net/i40e/Makefile
@@ -110,11 +110,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_fdir.c
SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += rte_pmd_i40e.c
-# vector PMD driver needs SSE4.1 support
-ifeq ($(findstring RTE_MACHINE_CPUFLAG_SSE4_1,$(CFLAGS)),)
-CFLAGS_i40e_rxtx_vec_sse.o += -msse4.1
-endif
-
# install this header file
SYMLINK-$(CONFIG_RTE_LIBRTE_I40E_PMD)-include := rte_pmd_i40e.h
diff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c b/drivers/net/i40e/i40e_rxtx_vec_sse.c
index 2dc53a9..779f14e 100644
--- a/drivers/net/i40e/i40e_rxtx_vec_sse.c
+++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c
@@ -651,11 +651,5 @@ i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
int __attribute__((cold))
i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
{
-#ifndef RTE_LIBRTE_IEEE1588
- /* need SSE4.1 support */
- if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
- return -1;
-#endif
-
return i40e_rx_vec_dev_conf_condition_check_default(dev);
}
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 15/18] net/ixgbe: remove fallback code for non-SSE4 systems
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (13 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 14/18] net/i40e: remove checks for SSE4 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 16/18] examples/ip_pipeline: remove macro check for SSE4 Bruce Richardson
` (3 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Wenzhuo Lu, Konstantin Ananyev; +Cc: Bruce Richardson, dev
Since SSE4 is now part of minimum requirements for DPDK on x86, we no
longer need this fallback code.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
index 203f092..d209bb2 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
@@ -216,26 +216,11 @@ desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags,
* appropriate flags means that we have to do a shift and blend for
* each mbuf before we do the write.
*/
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
-
rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10);
rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10);
rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10);
rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10);
-#else
- rearm0 = _mm_slli_si128(vtag1, 14);
- rearm1 = _mm_slli_si128(vtag1, 12);
- rearm2 = _mm_slli_si128(vtag1, 10);
- rearm3 = _mm_slli_si128(vtag1, 8);
-
- rearm0 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm0, 48));
- rearm1 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm1, 48));
- rearm2 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm2, 48));
- rearm3 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm3, 48));
-
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
-
/* write the rearm data and the olflags in one write */
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
offsetof(struct rte_mbuf, rearm_data) + 8);
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 16/18] examples/ip_pipeline: remove macro check for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (14 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 15/18] net/ixgbe: remove fallback code for non-SSE4 systems Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 17/18] examples/l3fwd: remove checks " Bruce Richardson
` (2 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: Cristian Dumitrescu; +Cc: Bruce Richardson, dev
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
examples/ip_pipeline/pipeline/hash_func.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/ip_pipeline/pipeline/hash_func.h b/examples/ip_pipeline/pipeline/hash_func.h
index 9db7173..b112369 100644
--- a/examples/ip_pipeline/pipeline/hash_func.h
+++ b/examples/ip_pipeline/pipeline/hash_func.h
@@ -152,7 +152,7 @@ hash_xor_key64(void *key, __rte_unused uint32_t key_size, uint64_t seed)
return (xor0 >> 32) ^ xor0;
}
-#if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_SSE4_2)
+#if defined(RTE_ARCH_X86_64)
#include <x86intrin.h>
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 17/18] examples/l3fwd: remove checks for SSE4
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (15 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 16/18] examples/ip_pipeline: remove macro check for SSE4 Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-20 15:23 ` [PATCH 18/18] examples/performance-thread: remove non-SSE4 fallbacks Bruce Richardson
2017-06-30 13:23 ` [PATCH 00/18] Increase minimum requirements for x86 platforms Ananyev, Konstantin
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
to check for its presence any more.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
examples/l3fwd-power/main.c | 2 +-
examples/l3fwd-vf/main.c | 2 +-
examples/l3fwd/l3fwd_em.c | 6 +++---
examples/l3fwd/l3fwd_lpm.c | 6 +++---
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c
index 9d57fde..52eb835 100644
--- a/examples/l3fwd-power/main.c
+++ b/examples/l3fwd-power/main.c
@@ -245,7 +245,7 @@ static struct rte_mempool * pktmbuf_pool[NB_SOCKETS];
#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
+#ifdef RTE_ARCH_X86
#include <rte_hash_crc.h>
#define DEFAULT_HASH_FUNC rte_hash_crc
#else
diff --git a/examples/l3fwd-vf/main.c b/examples/l3fwd-vf/main.c
index 797f722..5ac30b7 100644
--- a/examples/l3fwd-vf/main.c
+++ b/examples/l3fwd-vf/main.c
@@ -215,7 +215,7 @@ static struct rte_mempool * pktmbuf_pool[NB_SOCKETS];
#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
+#ifdef RTE_ARCH_X86
#include <rte_hash_crc.h>
#define DEFAULT_HASH_FUNC rte_hash_crc
#else
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 9cc4460..67e2ab1 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -57,7 +57,7 @@
#include "l3fwd.h"
-#if defined(RTE_MACHINE_CPUFLAG_SSE4_2) || defined(RTE_MACHINE_CPUFLAG_CRC32)
+#if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_CRC32)
#define EM_HASH_CRC 1
#endif
@@ -328,7 +328,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint8_t portid, void *lookup_struct)
return (uint8_t)((ret < 0) ? portid : ipv6_l3fwd_out_if[ret]);
}
-#if defined(__SSE4_1__)
+#if defined(RTE_ARCH_X86)
#if defined(NO_HASH_MULTI_LOOKUP)
#include "l3fwd_em_sse.h"
#else
@@ -709,7 +709,7 @@ em_main_loop(__attribute__((unused)) void *dummy)
if (nb_rx == 0)
continue;
-#if defined(__SSE4_1__)
+#if defined(RTE_ARCH_X86)
l3fwd_em_send_packets(nb_rx, pkts_burst,
portid, qconf);
#else
diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c
index f621269..7f30d65 100644
--- a/examples/l3fwd/l3fwd_lpm.c
+++ b/examples/l3fwd/l3fwd_lpm.c
@@ -104,7 +104,7 @@ static struct ipv6_l3fwd_lpm_route ipv6_l3fwd_lpm_route_array[] = {
struct rte_lpm *ipv4_l3fwd_lpm_lookup_struct[NB_SOCKETS];
struct rte_lpm6 *ipv6_l3fwd_lpm_lookup_struct[NB_SOCKETS];
-#if defined(__SSE4_1__)
+#if defined(RTE_ARCH_X86)
#include "l3fwd_lpm_sse.h"
#else
#include "l3fwd_lpm.h"
@@ -178,13 +178,13 @@ lpm_main_loop(__attribute__((unused)) void *dummy)
if (nb_rx == 0)
continue;
-#if defined(__SSE4_1__)
+#if defined(RTE_ARCH_X86)
l3fwd_lpm_send_packets(nb_rx, pkts_burst,
portid, qconf);
#else
l3fwd_lpm_no_opt_send_packets(nb_rx, pkts_burst,
portid, qconf);
-#endif /* __SSE_4_1__ */
+#endif /* X86 */
}
}
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 18/18] examples/performance-thread: remove non-SSE4 fallbacks
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (16 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 17/18] examples/l3fwd: remove checks " Bruce Richardson
@ 2017-06-20 15:23 ` Bruce Richardson
2017-06-30 13:23 ` [PATCH 00/18] Increase minimum requirements for x86 platforms Ananyev, Konstantin
18 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-06-20 15:23 UTC (permalink / raw)
To: John McNamara; +Cc: Bruce Richardson, dev
Since this example is for x86_64 platforms only, and since SSE4 is now a
mandatory requirement, we can remove the ifdefs checking for that
instruction set level, and the fallbacks if it is not present.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
examples/performance-thread/l3fwd-thread/main.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index 8237ac6..e1db857 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -157,11 +157,7 @@ cb_parse_ptype(__rte_unused uint8_t port, __rte_unused uint16_t queue,
* When set to one, optimized forwarding path is enabled.
* Note that LPM optimisation path uses SSE4.1 instructions.
*/
-#if ((APP_LOOKUP_METHOD == APP_LOOKUP_LPM) && !defined(__SSE4_1__))
-#define ENABLE_MULTI_BUFFER_OPTIMIZE 0
-#else
#define ENABLE_MULTI_BUFFER_OPTIMIZE 1
-#endif
#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
#include <rte_hash.h>
@@ -362,13 +358,8 @@ static struct rte_mempool *pktmbuf_pool[NB_SOCKETS];
#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
#include <rte_hash_crc.h>
#define DEFAULT_HASH_FUNC rte_hash_crc
-#else
-#include <rte_jhash.h>
-#define DEFAULT_HASH_FUNC rte_jhash
-#endif
struct ipv4_5tuple {
uint32_t ip_dst;
@@ -485,17 +476,10 @@ ipv4_hash_crc(const void *data, __rte_unused uint32_t data_len,
t = k->proto;
p = (const uint32_t *)&k->port_src;
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
init_val = rte_hash_crc_4byte(t, init_val);
init_val = rte_hash_crc_4byte(k->ip_src, init_val);
init_val = rte_hash_crc_4byte(k->ip_dst, init_val);
init_val = rte_hash_crc_4byte(*p, init_val);
-#else /* RTE_MACHINE_CPUFLAG_SSE4_2 */
- init_val = rte_jhash_1word(t, init_val);
- init_val = rte_jhash_1word(k->ip_src, init_val);
- init_val = rte_jhash_1word(k->ip_dst, init_val);
- init_val = rte_jhash_1word(*p, init_val);
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
return init_val;
}
@@ -506,16 +490,13 @@ ipv6_hash_crc(const void *data, __rte_unused uint32_t data_len,
const union ipv6_5tuple_host *k;
uint32_t t;
const uint32_t *p;
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
const uint32_t *ip_src0, *ip_src1, *ip_src2, *ip_src3;
const uint32_t *ip_dst0, *ip_dst1, *ip_dst2, *ip_dst3;
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
k = data;
t = k->proto;
p = (const uint32_t *)&k->port_src;
-#ifdef RTE_MACHINE_CPUFLAG_SSE4_2
ip_src0 = (const uint32_t *) k->ip_src;
ip_src1 = (const uint32_t *)(k->ip_src + 4);
ip_src2 = (const uint32_t *)(k->ip_src + 8);
@@ -534,12 +515,6 @@ ipv6_hash_crc(const void *data, __rte_unused uint32_t data_len,
init_val = rte_hash_crc_4byte(*ip_dst2, init_val);
init_val = rte_hash_crc_4byte(*ip_dst3, init_val);
init_val = rte_hash_crc_4byte(*p, init_val);
-#else /* RTE_MACHINE_CPUFLAG_SSE4_2 */
- init_val = rte_jhash_1word(t, init_val);
- init_val = rte_jhash(k->ip_src, sizeof(uint8_t) * IPV6_ADDR_LEN, init_val);
- init_val = rte_jhash(k->ip_dst, sizeof(uint8_t) * IPV6_ADDR_LEN, init_val);
- init_val = rte_jhash_1word(*p, init_val);
-#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
return init_val;
}
--
2.9.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 09/18] crypto/aesni_mb: remove check for SSE4
2017-06-20 15:23 ` [PATCH 09/18] crypto/aesni_mb: " Bruce Richardson
@ 2017-06-23 12:58 ` Declan Doherty
0 siblings, 0 replies; 27+ messages in thread
From: Declan Doherty @ 2017-06-23 12:58 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev
On 20/06/2017 4:23 PM, Bruce Richardson wrote:
> Since SSE4 is now part of the minimum requirements for DPDK, we don't need
> to check for its presence any more.
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
...
>
Acked-by: Declan Doherty <declan.doherty@intel.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 07/18] net: remove check for SSE4
2017-06-20 15:23 ` [PATCH 07/18] net: remove check for SSE4 Bruce Richardson
@ 2017-06-30 9:44 ` Olivier Matz
0 siblings, 0 replies; 27+ messages in thread
From: Olivier Matz @ 2017-06-30 9:44 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev
On Tue, 20 Jun 2017 16:23:02 +0100, Bruce Richardson <bruce.richardson@intel.com> wrote:
> Since SSE4 is now part of the minimum requirements for DPDK, we don't need
> to check for its presence any more.
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/18] Increase minimum requirements for x86 platforms
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
` (17 preceding siblings ...)
2017-06-20 15:23 ` [PATCH 18/18] examples/performance-thread: remove non-SSE4 fallbacks Bruce Richardson
@ 2017-06-30 13:23 ` Ananyev, Konstantin
2017-07-04 12:42 ` Thomas Monjalon
18 siblings, 1 reply; 27+ messages in thread
From: Ananyev, Konstantin @ 2017-06-30 13:23 UTC (permalink / raw)
To: Richardson, Bruce, dev; +Cc: Richardson, Bruce
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bruce Richardson
> Sent: Tuesday, June 20, 2017 4:23 PM
> To: dev@dpdk.org
> Cc: Richardson, Bruce <bruce.richardson@intel.com>
> Subject: [dpdk-dev] [PATCH 00/18] Increase minimum requirements for x86 platforms
>
> This patchset sets the minimum instruction set level for x86 platform to
> SSE4.2, up from SSE3. This means that all builds will have SSE4.2 support
> included, and we can remove special case manipulation of CFLAGS for the
> same. Naturally, this does mean that some machines that previously could
> run DPDK now can't do so, but hardware with SSE4.2 has been around for
> almost a decade now, so this should not be a major problem.
>
>
> Bruce Richardson (18):
> mk: require SSE4.2 support on all x86 platforms
> acl: remove checks for SSE4
> distributor: remove checks for SSE4
> eal: remove unneeded conditionals for SSE headers
> hash: remove checks for SSE4
> ip_frag: check for x86 rather than SSE4
> net: remove check for SSE4
> sched: remove check for SSE4
> crypto/aesni_mb: remove check for SSE4
> crypto/kasumi: remove check for SSE4
> crypto/snow3g: remove check for SSE4
> crypto/zuc: remove check for SSE4
> net/enic: replace check for SSE4 with check for x86
> net/i40e: remove checks for SSE4
> net/ixgbe: remove fallback code for non-SSE4 systems
> examples/ip_pipeline: remove macro check for SSE4
> examples/l3fwd: remove checks for SSE4
> examples/performance-thread: remove non-SSE4 fallbacks
>
> drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 6 +---
> drivers/crypto/kasumi/rte_kasumi_pmd.c | 6 +---
> drivers/crypto/snow3g/rte_snow3g_pmd.c | 10 +------
> drivers/crypto/zuc/rte_zuc_pmd.c | 10 +------
> drivers/net/enic/enic_clsf.c | 2 +-
> drivers/net/i40e/Makefile | 5 ----
> drivers/net/i40e/i40e_rxtx_vec_sse.c | 6 ----
> drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 15 ----------
> examples/ip_pipeline/pipeline/hash_func.h | 2 +-
> examples/l3fwd-power/main.c | 2 +-
> examples/l3fwd-vf/main.c | 2 +-
> examples/l3fwd/l3fwd_em.c | 6 ++--
> examples/l3fwd/l3fwd_lpm.c | 6 ++--
> examples/performance-thread/l3fwd-thread/main.c | 25 -----------------
> lib/librte_acl/Makefile | 4 ---
> lib/librte_distributor/Makefile | 4 ---
> lib/librte_distributor/rte_distributor.c | 6 ++--
> lib/librte_eal/common/include/arch/x86/rte_vect.h | 16 +----------
> lib/librte_hash/rte_cmp_x86.h | 6 ----
> lib/librte_hash/rte_cuckoo_hash.h | 2 +-
> lib/librte_hash/rte_fbk_hash.h | 2 +-
> lib/librte_hash/rte_hash_crc.h | 34 +++++++----------------
> lib/librte_ip_frag/ip_frag_internal.c | 10 +++----
> lib/librte_net/rte_net_crc.c | 4 +--
> lib/librte_sched/rte_sched.c | 2 +-
> lib/librte_table/rte_lru.h | 7 +----
> mk/machine/default/rte.vars.mk | 2 +-
> mk/machine/native/rte.vars.mk | 3 --
> mk/toolchain/icc/rte.toolchain-compat.mk | 2 +-
> 29 files changed, 38 insertions(+), 169 deletions(-)
>
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> 2.9.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 05/18] hash: remove checks for SSE4
2017-06-20 15:23 ` [PATCH 05/18] hash: remove checks for SSE4 Bruce Richardson
@ 2017-07-04 12:22 ` Thomas Monjalon
0 siblings, 0 replies; 27+ messages in thread
From: Thomas Monjalon @ 2017-07-04 12:22 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, Pablo de Lara
20/06/2017 17:23, Bruce Richardson:
> Since SSE4 is now part of the minimum requirements for DPDK, we don't need
> a fallback case to handle selection of algorithm when SSE4 is unavailable.
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
> lib/librte_hash/rte_cmp_x86.h | 6 ------
> lib/librte_hash/rte_cuckoo_hash.h | 2 +-
> lib/librte_hash/rte_fbk_hash.h | 2 +-
> lib/librte_hash/rte_hash_crc.h | 34 ++++++++++------------------------
> 4 files changed, 12 insertions(+), 32 deletions(-)
You forgot thash, I am adding it:
--- a/lib/librte_hash/rte_thash.h
+++ b/lib/librte_hash/rte_thash.h
@@ -56,11 +56,11 @@ extern "C" {
#include <rte_ip.h>
#include <rte_common.h>
-#if defined(__SSE3__) || defined(RTE_MACHINE_CPUFLAG_NEON)
+#if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
#include <rte_vect.h>
#endif
-#ifdef __SSE3__
+#ifdef RTE_ARCH_X86
/* Byte swap mask used for converting IPv6 address
* 4-byte chunks to CPU byte order
*/
@@ -134,7 +134,7 @@ struct rte_ipv6_tuple {
union rte_thash_tuple {
struct rte_ipv4_tuple v4;
struct rte_ipv6_tuple v6;
-#ifdef __SSE3__
+#ifdef RTE_ARCH_X86
} __attribute__((aligned(XMM_SIZE)));
#else
};
@@ -169,7 +169,7 @@ rte_convert_rss_key(const uint32_t *orig, uint32_t *targ, int len)
static inline void
rte_thash_load_v6_addrs(const struct ipv6_hdr *orig, union rte_thash_tuple *targ)
{
-#ifdef __SSE3__
+#ifdef RTE_ARCH_X86
__m128i ipv6 = _mm_loadu_si128((const __m128i *)orig->src_addr);
*(__m128i *)targ->v6.src_addr =
_mm_shuffle_epi8(ipv6, rte_thash_ipv6_bswap_mask);
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 04/18] eal: remove unneeded conditionals for SSE headers
2017-06-20 15:22 ` [PATCH 04/18] eal: remove unneeded conditionals for SSE headers Bruce Richardson
@ 2017-07-04 12:23 ` Thomas Monjalon
0 siblings, 0 replies; 27+ messages in thread
From: Thomas Monjalon @ 2017-07-04 12:23 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, Konstantin Ananyev
20/06/2017 17:22, Bruce Richardson:
> Our x86 baseline is to have support for SSE4.2, so therefore there is no
> point in conditions around the inclusion of SSE1 - SSE4 headers.
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
> lib/librte_eal/common/include/arch/x86/rte_vect.h | 16 +---------------
> 1 file changed, 1 insertion(+), 15 deletions(-)
I'm adding rte_pause:
--- a/lib/librte_eal/common/include/arch/x86/rte_pause.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_pause.h
@@ -40,17 +40,11 @@ extern "C" {
#include "generic/rte_pause.h"
-#ifdef __SSE2__
#include <emmintrin.h>
static inline void rte_pause(void)
{
_mm_pause();
}
-#else
-static inline void rte_pause(void)
-{
-}
-#endif
#ifdef __cplusplus
}
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 08/18] sched: remove check for SSE4
2017-06-20 15:23 ` [PATCH 08/18] sched: " Bruce Richardson
@ 2017-07-04 12:40 ` Thomas Monjalon
0 siblings, 0 replies; 27+ messages in thread
From: Thomas Monjalon @ 2017-07-04 12:40 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, Cristian Dumitrescu
20/06/2017 17:23, Bruce Richardson:
> Since SSE4 is now part of the minimum requirements for DPDK, we don't need
> to check for its presence any more.
>
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
> lib/librte_sched/rte_sched.c | 2 +-
> lib/librte_table/rte_lru.h | 7 +------
> 2 files changed, 2 insertions(+), 7 deletions(-)
You have squashed sched and table together.
Resurrecting commit for librte_table:
table: remove check for SSE4
Since SSE4 is now part of the minimum requirements for DPDK, we don't need
the scalar version on x86.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/18] Increase minimum requirements for x86 platforms
2017-06-30 13:23 ` [PATCH 00/18] Increase minimum requirements for x86 platforms Ananyev, Konstantin
@ 2017-07-04 12:42 ` Thomas Monjalon
2017-07-21 15:50 ` Bruce Richardson
0 siblings, 1 reply; 27+ messages in thread
From: Thomas Monjalon @ 2017-07-04 12:42 UTC (permalink / raw)
To: Richardson, Bruce; +Cc: dev, Ananyev, Konstantin
> > Bruce Richardson (18):
> > mk: require SSE4.2 support on all x86 platforms
> > acl: remove checks for SSE4
> > distributor: remove checks for SSE4
> > eal: remove unneeded conditionals for SSE headers
> > hash: remove checks for SSE4
> > ip_frag: check for x86 rather than SSE4
> > net: remove check for SSE4
> > sched: remove check for SSE4
> > crypto/aesni_mb: remove check for SSE4
> > crypto/kasumi: remove check for SSE4
> > crypto/snow3g: remove check for SSE4
> > crypto/zuc: remove check for SSE4
> > net/enic: replace check for SSE4 with check for x86
> > net/i40e: remove checks for SSE4
> > net/ixgbe: remove fallback code for non-SSE4 systems
> > examples/ip_pipeline: remove macro check for SSE4
> > examples/l3fwd: remove checks for SSE4
> > examples/performance-thread: remove non-SSE4 fallbacks
>
> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Applied and rebased with additions (in this thread), thanks.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/18] Increase minimum requirements for x86 platforms
2017-07-04 12:42 ` Thomas Monjalon
@ 2017-07-21 15:50 ` Bruce Richardson
0 siblings, 0 replies; 27+ messages in thread
From: Bruce Richardson @ 2017-07-21 15:50 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev, Ananyev, Konstantin
On Tue, Jul 04, 2017 at 02:42:24PM +0200, Thomas Monjalon wrote:
> > > Bruce Richardson (18):
> > > mk: require SSE4.2 support on all x86 platforms
> > > acl: remove checks for SSE4
> > > distributor: remove checks for SSE4
> > > eal: remove unneeded conditionals for SSE headers
> > > hash: remove checks for SSE4
> > > ip_frag: check for x86 rather than SSE4
> > > net: remove check for SSE4
> > > sched: remove check for SSE4
> > > crypto/aesni_mb: remove check for SSE4
> > > crypto/kasumi: remove check for SSE4
> > > crypto/snow3g: remove check for SSE4
> > > crypto/zuc: remove check for SSE4
> > > net/enic: replace check for SSE4 with check for x86
> > > net/i40e: remove checks for SSE4
> > > net/ixgbe: remove fallback code for non-SSE4 systems
> > > examples/ip_pipeline: remove macro check for SSE4
> > > examples/l3fwd: remove checks for SSE4
> > > examples/performance-thread: remove non-SSE4 fallbacks
> >
> > Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
>
> Applied and rebased with additions (in this thread), thanks.
Thanks for fixing the couple of things I missed!
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2017-07-21 15:50 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-20 15:22 [PATCH 00/18] Increase minimum requirements for x86 platforms Bruce Richardson
2017-06-20 15:22 ` [PATCH 01/18] mk: require SSE4.2 support on all " Bruce Richardson
2017-06-20 15:22 ` [PATCH 02/18] acl: remove checks for SSE4 Bruce Richardson
2017-06-20 15:22 ` [PATCH 03/18] distributor: " Bruce Richardson
2017-06-20 15:22 ` [PATCH 04/18] eal: remove unneeded conditionals for SSE headers Bruce Richardson
2017-07-04 12:23 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 05/18] hash: remove checks for SSE4 Bruce Richardson
2017-07-04 12:22 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 06/18] ip_frag: check for x86 rather than SSE4 Bruce Richardson
2017-06-20 15:23 ` [PATCH 07/18] net: remove check for SSE4 Bruce Richardson
2017-06-30 9:44 ` Olivier Matz
2017-06-20 15:23 ` [PATCH 08/18] sched: " Bruce Richardson
2017-07-04 12:40 ` Thomas Monjalon
2017-06-20 15:23 ` [PATCH 09/18] crypto/aesni_mb: " Bruce Richardson
2017-06-23 12:58 ` Declan Doherty
2017-06-20 15:23 ` [PATCH 10/18] crypto/kasumi: " Bruce Richardson
2017-06-20 15:23 ` [PATCH 11/18] crypto/snow3g: " Bruce Richardson
2017-06-20 15:23 ` [PATCH 12/18] crypto/zuc: " Bruce Richardson
2017-06-20 15:23 ` [PATCH 13/18] net/enic: replace check for SSE4 with check for x86 Bruce Richardson
2017-06-20 15:23 ` [PATCH 14/18] net/i40e: remove checks for SSE4 Bruce Richardson
2017-06-20 15:23 ` [PATCH 15/18] net/ixgbe: remove fallback code for non-SSE4 systems Bruce Richardson
2017-06-20 15:23 ` [PATCH 16/18] examples/ip_pipeline: remove macro check for SSE4 Bruce Richardson
2017-06-20 15:23 ` [PATCH 17/18] examples/l3fwd: remove checks " Bruce Richardson
2017-06-20 15:23 ` [PATCH 18/18] examples/performance-thread: remove non-SSE4 fallbacks Bruce Richardson
2017-06-30 13:23 ` [PATCH 00/18] Increase minimum requirements for x86 platforms Ananyev, Konstantin
2017-07-04 12:42 ` Thomas Monjalon
2017-07-21 15:50 ` Bruce Richardson
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