From: Fredrik Noring <noring@nocrew.org>
To: "Maciej W. Rozycki" <macro@mips.com>,
"Jürgen Urban" <JuergenUrban@gmx.de>
Cc: linux-mips@linux-mips.org
Subject: [RFC] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache
Date: Sun, 11 Feb 2018 08:46:51 +0100 [thread overview]
Message-ID: <20180211074651.GB2222@localhost.localdomain> (raw)
In-Reply-To: <alpine.DEB.2.00.1801312259410.4191@tp.orcam.me.uk>
Toshiba TX79 manual programming notes:
For all CACHE sub-operations which operate on the instruction cache
the following programming restrictions have to be followed:
1. A sequence of CACHE instructions has to be directly preceded and
followed by a SYNC.P instruction.
2. Each individual FILL sub-operation has to be followed by a SYNC.L
instruction.
For all CACHE sub-operations which operate on the data cache the
following programming restrictions have to be followed:
1. A sequence of CACHE instructions have to be directly preceded and
followed by a SYNC.L instruction.
2. Each of the three WRITEBACK sub-operations have to be
individually followed by a SYNC.L instruction.
For all CACHE sub-operations which operate on the BTAC the following
programming restrictions have to be followed:
1. A sequence of CACHE instructions have to be directly preceded and
followed by a SYNC.P instruction.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
This change has been ported from v2.6 patches.
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 1b69bb602ffd..c1834e2ed92d 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -46,7 +46,7 @@ extern void (*r4k_blast_icache)(void);
#define R5900_LOOP_WAR() do { } while(0)
#endif
-#define cache_op(op,addr) \
+#define cache_op_s(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
@@ -55,6 +55,35 @@ extern void (*r4k_blast_icache)(void);
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifdef CONFIG_CPU_R5900
+#define cache_op_d(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " sync.l \n" \
+ " cache %0, %1 \n" \
+ " sync.l \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+#define cache_op_i(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " sync.p \n" \
+ " cache %0, %1 \n" \
+ " sync.p \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+#else
+#define cache_op_d cache_op_s
+#define cache_op_i cache_op_s
+#define cache_op cache_op_s
+#endif
+#define cache_op_t cache_op_s
#ifdef CONFIG_MIPS_MT
@@ -99,20 +128,20 @@ extern void (*r4k_blast_icache)(void);
static inline void flush_icache_line_indexed(unsigned long addr)
{
__iflush_prologue
- cache_op(Index_Invalidate_I, addr);
+ cache_op_i(Index_Invalidate_I, addr);
__iflush_epilogue
}
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op_d(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
static inline void flush_scache_line_indexed(unsigned long addr)
{
- cache_op(Index_Writeback_Inv_SD, addr);
+ cache_op_s(Index_Writeback_Inv_SD, addr);
}
static inline void flush_icache_line(unsigned long addr)
@@ -120,11 +149,11 @@ static inline void flush_icache_line(unsigned long addr)
__iflush_prologue
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
- cache_op(Hit_Invalidate_I_Loongson2, addr);
+ cache_op_i(Hit_Invalidate_I_Loongson2, addr);
break;
default:
- cache_op(Hit_Invalidate_I, addr);
+ cache_op_i(Hit_Invalidate_I, addr);
break;
}
__iflush_epilogue
@@ -133,28 +162,28 @@ static inline void flush_icache_line(unsigned long addr)
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op_d(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
- cache_op(Hit_Invalidate_D, addr);
+ cache_op_d(Hit_Invalidate_D, addr);
__dflush_epilogue
}
static inline void invalidate_scache_line(unsigned long addr)
{
- cache_op(Hit_Invalidate_SD, addr);
+ cache_op_s(Hit_Invalidate_SD, addr);
}
static inline void flush_scache_line(unsigned long addr)
{
- cache_op(Hit_Writeback_Inv_SD, addr);
+ cache_op_s(Hit_Writeback_Inv_SD, addr);
}
-#define protected_cache_op(op,addr) \
+#define protected_cache_op_s(op,addr) \
({ \
int __err = 0; \
__asm__ __volatile__( \
@@ -176,6 +205,49 @@ static inline void flush_scache_line(unsigned long addr)
__err; \
})
+#ifdef CONFIG_CPU_R5900
+#define protected_cache_op_d(op,addr) \
+({ \
+ int __err = 0; \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3 \n" \
+ " sync.l \n" \
+ "1: cache %0, (%1) \n" \
+ " sync.l \n" \
+ "2: .set pop \n" \
+ " .section __ex_table,\"a\" \n" \
+ " "STR(PTR)" 1b, 2b \n" \
+ " .previous" \
+ : \
+ : "i" (op), "r" (addr)); \
+ __err; \
+})
+
+#define protected_cache_op_i(op,addr) \
+({ \
+ int __err = 0; \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3 \n" \
+ " sync.p \n" \
+ "1: cache %0, (%1) \n" \
+ " sync.p \n" \
+ "2: .set pop \n" \
+ " .section __ex_table,\"a\" \n" \
+ " "STR(PTR)" 1b, 2b \n" \
+ " .previous" \
+ : \
+ : "i" (op), "r" (addr)); \
+ __err; \
+})
+#else
+#define protected_cache_op_i protected_cache_op_s
+#define protected_cache_op_d protected_cache_op_s
+#define protected_cache_op protected_cache_op_s
+#endif
#define protected_cachee_op(op,addr) \
({ \
@@ -207,13 +279,13 @@ static inline int protected_flush_icache_line(unsigned long addr)
{
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
- return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+ return protected_cache_op_i(Hit_Invalidate_I_Loongson2, addr);
default:
#ifdef CONFIG_EVA
- return protected_cachee_op(Hit_Invalidate_I, addr);
+ return protected_cachee_op_i(Hit_Invalidate_I, addr);
#else
- return protected_cache_op(Hit_Invalidate_I, addr);
+ return protected_cache_op_i(Hit_Invalidate_I, addr);
#endif
}
}
@@ -227,18 +299,18 @@ static inline int protected_flush_icache_line(unsigned long addr)
static inline int protected_writeback_dcache_line(unsigned long addr)
{
#ifdef CONFIG_EVA
- return protected_cachee_op(Hit_Writeback_Inv_D, addr);
+ return protected_cachee_op_d(Hit_Writeback_Inv_D, addr);
#else
- return protected_cache_op(Hit_Writeback_Inv_D, addr);
+ return protected_cache_op_d(Hit_Writeback_Inv_D, addr);
#endif
}
static inline int protected_writeback_scache_line(unsigned long addr)
{
#ifdef CONFIG_EVA
- return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
+ return protected_cachee_op_s(Hit_Writeback_Inv_SD, addr);
#else
- return protected_cache_op(Hit_Writeback_Inv_SD, addr);
+ return protected_cache_op_s(Hit_Writeback_Inv_SD, addr);
#endif
}
@@ -247,7 +319,7 @@ static inline int protected_writeback_scache_line(unsigned long addr)
*/
static inline void invalidate_tcache_page(unsigned long addr)
{
- cache_op(Page_Invalidate_T, addr);
+ cache_op_t(Page_Invalidate_T, addr);
}
#ifndef CONFIG_CPU_MIPSR6
@@ -328,6 +400,65 @@ static inline void invalidate_tcache_page(unsigned long addr)
: \
: "r" (base), \
"i" (op));
+#ifdef CONFIG_CPU_R5900
+#define cache64_unroll32_d(base,op) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3 \n" \
+ " sync.l \n" \
+ " cache %1, 0x000(%0); sync.l; cache %1, 0x040(%0); sync.l \n" \
+ " cache %1, 0x080(%0); sync.l; cache %1, 0x0c0(%0); sync.l \n" \
+ " cache %1, 0x100(%0); sync.l; cache %1, 0x140(%0); sync.l \n" \
+ " cache %1, 0x180(%0); sync.l; cache %1, 0x1c0(%0); sync.l \n" \
+ " cache %1, 0x200(%0); sync.l; cache %1, 0x240(%0); sync.l \n" \
+ " cache %1, 0x280(%0); sync.l; cache %1, 0x2c0(%0); sync.l \n" \
+ " cache %1, 0x300(%0); sync.l; cache %1, 0x340(%0); sync.l \n" \
+ " cache %1, 0x380(%0); sync.l; cache %1, 0x3c0(%0); sync.l \n" \
+ " cache %1, 0x400(%0); sync.l; cache %1, 0x440(%0); sync.l \n" \
+ " cache %1, 0x480(%0); sync.l; cache %1, 0x4c0(%0); sync.l \n" \
+ " cache %1, 0x500(%0); sync.l; cache %1, 0x540(%0); sync.l \n" \
+ " cache %1, 0x580(%0); sync.l; cache %1, 0x5c0(%0); sync.l \n" \
+ " cache %1, 0x600(%0); sync.l; cache %1, 0x640(%0); sync.l \n" \
+ " cache %1, 0x680(%0); sync.l; cache %1, 0x6c0(%0); sync.l \n" \
+ " cache %1, 0x700(%0); sync.l; cache %1, 0x740(%0); sync.l \n" \
+ " cache %1, 0x780(%0); sync.l; cache %1, 0x7c0(%0); sync.l \n" \
+ " .set pop \n" \
+ : \
+ : "r" (base), \
+ "i" (op));
+
+#define cache64_unroll32_i(base,op) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3 \n" \
+ " sync.p \n" \
+ " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
+ " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \
+ " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \
+ " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \
+ " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \
+ " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \
+ " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \
+ " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \
+ " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \
+ " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \
+ " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \
+ " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \
+ " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \
+ " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
+ " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
+ " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
+ " sync.p \n" \
+ " .set pop \n" \
+ : \
+ : "r" (base), \
+ "i" (op));
+#else
+#define cache64_unroll32_i cache64_unroll32
+#define cache64_unroll32_d cache64_unroll32
+#endif
#define cache128_unroll32(base,op) \
__asm__ __volatile__( \
@@ -584,7 +715,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
"i" (op));
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
+#define __BUILD_BLAST_CACHE(fn_pfx, pfx, desc, indexop, hitop, lsize, extra) \
static inline void extra##blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
@@ -598,7 +729,7 @@ static inline void extra##blast_##pfx##cache##lsize(void) \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws, indexop); \
+ cache##lsize##_unroll32##fn_pfx(addr|ws, indexop); \
\
__##pfx##flush_epilogue \
} \
@@ -611,7 +742,7 @@ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
__##pfx##flush_prologue \
\
do { \
- cache##lsize##_unroll32(start, hitop); \
+ cache##lsize##_unroll32##fn_pfx(start, hitop); \
start += lsize * 32; \
} while (start < end); \
\
@@ -632,31 +763,31 @@ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws, indexop); \
+ cache##lsize##_unroll32##fn_pfx(addr|ws, indexop); \
\
__##pfx##flush_epilogue \
}
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(_d, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+__BUILD_BLAST_CACHE(_i, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+__BUILD_BLAST_CACHE(, inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(, inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
@@ -685,7 +816,7 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
/* build blast_xxx_range, protected_blast_xxx_range */
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
+#define __BUILD_BLAST_CACHE_RANGE(fn_pfx, pfx, desc, hitop, prot, extra) \
static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
@@ -696,7 +827,7 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
__##pfx##flush_prologue \
\
while (1) { \
- prot##cache_op(hitop, addr); \
+ prot##cache_op##fn_pfx(hitop, addr); \
R5900_LOOP_WAR(); /* FIXME: Is this needed in C? */ \
if (addr == aend) \
break; \
@@ -708,8 +839,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
#ifndef CONFIG_EVA
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_d, d, dcache, Hit_Writeback_Inv_D, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I, protected_, )
#else
@@ -746,14 +877,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
#endif
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+__BUILD_BLAST_CACHE_RANGE(_s, s, scache, Hit_Writeback_Inv_SD, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I_Loongson2, \
protected_, loongson2_)
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
+__BUILD_BLAST_CACHE_RANGE(_d, d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I, , )
+__BUILD_BLAST_CACHE_RANGE(_s, s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
+__BUILD_BLAST_CACHE_RANGE(_d, inv_d, dcache, Hit_Invalidate_D, , )
+__BUILD_BLAST_CACHE_RANGE(_d, inv_s, scache, Hit_Invalidate_SD, , )
#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3cd5bb465354..432ebd18cb7c 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1626,14 +1626,14 @@ static int probe_scache(void)
write_c0_taglo(0);
write_c0_taghi(0);
__asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
- cache_op(Index_Store_Tag_I, begin);
- cache_op(Index_Store_Tag_D, begin);
- cache_op(Index_Store_Tag_SD, begin);
+ cache_op_i(Index_Store_Tag_I, begin);
+ cache_op_d(Index_Store_Tag_D, begin);
+ cache_op_s(Index_Store_Tag_SD, begin);
/* Now search for the wrap around point. */
pow2 = (128 * 1024);
for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
- cache_op(Index_Load_Tag_SD, addr);
+ cache_op_s(Index_Load_Tag_SD, addr);
__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
if (!read_c0_taglo())
break;
next prev parent reply other threads:[~2018-02-11 7:47 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-27 13:23 [PATCH] MIPS: Add basic R5900 support Fredrik Noring
2017-08-28 13:53 ` Ralf Baechle
2017-08-28 17:11 ` Maciej W. Rozycki
2017-08-29 17:33 ` Fredrik Noring
2017-08-29 17:24 ` Maciej W. Rozycki
2017-08-29 17:24 ` Maciej W. Rozycki
2017-08-30 13:23 ` Fredrik Noring
2017-08-31 15:11 ` Maciej W. Rozycki
2017-08-31 15:11 ` Maciej W. Rozycki
2017-09-02 10:28 ` Fredrik Noring
2017-09-09 10:13 ` Maciej W. Rozycki
2017-09-09 10:13 ` Maciej W. Rozycki
2017-09-11 5:21 ` Maciej W. Rozycki
2017-09-11 5:21 ` Maciej W. Rozycki
2017-09-12 17:59 ` Fredrik Noring
2017-09-15 11:12 ` Maciej W. Rozycki
2017-09-15 11:12 ` Maciej W. Rozycki
2017-09-15 13:19 ` Fredrik Noring
2017-09-15 18:28 ` Maciej W. Rozycki
2017-09-15 18:28 ` Maciej W. Rozycki
2017-09-02 14:10 ` [PATCH v2] " Fredrik Noring
2017-09-11 5:18 ` Maciej W. Rozycki
2017-09-11 5:18 ` Maciej W. Rozycki
2017-09-11 15:17 ` Fredrik Noring
2017-09-14 13:50 ` Maciej W. Rozycki
2017-09-14 13:50 ` Maciej W. Rozycki
2017-09-16 13:34 ` Fredrik Noring
2017-09-18 17:05 ` Maciej W. Rozycki
2017-09-18 17:05 ` Maciej W. Rozycki
2017-09-18 19:24 ` Fredrik Noring
2017-09-19 12:44 ` Maciej W. Rozycki
2017-09-19 12:44 ` Maciej W. Rozycki
2017-09-20 14:54 ` Fredrik Noring
2017-09-26 11:50 ` Maciej W. Rozycki
2017-09-26 11:50 ` Maciej W. Rozycki
2017-09-27 17:21 ` Fredrik Noring
2017-09-28 12:13 ` Maciej W. Rozycki
2017-09-28 12:13 ` Maciej W. Rozycki
2017-09-30 6:56 ` Fredrik Noring
2017-10-02 9:05 ` Maciej W. Rozycki
2017-10-02 9:05 ` Maciej W. Rozycki
2017-10-02 16:33 ` Fredrik Noring
2017-10-29 17:20 ` Fredrik Noring
2017-11-10 23:34 ` Maciej W. Rozycki
2017-11-10 23:34 ` Maciej W. Rozycki
2017-11-11 16:04 ` Fredrik Noring
2018-01-29 20:27 ` Fredrik Noring
2018-01-31 23:01 ` Maciej W. Rozycki
2018-02-11 7:29 ` [RFC] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2018-02-12 9:25 ` Maciej W. Rozycki
2018-02-12 15:22 ` Fredrik Noring
2018-02-11 7:46 ` Fredrik Noring [this message]
2018-02-11 7:56 ` [RFC] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2018-02-12 9:28 ` Maciej W. Rozycki
2018-02-15 19:15 ` [RFC v2] " Fredrik Noring
2018-02-15 20:49 ` Maciej W. Rozycki
2018-02-17 11:16 ` Fredrik Noring
2018-02-17 11:57 ` Maciej W. Rozycki
2018-02-17 13:38 ` Fredrik Noring
2018-02-17 15:03 ` Maciej W. Rozycki
2018-02-17 20:04 ` Fredrik Noring
2018-02-20 14:09 ` Maciej W. Rozycki
2018-02-22 17:04 ` Fredrik Noring
2018-02-18 8:47 ` Fredrik Noring
2018-02-20 14:41 ` Maciej W. Rozycki
2018-02-22 17:27 ` Fredrik Noring
2018-02-11 8:01 ` [RFC] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2018-02-11 11:16 ` Aw: " "Jürgen Urban"
2018-02-11 8:09 ` [RFC] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2018-02-11 11:07 ` Aw: " "Jürgen Urban"
2018-02-11 8:29 ` [RFC] MIPS: R5900: Use mandatory SYNC.L in exception handlers Fredrik Noring
2018-02-11 10:33 ` Aw: " "Jürgen Urban"
2018-02-12 9:22 ` Maciej W. Rozycki
2018-02-12 9:22 ` Maciej W. Rozycki
2018-02-18 10:30 ` Fredrik Noring
2018-02-17 14:43 ` [RFC] MIPS: R5900: Workaround for saving and restoring FPU registers Fredrik Noring
2018-02-17 15:18 ` Maciej W. Rozycki
2018-02-17 17:47 ` Fredrik Noring
2018-02-17 19:33 ` Maciej W. Rozycki
2018-02-18 9:26 ` [RFC] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2018-02-18 11:08 ` [RFC] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2018-03-03 12:26 ` [RFC] MIPS: PS2: Interrupt request (IRQ) support Fredrik Noring
2018-03-03 13:09 ` Maciej W. Rozycki
2018-03-03 14:14 ` Fredrik Noring
2018-04-09 15:51 ` Fredrik Noring
2018-03-18 10:45 ` Fredrik Noring
2018-03-19 19:15 ` Thomas Gleixner
2018-06-18 18:52 ` [RFC v2] " Fredrik Noring
2017-10-30 17:55 ` [PATCH v2] MIPS: Add basic R5900 support Fredrik Noring
2017-11-24 10:26 ` Maciej W. Rozycki
2017-11-24 10:26 ` Maciej W. Rozycki
2017-11-24 10:39 ` Maciej W. Rozycki
2017-11-24 10:39 ` Maciej W. Rozycki
2017-09-20 14:07 ` Fredrik Noring
2017-09-21 21:07 ` Maciej W. Rozycki
2017-09-21 21:07 ` Maciej W. Rozycki
2017-09-22 16:37 ` Fredrik Noring
2017-09-22 16:37 ` Fredrik Noring
2017-09-29 23:55 ` Maciej W. Rozycki
2017-09-29 23:55 ` Maciej W. Rozycki
2017-09-30 18:26 ` Fredrik Noring
2017-10-02 9:11 ` Maciej W. Rozycki
2017-10-02 9:11 ` Maciej W. Rozycki
2017-10-03 19:49 ` Fredrik Noring
2017-10-05 19:04 ` Fredrik Noring
2017-10-06 20:28 ` Fredrik Noring
2017-10-15 16:39 ` Fredrik Noring
2017-10-17 12:23 ` Maciej W. Rozycki
2017-10-17 12:23 ` Maciej W. Rozycki
2017-10-21 18:00 ` Fredrik Noring
2017-10-23 16:10 ` Maciej W. Rozycki
2017-10-23 16:10 ` Maciej W. Rozycki
2017-09-21 18:11 ` Paul Burton
2017-09-21 18:11 ` Paul Burton
2017-09-21 19:48 ` Maciej W. Rozycki
2017-09-21 19:48 ` Maciej W. Rozycki
2017-10-29 18:42 ` Fredrik Noring
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