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From: "Maciej W. Rozycki" <macro@imgtec.com>
To: Fredrik Noring <noring@nocrew.org>
Cc: <linux-mips@linux-mips.org>
Subject: Re: [PATCH v2] MIPS: Add basic R5900 support
Date: Thu, 28 Sep 2017 13:13:45 +0100	[thread overview]
Message-ID: <alpine.DEB.2.00.1709272208300.16752@tp.orcam.me.uk> (raw)
In-Reply-To: <20170927172107.GB2631@localhost.localdomain>

Hi Fredrik,

> >  Instead I think these macros as well all the ones in <asm/stackframe.h> 
> > should remain unchanged and the save and restoration of the 64-bit upper 
> > halves done separately, most likely in `switch_to', which is where all the 
> > user context registers which like these upper halves are not touched by 
> > the kernel (and which are not handled lazily by other means) are switched.
> 
> Hmm... What about a 32-bit kernel and bits 63:32 sign-extended by kernel
> instructions? LONG_{L,S} saves/restores 31:0 using LW/SW thus 63:32 will
> be lost in exceptions?

 You mean for use with MMI instructions?  Offhand I think we have two 
options:

1. Declaring the lack of support for MMI instructions in o32 software.

2. Switching to using LD/SD in <asm/stackframe.h> and preserving statics 
   across syscalls with SAVE_STATIC/RESTORE_STATIC at the cost of
   performance loss.

I'm open for a better suggestion though.  I propose that we start with #1, 
as the zero performance cost and zero effort solution.

> >  Can you try a regular 32-bit MIPS Debian distribution instead?
> 
> BusyBox at
> 
> https://packages.debian.org/stretch/mipsel/busybox-static/download
> 
> seemed appropriate but yields "illegal instruction" which I suppose is
> interesting in itself. My MIPS toolchain is somewhat limited at the moment
> so I will need to get back on this.

 Getting a core dump and using it to figure out which specific instruction 
caused the exception would be interesting.  Also make sure you have RDHWR 
instruction emulation in place for CP0 UserLocal register access.

> >  BTW, I have just noticed that DMULT, DMULTU, DDIV and DDIVU instructions 
> > are not implemented.  Which means that a 64-bit kernel will only work if 
> > compiled with `-march=r5900' and emulation is required for 64-bit user 
> > programs.
> 
> Indeed. In the R5900 patch these instructions are emulated (or simulated as
> it is called in the source) in
> 
> https://github.com/frno7/linux/blob/1c8247e352d1eb7ae9022a76ecf19f74264534f7/arch/mips/kernel/traps.c
> 
> along with LLD, SCD, etc.

 Ah, OK then.

  Maciej

WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@imgtec.com>
To: Fredrik Noring <noring@nocrew.org>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH v2] MIPS: Add basic R5900 support
Date: Thu, 28 Sep 2017 13:13:45 +0100	[thread overview]
Message-ID: <alpine.DEB.2.00.1709272208300.16752@tp.orcam.me.uk> (raw)
Message-ID: <20170928121345.CNQgQZJFe4OfaDp8yc9NWIJek9XynqzZ9iXr86lMmDI@z> (raw)
In-Reply-To: <20170927172107.GB2631@localhost.localdomain>

Hi Fredrik,

> >  Instead I think these macros as well all the ones in <asm/stackframe.h> 
> > should remain unchanged and the save and restoration of the 64-bit upper 
> > halves done separately, most likely in `switch_to', which is where all the 
> > user context registers which like these upper halves are not touched by 
> > the kernel (and which are not handled lazily by other means) are switched.
> 
> Hmm... What about a 32-bit kernel and bits 63:32 sign-extended by kernel
> instructions? LONG_{L,S} saves/restores 31:0 using LW/SW thus 63:32 will
> be lost in exceptions?

 You mean for use with MMI instructions?  Offhand I think we have two 
options:

1. Declaring the lack of support for MMI instructions in o32 software.

2. Switching to using LD/SD in <asm/stackframe.h> and preserving statics 
   across syscalls with SAVE_STATIC/RESTORE_STATIC at the cost of
   performance loss.

I'm open for a better suggestion though.  I propose that we start with #1, 
as the zero performance cost and zero effort solution.

> >  Can you try a regular 32-bit MIPS Debian distribution instead?
> 
> BusyBox at
> 
> https://packages.debian.org/stretch/mipsel/busybox-static/download
> 
> seemed appropriate but yields "illegal instruction" which I suppose is
> interesting in itself. My MIPS toolchain is somewhat limited at the moment
> so I will need to get back on this.

 Getting a core dump and using it to figure out which specific instruction 
caused the exception would be interesting.  Also make sure you have RDHWR 
instruction emulation in place for CP0 UserLocal register access.

> >  BTW, I have just noticed that DMULT, DMULTU, DDIV and DDIVU instructions 
> > are not implemented.  Which means that a 64-bit kernel will only work if 
> > compiled with `-march=r5900' and emulation is required for 64-bit user 
> > programs.
> 
> Indeed. In the R5900 patch these instructions are emulated (or simulated as
> it is called in the source) in
> 
> https://github.com/frno7/linux/blob/1c8247e352d1eb7ae9022a76ecf19f74264534f7/arch/mips/kernel/traps.c
> 
> along with LLD, SCD, etc.

 Ah, OK then.

  Maciej

  reply	other threads:[~2017-09-28 12:14 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-27 13:23 [PATCH] MIPS: Add basic R5900 support Fredrik Noring
2017-08-28 13:53 ` Ralf Baechle
2017-08-28 17:11   ` Maciej W. Rozycki
2017-08-29 17:33   ` Fredrik Noring
2017-08-29 17:24 ` Maciej W. Rozycki
2017-08-29 17:24   ` Maciej W. Rozycki
2017-08-30 13:23   ` Fredrik Noring
2017-08-31 15:11     ` Maciej W. Rozycki
2017-08-31 15:11       ` Maciej W. Rozycki
2017-09-02 10:28   ` Fredrik Noring
2017-09-09 10:13     ` Maciej W. Rozycki
2017-09-09 10:13       ` Maciej W. Rozycki
2017-09-11  5:21       ` Maciej W. Rozycki
2017-09-11  5:21         ` Maciej W. Rozycki
2017-09-12 17:59         ` Fredrik Noring
2017-09-15 11:12           ` Maciej W. Rozycki
2017-09-15 11:12             ` Maciej W. Rozycki
2017-09-15 13:19             ` Fredrik Noring
2017-09-15 18:28               ` Maciej W. Rozycki
2017-09-15 18:28                 ` Maciej W. Rozycki
2017-09-02 14:10   ` [PATCH v2] " Fredrik Noring
2017-09-11  5:18     ` Maciej W. Rozycki
2017-09-11  5:18       ` Maciej W. Rozycki
2017-09-11 15:17       ` Fredrik Noring
2017-09-14 13:50         ` Maciej W. Rozycki
2017-09-14 13:50           ` Maciej W. Rozycki
2017-09-16 13:34           ` Fredrik Noring
2017-09-18 17:05             ` Maciej W. Rozycki
2017-09-18 17:05               ` Maciej W. Rozycki
2017-09-18 19:24               ` Fredrik Noring
2017-09-19 12:44                 ` Maciej W. Rozycki
2017-09-19 12:44                   ` Maciej W. Rozycki
2017-09-20 14:54                   ` Fredrik Noring
2017-09-26 11:50                     ` Maciej W. Rozycki
2017-09-26 11:50                       ` Maciej W. Rozycki
2017-09-27 17:21                       ` Fredrik Noring
2017-09-28 12:13                         ` Maciej W. Rozycki [this message]
2017-09-28 12:13                           ` Maciej W. Rozycki
2017-09-30  6:56                           ` Fredrik Noring
2017-10-02  9:05                             ` Maciej W. Rozycki
2017-10-02  9:05                               ` Maciej W. Rozycki
2017-10-02 16:33                               ` Fredrik Noring
2017-10-29 17:20                               ` Fredrik Noring
2017-11-10 23:34                                 ` Maciej W. Rozycki
2017-11-10 23:34                                   ` Maciej W. Rozycki
2017-11-11 16:04                                   ` Fredrik Noring
2018-01-29 20:27                                     ` Fredrik Noring
2018-01-31 23:01                                       ` Maciej W. Rozycki
2018-02-11  7:29                                         ` [RFC] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2018-02-12  9:25                                           ` Maciej W. Rozycki
2018-02-12 15:22                                             ` Fredrik Noring
2018-02-11  7:46                                         ` [RFC] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache Fredrik Noring
2018-02-11  7:56                                         ` [RFC] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2018-02-12  9:28                                           ` Maciej W. Rozycki
2018-02-15 19:15                                             ` [RFC v2] " Fredrik Noring
2018-02-15 20:49                                               ` Maciej W. Rozycki
2018-02-17 11:16                                                 ` Fredrik Noring
2018-02-17 11:57                                                   ` Maciej W. Rozycki
2018-02-17 13:38                                                     ` Fredrik Noring
2018-02-17 15:03                                                       ` Maciej W. Rozycki
2018-02-17 20:04                                                         ` Fredrik Noring
2018-02-20 14:09                                                           ` Maciej W. Rozycki
2018-02-22 17:04                                                             ` Fredrik Noring
2018-02-18  8:47                                                 ` Fredrik Noring
2018-02-20 14:41                                                   ` Maciej W. Rozycki
2018-02-22 17:27                                                     ` Fredrik Noring
2018-02-11  8:01                                         ` [RFC] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2018-02-11 11:16                                           ` Aw: " "Jürgen Urban"
2018-02-11  8:09                                         ` [RFC] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2018-02-11 11:07                                           ` Aw: " "Jürgen Urban"
2018-02-11  8:29                                         ` [RFC] MIPS: R5900: Use mandatory SYNC.L in exception handlers Fredrik Noring
2018-02-11 10:33                                           ` Aw: " "Jürgen Urban"
2018-02-12  9:22                                             ` Maciej W. Rozycki
2018-02-12  9:22                                               ` Maciej W. Rozycki
2018-02-18 10:30                                               ` Fredrik Noring
2018-02-17 14:43                                         ` [RFC] MIPS: R5900: Workaround for saving and restoring FPU registers Fredrik Noring
2018-02-17 15:18                                           ` Maciej W. Rozycki
2018-02-17 17:47                                             ` Fredrik Noring
2018-02-17 19:33                                               ` Maciej W. Rozycki
2018-02-18  9:26                                         ` [RFC] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2018-02-18 11:08                                         ` [RFC] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2018-03-03 12:26                                         ` [RFC] MIPS: PS2: Interrupt request (IRQ) support Fredrik Noring
2018-03-03 13:09                                           ` Maciej W. Rozycki
2018-03-03 14:14                                             ` Fredrik Noring
2018-04-09 15:51                                             ` Fredrik Noring
2018-03-18 10:45                                           ` Fredrik Noring
2018-03-19 19:15                                             ` Thomas Gleixner
2018-06-18 18:52                                             ` [RFC v2] " Fredrik Noring
2017-10-30 17:55                               ` [PATCH v2] MIPS: Add basic R5900 support Fredrik Noring
2017-11-24 10:26                                 ` Maciej W. Rozycki
2017-11-24 10:26                                   ` Maciej W. Rozycki
2017-11-24 10:39                                   ` Maciej W. Rozycki
2017-11-24 10:39                                     ` Maciej W. Rozycki
2017-09-20 14:07               ` Fredrik Noring
2017-09-21 21:07                 ` Maciej W. Rozycki
2017-09-21 21:07                   ` Maciej W. Rozycki
2017-09-22 16:37                   ` Fredrik Noring
2017-09-22 16:37                     ` Fredrik Noring
2017-09-29 23:55                     ` Maciej W. Rozycki
2017-09-29 23:55                       ` Maciej W. Rozycki
2017-09-30 18:26                       ` Fredrik Noring
2017-10-02  9:11                         ` Maciej W. Rozycki
2017-10-02  9:11                           ` Maciej W. Rozycki
2017-10-03 19:49                           ` Fredrik Noring
2017-10-05 19:04                             ` Fredrik Noring
2017-10-06 20:28                           ` Fredrik Noring
2017-10-15 16:39                             ` Fredrik Noring
2017-10-17 12:23                               ` Maciej W. Rozycki
2017-10-17 12:23                                 ` Maciej W. Rozycki
2017-10-21 18:00                                 ` Fredrik Noring
2017-10-23 16:10                                   ` Maciej W. Rozycki
2017-10-23 16:10                                     ` Maciej W. Rozycki
2017-09-21 18:11               ` Paul Burton
2017-09-21 18:11                 ` Paul Burton
2017-09-21 19:48                 ` Maciej W. Rozycki
2017-09-21 19:48                   ` Maciej W. Rozycki
2017-10-29 18:42       ` Fredrik Noring

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