From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: <linux-mips@linux-mips.org> Subject: Re: [PATCH] MIPS: Add basic R5900 support Date: Thu, 31 Aug 2017 16:11:53 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1708311259220.17596@tp.orcam.me.uk> (raw) In-Reply-To: <20170830132350.GA2110@localhost.localdomain> Hi Fredrik, > > Is there an external explicitly-driven write-back buffer there with the > > R5900? That would be odd with a MIPS III ISA processor, however if there > > indeed is, then I think the CPU_HAS_WB setting needs to go along with the > > code that implements `__wbflush' for this platform. > > The C790 block diagram contains a WBB connected to the BIU bus (p. 2-2) in the > "TX System RISC TX79 Core Architecture" manual: > > The Writeback Buffer (WBB) is an 8 entry by 16 byte (one quadword) FIFO > queuing up stores prior to accessing the CPU bus. It increases C790 > performance by decoupling the processor from the latencies of the CPU bus. > It is also used during the gathering operation of uncached accelerated > stores; sequential stores less than a quadword in length are gathered in > the WBB, thereby reducing bus bandwidth usage. (p. 2-4) That's no different though from the write-back buffer the R4400 CPU has, as do many more modern MIPS architecture implementations, with strong bus (and hence memory) ordering enforced by the SYNC instruction. In that case a lone SYNC instruction is sufficient as the implementation of the `wmb', `rmb' and `mb' memory ordering barrier operations. > __wbflush is implemented in arch/mips/ps2/setup.c:193 in the remaining patch > (link below): > > static void ps2_wbflush(void) > { > __asm__ __volatile__("sync.l":::"memory"); > > /* flush write buffer to bus */ > inl(ps2sif_bustophys(0)); > } > > https://github.com/frno7/linux/blob/ps2-v4.12-squashed/arch/mips/ps2/setup.c#L193 > > Then ps2sif_bustophys is implemented in arch/mips/ps2/iopheap.c: > > phys_addr_t ps2sif_bustophys(dma_addr_t a) > { > return(a + PS2_IOP_HEAP_BASE); > } > > which in turn uses > > #define PS2_IOP_HEAP_BASE 0x1c000000 > > from arch/mips/include/asm/mach-ps2/ps2.h. Would you like to move this code > somewhere else to go along with the declaration of CPU_HAS_WB? This looks to me like a completion barrier, rather than a bus ordering barrier that would require a special `__wbflush' implementation. Here SYNC.L (which is BTW an assembly idiom for plain SYNC) enforces strong ordering, acting as `mb' as per the architecture requirement, and the following read back causes all the outstanding bus accesses to retire beforehand, acting as a completion barrier. So I think this `ps2_wbflush' completion barrier should be used as the implementation of `mmiowb', or (suspecting that with SYNC already in the picture it would be too strong for this platform, unless the chipset can do further write merging or reordering) perhaps just `iob', or a more general `iobarrier_sync' operation I have outlined here: <https://marc.info/?l=linux-kernel&m=139868504324701&w=2> (but never got to implementing). In that case you don't need to select CPU_HAS_WB, as the platform does not have a write-back buffer that would require special handling for bus ordering purposes. Let me know if you have any questions or comments. Maciej
WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Add basic R5900 support Date: Thu, 31 Aug 2017 16:11:53 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1708311259220.17596@tp.orcam.me.uk> (raw) Message-ID: <20170831151153.W-IAZDhOt6Zv_bSxr_rEcC0mf_9QkyPvrl74Y5CUXpQ@z> (raw) In-Reply-To: <20170830132350.GA2110@localhost.localdomain> Hi Fredrik, > > Is there an external explicitly-driven write-back buffer there with the > > R5900? That would be odd with a MIPS III ISA processor, however if there > > indeed is, then I think the CPU_HAS_WB setting needs to go along with the > > code that implements `__wbflush' for this platform. > > The C790 block diagram contains a WBB connected to the BIU bus (p. 2-2) in the > "TX System RISC TX79 Core Architecture" manual: > > The Writeback Buffer (WBB) is an 8 entry by 16 byte (one quadword) FIFO > queuing up stores prior to accessing the CPU bus. It increases C790 > performance by decoupling the processor from the latencies of the CPU bus. > It is also used during the gathering operation of uncached accelerated > stores; sequential stores less than a quadword in length are gathered in > the WBB, thereby reducing bus bandwidth usage. (p. 2-4) That's no different though from the write-back buffer the R4400 CPU has, as do many more modern MIPS architecture implementations, with strong bus (and hence memory) ordering enforced by the SYNC instruction. In that case a lone SYNC instruction is sufficient as the implementation of the `wmb', `rmb' and `mb' memory ordering barrier operations. > __wbflush is implemented in arch/mips/ps2/setup.c:193 in the remaining patch > (link below): > > static void ps2_wbflush(void) > { > __asm__ __volatile__("sync.l":::"memory"); > > /* flush write buffer to bus */ > inl(ps2sif_bustophys(0)); > } > > https://github.com/frno7/linux/blob/ps2-v4.12-squashed/arch/mips/ps2/setup.c#L193 > > Then ps2sif_bustophys is implemented in arch/mips/ps2/iopheap.c: > > phys_addr_t ps2sif_bustophys(dma_addr_t a) > { > return(a + PS2_IOP_HEAP_BASE); > } > > which in turn uses > > #define PS2_IOP_HEAP_BASE 0x1c000000 > > from arch/mips/include/asm/mach-ps2/ps2.h. Would you like to move this code > somewhere else to go along with the declaration of CPU_HAS_WB? This looks to me like a completion barrier, rather than a bus ordering barrier that would require a special `__wbflush' implementation. Here SYNC.L (which is BTW an assembly idiom for plain SYNC) enforces strong ordering, acting as `mb' as per the architecture requirement, and the following read back causes all the outstanding bus accesses to retire beforehand, acting as a completion barrier. So I think this `ps2_wbflush' completion barrier should be used as the implementation of `mmiowb', or (suspecting that with SYNC already in the picture it would be too strong for this platform, unless the chipset can do further write merging or reordering) perhaps just `iob', or a more general `iobarrier_sync' operation I have outlined here: <https://marc.info/?l=linux-kernel&m=139868504324701&w=2> (but never got to implementing). In that case you don't need to select CPU_HAS_WB, as the platform does not have a write-back buffer that would require special handling for bus ordering purposes. Let me know if you have any questions or comments. Maciej
next prev parent reply other threads:[~2017-08-31 15:12 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-27 13:23 [PATCH] MIPS: Add basic R5900 support Fredrik Noring 2017-08-28 13:53 ` Ralf Baechle 2017-08-28 17:11 ` Maciej W. Rozycki 2017-08-29 17:33 ` Fredrik Noring 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-30 13:23 ` Fredrik Noring 2017-08-31 15:11 ` Maciej W. Rozycki [this message] 2017-08-31 15:11 ` Maciej W. Rozycki 2017-09-02 10:28 ` Fredrik Noring 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-12 17:59 ` Fredrik Noring 2017-09-15 11:12 ` Maciej W. Rozycki 2017-09-15 11:12 ` Maciej W. Rozycki 2017-09-15 13:19 ` Fredrik Noring 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-02 14:10 ` [PATCH v2] " Fredrik Noring 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 15:17 ` Fredrik Noring 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-16 13:34 ` Fredrik Noring 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 19:24 ` Fredrik Noring 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-20 14:54 ` Fredrik Noring 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-27 17:21 ` Fredrik Noring 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-30 6:56 ` Fredrik Noring 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 16:33 ` Fredrik Noring 2017-10-29 17:20 ` Fredrik Noring 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-11 16:04 ` Fredrik Noring 2018-01-29 20:27 ` Fredrik Noring 2018-01-31 23:01 ` Maciej W. Rozycki 2018-02-11 7:29 ` [RFC] MIPS: R5900: Workaround for the short loop bug Fredrik Noring 2018-02-12 9:25 ` Maciej W. Rozycki 2018-02-12 15:22 ` Fredrik Noring 2018-02-11 7:46 ` [RFC] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache Fredrik Noring 2018-02-11 7:56 ` [RFC] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring 2018-02-12 9:28 ` Maciej W. Rozycki 2018-02-15 19:15 ` [RFC v2] " Fredrik Noring 2018-02-15 20:49 ` Maciej W. Rozycki 2018-02-17 11:16 ` Fredrik Noring 2018-02-17 11:57 ` Maciej W. Rozycki 2018-02-17 13:38 ` Fredrik Noring 2018-02-17 15:03 ` Maciej W. Rozycki 2018-02-17 20:04 ` Fredrik Noring 2018-02-20 14:09 ` Maciej W. Rozycki 2018-02-22 17:04 ` Fredrik Noring 2018-02-18 8:47 ` Fredrik Noring 2018-02-20 14:41 ` Maciej W. Rozycki 2018-02-22 17:27 ` Fredrik Noring 2018-02-11 8:01 ` [RFC] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring 2018-02-11 11:16 ` Aw: " "Jürgen Urban" 2018-02-11 8:09 ` [RFC] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring 2018-02-11 11:07 ` Aw: " "Jürgen Urban" 2018-02-11 8:29 ` [RFC] MIPS: R5900: Use mandatory SYNC.L in exception handlers Fredrik Noring 2018-02-11 10:33 ` Aw: " "Jürgen Urban" 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-18 10:30 ` Fredrik Noring 2018-02-17 14:43 ` [RFC] MIPS: R5900: Workaround for saving and restoring FPU registers Fredrik Noring 2018-02-17 15:18 ` Maciej W. Rozycki 2018-02-17 17:47 ` Fredrik Noring 2018-02-17 19:33 ` Maciej W. Rozycki 2018-02-18 9:26 ` [RFC] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring 2018-02-18 11:08 ` [RFC] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring 2018-03-03 12:26 ` [RFC] MIPS: PS2: Interrupt request (IRQ) support Fredrik Noring 2018-03-03 13:09 ` Maciej W. Rozycki 2018-03-03 14:14 ` Fredrik Noring 2018-04-09 15:51 ` Fredrik Noring 2018-03-18 10:45 ` Fredrik Noring 2018-03-19 19:15 ` Thomas Gleixner 2018-06-18 18:52 ` [RFC v2] " Fredrik Noring 2017-10-30 17:55 ` [PATCH v2] MIPS: Add basic R5900 support Fredrik Noring 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-09-20 14:07 ` Fredrik Noring 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-22 16:37 ` Fredrik Noring 2017-09-22 16:37 ` Fredrik Noring 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-30 18:26 ` Fredrik Noring 2017-10-02 9:11 ` Maciej W. Rozycki 2017-10-02 9:11 ` Maciej W. Rozycki 2017-10-03 19:49 ` Fredrik Noring 2017-10-05 19:04 ` Fredrik Noring 2017-10-06 20:28 ` Fredrik Noring 2017-10-15 16:39 ` Fredrik Noring 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-21 18:00 ` Fredrik Noring 2017-10-23 16:10 ` Maciej W. Rozycki 2017-10-23 16:10 ` Maciej W. Rozycki 2017-09-21 18:11 ` Paul Burton 2017-09-21 18:11 ` Paul Burton 2017-09-21 19:48 ` Maciej W. Rozycki 2017-09-21 19:48 ` Maciej W. Rozycki 2017-10-29 18:42 ` Fredrik Noring
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=alpine.DEB.2.00.1708311259220.17596@tp.orcam.me.uk \ --to=macro@imgtec.com \ --cc=linux-mips@linux-mips.org \ --cc=noring@nocrew.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.