From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: <linux-mips@linux-mips.org> Subject: Re: [PATCH] MIPS: Add basic R5900 support Date: Fri, 15 Sep 2017 12:12:37 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1709151136220.16752@tp.orcam.me.uk> (raw) In-Reply-To: <20170912175826.GA2526@localhost.localdomain> Hi Fredrik, > > > Can you please try flipping the bits instead then, e.g.: > > > > > > uint32_t fcsr0, fcsr1; > > > asm volatile (" cfc1 %0,$31\n" > > > " lui %1,0xfffc\n" > > > > Actually can you please substitute: > > > > " li %1,0xfffc0003\n" > > > > here, so that we know how RM behaves? > > Sure. I get "FCSR old: 01000001, new: 01800001" with the R5900. Thanks, that is as I suspected then. I wonder if FS=1 hardwired also means the Underflow exception cannot happen. As the corresponding Cause and Enable bits cannot be set together or an FPE exception will happen right away, and the Unimplemented Operation exception is uncoditional so we need to leave it out, can you please also try these masks in turns: " li %1,0x0001f07c\n" and: " li %1,0x00000f80\n" This will reveal if any of the Cause, Enable or Flag bits are hardwired. > > Again, it is odd to see it set to 1 (towards zero) by default and if it > > is hardwired, then `->fpu_csr31' and `->fpu_msk31' will have to be > > updated, AT_FPUCW exported and glibc adjusted. > > Right. Quite a few details to resolve for the FPU then. Here is the > disassembly to double-check the compiled code: Nothing unusual here. As you can see GCC has been smart enough to schedule temporaries right in argument registers passed to the `printf' call. :) Maciej
WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Add basic R5900 support Date: Fri, 15 Sep 2017 12:12:37 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1709151136220.16752@tp.orcam.me.uk> (raw) Message-ID: <20170915111237.idmUaTJF0DLIW2Xe1uSgXcld4fpdrfgwmuDKa0atHVw@z> (raw) In-Reply-To: <20170912175826.GA2526@localhost.localdomain> Hi Fredrik, > > > Can you please try flipping the bits instead then, e.g.: > > > > > > uint32_t fcsr0, fcsr1; > > > asm volatile (" cfc1 %0,$31\n" > > > " lui %1,0xfffc\n" > > > > Actually can you please substitute: > > > > " li %1,0xfffc0003\n" > > > > here, so that we know how RM behaves? > > Sure. I get "FCSR old: 01000001, new: 01800001" with the R5900. Thanks, that is as I suspected then. I wonder if FS=1 hardwired also means the Underflow exception cannot happen. As the corresponding Cause and Enable bits cannot be set together or an FPE exception will happen right away, and the Unimplemented Operation exception is uncoditional so we need to leave it out, can you please also try these masks in turns: " li %1,0x0001f07c\n" and: " li %1,0x00000f80\n" This will reveal if any of the Cause, Enable or Flag bits are hardwired. > > Again, it is odd to see it set to 1 (towards zero) by default and if it > > is hardwired, then `->fpu_csr31' and `->fpu_msk31' will have to be > > updated, AT_FPUCW exported and glibc adjusted. > > Right. Quite a few details to resolve for the FPU then. Here is the > disassembly to double-check the compiled code: Nothing unusual here. As you can see GCC has been smart enough to schedule temporaries right in argument registers passed to the `printf' call. :) Maciej
next prev parent reply other threads:[~2017-09-15 11:13 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-27 13:23 [PATCH] MIPS: Add basic R5900 support Fredrik Noring 2017-08-28 13:53 ` Ralf Baechle 2017-08-28 17:11 ` Maciej W. Rozycki 2017-08-29 17:33 ` Fredrik Noring 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-30 13:23 ` Fredrik Noring 2017-08-31 15:11 ` Maciej W. Rozycki 2017-08-31 15:11 ` Maciej W. Rozycki 2017-09-02 10:28 ` Fredrik Noring 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-12 17:59 ` Fredrik Noring 2017-09-15 11:12 ` Maciej W. Rozycki [this message] 2017-09-15 11:12 ` Maciej W. Rozycki 2017-09-15 13:19 ` Fredrik Noring 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-02 14:10 ` [PATCH v2] " Fredrik Noring 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 15:17 ` Fredrik Noring 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-16 13:34 ` Fredrik Noring 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 19:24 ` Fredrik Noring 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-20 14:54 ` Fredrik Noring 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-27 17:21 ` Fredrik Noring 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-30 6:56 ` Fredrik Noring 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 16:33 ` Fredrik Noring 2017-10-29 17:20 ` Fredrik Noring 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-11 16:04 ` Fredrik Noring 2018-01-29 20:27 ` Fredrik Noring 2018-01-31 23:01 ` Maciej W. Rozycki 2018-02-11 7:29 ` [RFC] MIPS: R5900: Workaround for the short loop bug Fredrik Noring 2018-02-12 9:25 ` Maciej W. Rozycki 2018-02-12 15:22 ` Fredrik Noring 2018-02-11 7:46 ` [RFC] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache Fredrik Noring 2018-02-11 7:56 ` [RFC] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring 2018-02-12 9:28 ` Maciej W. Rozycki 2018-02-15 19:15 ` [RFC v2] " Fredrik Noring 2018-02-15 20:49 ` Maciej W. Rozycki 2018-02-17 11:16 ` Fredrik Noring 2018-02-17 11:57 ` Maciej W. Rozycki 2018-02-17 13:38 ` Fredrik Noring 2018-02-17 15:03 ` Maciej W. Rozycki 2018-02-17 20:04 ` Fredrik Noring 2018-02-20 14:09 ` Maciej W. Rozycki 2018-02-22 17:04 ` Fredrik Noring 2018-02-18 8:47 ` Fredrik Noring 2018-02-20 14:41 ` Maciej W. Rozycki 2018-02-22 17:27 ` Fredrik Noring 2018-02-11 8:01 ` [RFC] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring 2018-02-11 11:16 ` Aw: " "Jürgen Urban" 2018-02-11 8:09 ` [RFC] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring 2018-02-11 11:07 ` Aw: " "Jürgen Urban" 2018-02-11 8:29 ` [RFC] MIPS: R5900: Use mandatory SYNC.L in exception handlers Fredrik Noring 2018-02-11 10:33 ` Aw: " "Jürgen Urban" 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-18 10:30 ` Fredrik Noring 2018-02-17 14:43 ` [RFC] MIPS: R5900: Workaround for saving and restoring FPU registers Fredrik Noring 2018-02-17 15:18 ` Maciej W. Rozycki 2018-02-17 17:47 ` Fredrik Noring 2018-02-17 19:33 ` Maciej W. Rozycki 2018-02-18 9:26 ` [RFC] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring 2018-02-18 11:08 ` [RFC] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring 2018-03-03 12:26 ` [RFC] MIPS: PS2: Interrupt request (IRQ) support Fredrik Noring 2018-03-03 13:09 ` Maciej W. Rozycki 2018-03-03 14:14 ` Fredrik Noring 2018-04-09 15:51 ` Fredrik Noring 2018-03-18 10:45 ` Fredrik Noring 2018-03-19 19:15 ` Thomas Gleixner 2018-06-18 18:52 ` [RFC v2] " Fredrik Noring 2017-10-30 17:55 ` [PATCH v2] MIPS: Add basic R5900 support Fredrik Noring 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-09-20 14:07 ` Fredrik Noring 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-22 16:37 ` Fredrik Noring 2017-09-22 16:37 ` Fredrik Noring 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-30 18:26 ` Fredrik Noring 2017-10-02 9:11 ` Maciej W. Rozycki 2017-10-02 9:11 ` Maciej W. Rozycki 2017-10-03 19:49 ` Fredrik Noring 2017-10-05 19:04 ` Fredrik Noring 2017-10-06 20:28 ` Fredrik Noring 2017-10-15 16:39 ` Fredrik Noring 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-21 18:00 ` Fredrik Noring 2017-10-23 16:10 ` Maciej W. Rozycki 2017-10-23 16:10 ` Maciej W. Rozycki 2017-09-21 18:11 ` Paul Burton 2017-09-21 18:11 ` Paul Burton 2017-09-21 19:48 ` Maciej W. Rozycki 2017-09-21 19:48 ` Maciej W. Rozycki 2017-10-29 18:42 ` Fredrik Noring
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