All of lore.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <anup@brainfault.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 3/4] riscv: Add S-mode defconfigs for QEMU virt machine
Date: Mon, 26 Nov 2018 16:09:09 +0530	[thread overview]
Message-ID: <20181126103910.14457-4-anup@brainfault.org> (raw)
In-Reply-To: <20181126103910.14457-1-anup@brainfault.org>

This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
 board/emulation/qemu-riscv/MAINTAINERS |  2 ++
 configs/qemu-riscv32_smode_defconfig   | 10 ++++++++++
 configs/qemu-riscv64_smode_defconfig   | 11 +++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 configs/qemu-riscv32_smode_defconfig
 create mode 100644 configs/qemu-riscv64_smode_defconfig

diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
index 3c6eb4f844..c701c83d77 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -4,4 +4,6 @@ S:	Maintained
 F:	board/emulation/qemu-riscv/
 F:	include/configs/qemu-riscv.h
 F:	configs/qemu-riscv32_defconfig
+F:	configs/qemu-riscv32_smode_defconfig
 F:	configs/qemu-riscv64_defconfig
+F:	configs/qemu-riscv64_smode_defconfig
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
new file mode 100644
index 0000000000..0a84ec1874
--- /dev/null
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -0,0 +1,10 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
new file mode 100644
index 0000000000..b012443370
--- /dev/null
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
-- 
2.17.1

  parent reply	other threads:[~2018-11-26 10:39 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-26 10:39 [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode Anup Patel
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50B90@ATCPCS16.andestech.com>
2018-11-27  6:40     ` Rick Chen
2018-11-27  6:52       ` Anup Patel
2018-11-27 10:47         ` Alexander Graf
2018-11-27 12:38           ` Anup Patel
2018-11-30  7:05             ` Rick Chen
2018-11-30  8:53               ` Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode Anup Patel
2018-11-26 10:39 ` Anup Patel [this message]
2018-11-26 10:39 ` [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S Anup Patel
2018-11-26 15:10   ` Bin Meng
2018-11-26 22:10     ` Auer, Lukas
     [not found]       ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50A96@ATCPCS16.andestech.com>
2018-11-27  3:21         ` Rick Chen
2018-11-27  3:28           ` Anup Patel
2018-11-27  5:20             ` Rick Chen
2018-11-27  5:44               ` Anup Patel
2018-11-27  5:47                 ` Anup Patel
2018-11-27  6:09                   ` Rick Chen
2018-11-27  6:13                     ` Anup Patel
2018-11-27  6:31                       ` Rick Chen
2018-11-27  6:40                         ` Anup Patel
2018-11-27  7:01                           ` Rick Chen
2018-11-27  7:56                             ` Anup Patel
2018-11-27  8:42                               ` Anup Patel
2018-11-27 10:41                                 ` Alexander Graf
2018-11-29 10:44                                   ` Rick Chen
2018-11-27  8:43                               ` Rick Chen
2018-11-27 10:07                                 ` Bin Meng
2018-11-29 10:42                                   ` Rick Chen
2018-11-29 11:29                                     ` Rick Chen
2018-11-30  1:47                                     ` Bin Meng
2018-11-30  6:06                                       ` Rick Chen
2018-11-30  6:21                                         ` Bin Meng
2018-11-30  6:41                                           ` Rick Chen
2018-11-30  6:57                                             ` Bin Meng
2018-11-30  7:16                                               ` Rick Chen
2018-11-30  7:26                                                 ` Bin Meng
2018-11-30  7:31                                                   ` Rick Chen
2018-11-27  6:45                     ` Rick Chen
2018-11-27  6:56                       ` Anup Patel
2018-11-27 10:00               ` Bin Meng
2018-11-27  9:56             ` Bin Meng
2018-11-28 12:22 ` [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181126103910.14457-4-anup@brainfault.org \
    --to=anup@brainfault.org \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.