[U-Boot] [PATCH v5 0/4] RISC-V S-mode support

[Anup Patel <anup@brainfault.org>]

On Mon, Nov 26, 2018 at 4:13 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patchset allows us runing u-boot in S-mode which is
> useful on platforms where M-mode runtime firmware is an
> independent firmware and u-boot is used as last stage OS
> bootloader.
>
> The patchset based upon git://git.denx.de/u-boot-riscv.git
> and is tested on QEMU in both M-mode and S-mode.
>
> For S-mode testing, we have used u-boot.bin as payload of
> latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26)
> applied with following changes:
>
> diff --git a/machine/emulation.c b/machine/emulation.c
> index 132e977..def75e1 100644
> --- a/machine/emulation.c
> +++ b/machine/emulation.c
> @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result
>
>    switch (num)
>    {
> +    case CSR_MISA:
> +      *result = read_csr(misa);
> +      return 0;
> +    case CSR_MHARTID:
> +      *result = read_csr(mhartid);
> +      return 0;
>      case CSR_CYCLE:
>        if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1))
>          return -1;
>
> Changes since v4:
>  - Rebased series based on commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb
>    of git://git.denx.de/u-boot-riscv.git
>  - Added a patch to remove redundant a2 store on DRAM base. This
>    store was creating problem booting U-Boot in S-mode using BBL.
>
> Changes since v3:
>  - Replaced 'u-boot' with 'U-Boot' in commit message
>  - Dropped 'an' in RISCV_SMODE kconfig option help message
>  - Added appropriate #ifdef in arch/riscv/lib/interrupts.c
>
> Changes since v2:
>  - Dropped 'default n" from RISCV_SMODE kconfig option
>  - Replaced '-smode_' in defconfig names with '_smode_'
>
> Changes since v1:
>  - Rebased upon latest git://git.denx.de/u-boot-riscv.git
>  - Add details in cover letter for running u-boot in S-mode
>    using BBL
>
> Anup Patel (4):
>   riscv: Add kconfig option to run U-Boot in S-mode
>   riscv: qemu: Use different SYS_TEXT_BASE for S-mode
>   riscv: Add S-mode defconfigs for QEMU virt machine
>   riscv: Remove redundant a2 store on DRAM base in start.S
>
>  arch/riscv/Kconfig                     |  5 ++++
>  arch/riscv/cpu/start.S                 | 35 +++++++++++++++++++++++--
>  arch/riscv/include/asm/encoding.h      |  2 ++
>  arch/riscv/lib/interrupts.c            | 36 +++++++++++++++++++-------
>  board/emulation/qemu-riscv/Kconfig     |  3 ++-
>  board/emulation/qemu-riscv/MAINTAINERS |  2 ++
>  configs/qemu-riscv32_smode_defconfig   | 10 +++++++
>  configs/qemu-riscv64_smode_defconfig   | 11 ++++++++
>  8 files changed, 92 insertions(+), 12 deletions(-)
>  create mode 100644 configs/qemu-riscv32_smode_defconfig
>  create mode 100644 configs/qemu-riscv64_smode_defconfig
>
> --
> 2.17.1
>

Hi Rick,

If its fine with you then please take PATCH 1-to-3

The PATCH 4 "riscv: Remove redundant a2 store on DRAM base in start.S"
you can drop and merge a better solution at your end.

Regards,
Anup