From: Rick Chen <rickchen36@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S
Date: Tue, 27 Nov 2018 11:21:40 +0800 [thread overview]
Message-ID: <CAN5B=eLV=4QJa3p8FridA_qJPYcAj_Yx_uhh2-eHd_x7VHj0Pw@mail.gmail.com> (raw)
In-Reply-To: <752D002CFF5D0F4FA35C0100F1D73F3FA3A50A96@ATCPCS16.andestech.com>
> > > > Currently, the RISC-V U-Boot is saving a2 register at
> > > > CONFIG_SYS_DRAM_BASE in start.S which does not make sense because
> > > > there is no information passed by previous booting stage in a2
> > > > register.
> > > >
> > > > This patch removes redundant a2 store on DRAM base.
> > > >
> > > > Signed-off-by: Anup Patel <anup@brainfault.org>
> > > > ---
> > > > arch/riscv/cpu/start.S | 2 --
> > > > 1 file changed, 2 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index
> > > > 704190f946..e4276e8e19 100644
> > > > --- a/arch/riscv/cpu/start.S
> > > > +++ b/arch/riscv/cpu/start.S
> > > > @@ -38,8 +38,6 @@ _start:
> > > > mv s0, a0
> > > > mv s1, a1
> > > >
> > > > - li t0, CONFIG_SYS_SDRAM_BASE
> > > > - SREG a2, 0(t0)
> > > > la t0, trap_entry
> > > > #ifdef CONFIG_RISCV_SMODE
> > > > csrw stvec, t0
> > > > --
> > >
> > > This is weird. I remember these two lines were already removed by
> > > Lukas's patch series before? Did not have time to dig out the history
> > > though.
> > >
> > > Regards,
> > > Bin
> >
> > You are correct, however I removed it again, because I did not want to break
> > Rick's board. He did add a commit to the last pull request that removes these
> > two lines and adjusts his board accordingly, but it is not in the current one.
> >
Hi Likas
Thanks for your explanation.
RIck's commit as below
https://www.mail-archive.com/u-boot at lists.denx.de/msg305880.html
B.R
Rick
> > Thanks,
> > Lukas
next prev parent reply other threads:[~2018-11-27 3:21 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-26 10:39 [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode Anup Patel
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50B90@ATCPCS16.andestech.com>
2018-11-27 6:40 ` Rick Chen
2018-11-27 6:52 ` Anup Patel
2018-11-27 10:47 ` Alexander Graf
2018-11-27 12:38 ` Anup Patel
2018-11-30 7:05 ` Rick Chen
2018-11-30 8:53 ` Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 3/4] riscv: Add S-mode defconfigs for QEMU virt machine Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S Anup Patel
2018-11-26 15:10 ` Bin Meng
2018-11-26 22:10 ` Auer, Lukas
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50A96@ATCPCS16.andestech.com>
2018-11-27 3:21 ` Rick Chen [this message]
2018-11-27 3:28 ` Anup Patel
2018-11-27 5:20 ` Rick Chen
2018-11-27 5:44 ` Anup Patel
2018-11-27 5:47 ` Anup Patel
2018-11-27 6:09 ` Rick Chen
2018-11-27 6:13 ` Anup Patel
2018-11-27 6:31 ` Rick Chen
2018-11-27 6:40 ` Anup Patel
2018-11-27 7:01 ` Rick Chen
2018-11-27 7:56 ` Anup Patel
2018-11-27 8:42 ` Anup Patel
2018-11-27 10:41 ` Alexander Graf
2018-11-29 10:44 ` Rick Chen
2018-11-27 8:43 ` Rick Chen
2018-11-27 10:07 ` Bin Meng
2018-11-29 10:42 ` Rick Chen
2018-11-29 11:29 ` Rick Chen
2018-11-30 1:47 ` Bin Meng
2018-11-30 6:06 ` Rick Chen
2018-11-30 6:21 ` Bin Meng
2018-11-30 6:41 ` Rick Chen
2018-11-30 6:57 ` Bin Meng
2018-11-30 7:16 ` Rick Chen
2018-11-30 7:26 ` Bin Meng
2018-11-30 7:31 ` Rick Chen
2018-11-27 6:45 ` Rick Chen
2018-11-27 6:56 ` Anup Patel
2018-11-27 10:00 ` Bin Meng
2018-11-27 9:56 ` Bin Meng
2018-11-28 12:22 ` [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
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