From: Rick Chen <rickchen36@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S
Date: Tue, 27 Nov 2018 14:45:32 +0800 [thread overview]
Message-ID: <CAN5B=eKcxx8YTVJEGFX5z1ebZsHbwEADz5_G91TMdX6HghsLfA@mail.gmail.com> (raw)
In-Reply-To: <CAN5B=eLePZFBBWpRV715yt1DvkfPy1E7PFYGuVMANpSHpgO3_g@mail.gmail.com>
> > > > > When we run U-Boot in S-mode the BBL runs from 0x80000000 so this
> > > > > two lines corrupts BBL instructions.
Hi Anup
You said
Your patchset based upon git://git.denx.de/u-boot-riscv.git
Why you announce this problem in [PATCH v5 4/4] riscv: Remove
redundant a2 store on DRAM base in start.S
Why you do not find this proble in v1, v2, v3, v4 ?
Rick
> > > > >
> > > > > If this is important for some board then please have it around #ifdef.
> > > > >
> > > >
> > > > Hi Anup
> > > >
> > > > In the discussion as below :
> > > > https://www.mail-archive.com/u-boot at lists.denx.de/msg305880.html
> > > >
> > > > I try to solve this issue with the aptch
> > > > [PATCH] riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
> > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > > > - li t0, CONFIG_SYS_SDRAM_BASE
> > > > - SREG a2, 0(t0)
> > > >
> > > > diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
> > > > b/board/AndesTech/ax25-ae350/ax25-ae350.c
> > > > void *board_fdt_blob_setup(void)
> > > > {
> > > > - void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
> > > > + void **ptr = (void *)&prior_stage_fdt_address;
> > > >
> > > > in the previous pull request.
> > > >
> > > > But Bin do not agree with that I use prior_stage_fdt_address in
> > > > board_fdt_blob_setup( )
> > > > I try to explain why I use it like that way.
> > > > Then Bin have not any reply in the following mail.
> > > > Finally I decide to drop this patch in the next pull request.
> > > >
> > > > Hi Bin
> > > >
> > > > How do you think about I recovery this patch to fix this issue ?
> > >
> > > Actually, previous booting stage can pass location of FDT stored in flash
> > > to U-Boot. U-Boot requires FDT at a DRAM location which it can modify
> > > in-place before passing on to Linux kernel so we should relocate the FDT
> > > passed by previous booting stage to some board specific DRAM location.
> > >
> > > My suggestion is as follows:
> > >
> > > Instead of SDRAM_BASE, we can have new board specific config
> > > CONFIG_RISCV_PRIOR_FDT_BASE
> > >
> > > If CONFIG_RISCV_PRIOR_FDT_BASE is defined/selected by
> > > config then in start.S copy-over the FDT from location pointed by
> > > "a1" register to location pointed by CONFIG_RISCV_PRIOR_FDT_BASE.
> >
>
> Hi Anup
>
> It can not achieve dtb delivery at runtime.
>
> Rick
>
> > I think you can copy-over FDT in C code too. You don't need to do
> > in start.S.
> >
> > >
> > > In your board_fdt_blob_setup(), you can safely do:
> > > void **ptr = (void *)CONFIG_RISCV_PRIOR_FDT_BASE;
> > >
> > > Regards,
> > > Anup
next prev parent reply other threads:[~2018-11-27 6:45 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-26 10:39 [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode Anup Patel
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50B90@ATCPCS16.andestech.com>
2018-11-27 6:40 ` Rick Chen
2018-11-27 6:52 ` Anup Patel
2018-11-27 10:47 ` Alexander Graf
2018-11-27 12:38 ` Anup Patel
2018-11-30 7:05 ` Rick Chen
2018-11-30 8:53 ` Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 3/4] riscv: Add S-mode defconfigs for QEMU virt machine Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S Anup Patel
2018-11-26 15:10 ` Bin Meng
2018-11-26 22:10 ` Auer, Lukas
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50A96@ATCPCS16.andestech.com>
2018-11-27 3:21 ` Rick Chen
2018-11-27 3:28 ` Anup Patel
2018-11-27 5:20 ` Rick Chen
2018-11-27 5:44 ` Anup Patel
2018-11-27 5:47 ` Anup Patel
2018-11-27 6:09 ` Rick Chen
2018-11-27 6:13 ` Anup Patel
2018-11-27 6:31 ` Rick Chen
2018-11-27 6:40 ` Anup Patel
2018-11-27 7:01 ` Rick Chen
2018-11-27 7:56 ` Anup Patel
2018-11-27 8:42 ` Anup Patel
2018-11-27 10:41 ` Alexander Graf
2018-11-29 10:44 ` Rick Chen
2018-11-27 8:43 ` Rick Chen
2018-11-27 10:07 ` Bin Meng
2018-11-29 10:42 ` Rick Chen
2018-11-29 11:29 ` Rick Chen
2018-11-30 1:47 ` Bin Meng
2018-11-30 6:06 ` Rick Chen
2018-11-30 6:21 ` Bin Meng
2018-11-30 6:41 ` Rick Chen
2018-11-30 6:57 ` Bin Meng
2018-11-30 7:16 ` Rick Chen
2018-11-30 7:26 ` Bin Meng
2018-11-30 7:31 ` Rick Chen
2018-11-27 6:45 ` Rick Chen [this message]
2018-11-27 6:56 ` Anup Patel
2018-11-27 10:00 ` Bin Meng
2018-11-27 9:56 ` Bin Meng
2018-11-28 12:22 ` [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
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