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From: Anup Patel <anup@brainfault.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S
Date: Tue, 27 Nov 2018 12:26:32 +0530	[thread overview]
Message-ID: <CAAhSdy0iLYwM-n=r=u3gih3gfjFzPc+2-yzPTHQKdqCJx7oQ5w@mail.gmail.com> (raw)
In-Reply-To: <CAN5B=eKcxx8YTVJEGFX5z1ebZsHbwEADz5_G91TMdX6HghsLfA@mail.gmail.com>

On Tue, Nov 27, 2018 at 12:14 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> > > > > > When we run U-Boot in S-mode the BBL runs from 0x80000000 so this
> > > > > > two lines corrupts BBL instructions.
>
> Hi Anup
>
> You said
> Your patchset based upon git://git.denx.de/u-boot-riscv.git
>
> Why you announce this problem in [PATCH v5 4/4] riscv: Remove
> redundant a2 store on DRAM base in start.S
> Why you do not find this proble in v1, v2, v3, v4 ?

I had this change locally. I thought some would definitely remove this
lines but did not see that happening so I send patch to remove these
lines myself.

Regards,
Anup

  reply	other threads:[~2018-11-27  6:56 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-26 10:39 [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode Anup Patel
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50B90@ATCPCS16.andestech.com>
2018-11-27  6:40     ` Rick Chen
2018-11-27  6:52       ` Anup Patel
2018-11-27 10:47         ` Alexander Graf
2018-11-27 12:38           ` Anup Patel
2018-11-30  7:05             ` Rick Chen
2018-11-30  8:53               ` Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 3/4] riscv: Add S-mode defconfigs for QEMU virt machine Anup Patel
2018-11-26 10:39 ` [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S Anup Patel
2018-11-26 15:10   ` Bin Meng
2018-11-26 22:10     ` Auer, Lukas
     [not found]       ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A50A96@ATCPCS16.andestech.com>
2018-11-27  3:21         ` Rick Chen
2018-11-27  3:28           ` Anup Patel
2018-11-27  5:20             ` Rick Chen
2018-11-27  5:44               ` Anup Patel
2018-11-27  5:47                 ` Anup Patel
2018-11-27  6:09                   ` Rick Chen
2018-11-27  6:13                     ` Anup Patel
2018-11-27  6:31                       ` Rick Chen
2018-11-27  6:40                         ` Anup Patel
2018-11-27  7:01                           ` Rick Chen
2018-11-27  7:56                             ` Anup Patel
2018-11-27  8:42                               ` Anup Patel
2018-11-27 10:41                                 ` Alexander Graf
2018-11-29 10:44                                   ` Rick Chen
2018-11-27  8:43                               ` Rick Chen
2018-11-27 10:07                                 ` Bin Meng
2018-11-29 10:42                                   ` Rick Chen
2018-11-29 11:29                                     ` Rick Chen
2018-11-30  1:47                                     ` Bin Meng
2018-11-30  6:06                                       ` Rick Chen
2018-11-30  6:21                                         ` Bin Meng
2018-11-30  6:41                                           ` Rick Chen
2018-11-30  6:57                                             ` Bin Meng
2018-11-30  7:16                                               ` Rick Chen
2018-11-30  7:26                                                 ` Bin Meng
2018-11-30  7:31                                                   ` Rick Chen
2018-11-27  6:45                     ` Rick Chen
2018-11-27  6:56                       ` Anup Patel [this message]
2018-11-27 10:00               ` Bin Meng
2018-11-27  9:56             ` Bin Meng
2018-11-28 12:22 ` [U-Boot] [PATCH v5 0/4] RISC-V S-mode support Anup Patel

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