From: Paul Walmsley <paul.walmsley@sifive.com> To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley <paul@pwsan.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, devicetree@vger.kernel.org Subject: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Date: Sun, 2 Jun 2019 01:05:00 -0700 [thread overview] Message-ID: <20190602080500.31700-6-paul.walmsley@sifive.com> (raw) In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> Add initial board data for the SiFive HiFive Unleashed A00. Currently the data populated in this DT file describes the board DRAM configuration and the external clock sources that supply the PRCI. This third version incorporates changes based on more comments from Rob Herring <robh+dt@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/riscv/boot/dts/sifive/Makefile | 2 + .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/Makefile create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile new file mode 100644 index 000000000000..baaeef9efdcb --- /dev/null +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-y += hifive-unleashed-a00.dtb diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts new file mode 100644 index 000000000000..1de4ea1577d5 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&qspi0 { + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com> To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Date: Sun, 2 Jun 2019 01:05:00 -0700 [thread overview] Message-ID: <20190602080500.31700-6-paul.walmsley@sifive.com> (raw) In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> Add initial board data for the SiFive HiFive Unleashed A00. Currently the data populated in this DT file describes the board DRAM configuration and the external clock sources that supply the PRCI. This third version incorporates changes based on more comments from Rob Herring <robh+dt@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/riscv/boot/dts/sifive/Makefile | 2 + .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/Makefile create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile new file mode 100644 index 000000000000..baaeef9efdcb --- /dev/null +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-y += hifive-unleashed-a00.dtb diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts new file mode 100644 index 000000000000..1de4ea1577d5 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&qspi0 { + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-06-02 8:05 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-02 8:04 [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-04 14:37 ` Loys Ollivier 2019-06-04 14:37 ` Loys Ollivier 2019-06-07 5:12 ` Paul Walmsley 2019-06-07 5:12 ` Paul Walmsley 2019-06-07 9:49 ` Loys Ollivier 2019-06-07 9:49 ` Loys Ollivier 2019-06-08 17:56 ` Palmer Dabbelt 2019-06-08 17:56 ` Palmer Dabbelt 2019-06-09 5:50 ` Paul Walmsley 2019-06-09 5:50 ` Paul Walmsley 2019-06-09 7:49 ` Christoph Hellwig 2019-06-09 7:49 ` Christoph Hellwig 2019-06-02 8:04 ` [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-10 21:44 ` Rob Herring 2019-06-10 21:44 ` Rob Herring 2019-06-16 18:39 ` Paul Walmsley 2019-06-16 18:39 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-04 14:38 ` Loys Ollivier 2019-06-04 14:38 ` Loys Ollivier 2019-06-02 8:05 ` Paul Walmsley [this message] 2019-06-02 8:05 ` [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley 2019-06-04 14:41 ` Loys Ollivier 2019-06-04 14:41 ` Loys Ollivier 2019-06-09 6:18 ` Antony Pavlov 2019-06-09 6:18 ` Antony Pavlov 2019-06-09 6:18 ` Antony Pavlov 2019-06-16 18:36 ` Paul Walmsley 2019-06-16 18:36 ` Paul Walmsley 2019-06-16 18:36 ` Paul Walmsley 2019-06-04 14:31 ` [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Loys Ollivier 2019-06-04 14:31 ` Loys Ollivier 2019-06-07 5:14 ` Paul Walmsley 2019-06-07 5:14 ` Paul Walmsley 2019-06-05 17:36 ` Kevin Hilman 2019-06-05 17:36 ` Kevin Hilman 2019-06-06 23:15 ` Atish Patra 2019-06-06 23:15 ` Atish Patra 2019-06-07 16:51 ` Kevin Hilman 2019-06-07 16:51 ` Kevin Hilman 2019-06-07 17:58 ` Atish Patra 2019-06-07 17:58 ` Atish Patra 2019-06-07 20:55 ` Auer, Lukas 2019-06-07 20:55 ` Auer, Lukas 2019-06-07 5:18 ` Paul Walmsley 2019-06-07 5:18 ` Paul Walmsley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20190602080500.31700-6-paul.walmsley@sifive.com \ --to=paul.walmsley@sifive.com \ --cc=aou@eecs.berkeley.edu \ --cc=devicetree@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mark.rutland@arm.com \ --cc=palmer@sifive.com \ --cc=paul@pwsan.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.