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From: Loys Ollivier <lollivier@baylibre.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@sifive.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
Date: Tue, 04 Jun 2019 16:41:17 +0200	[thread overview]
Message-ID: <86pnnth0qa.fsf@baylibre.com> (raw)
In-Reply-To: <20190602080500.31700-6-paul.walmsley@sifive.com>

On Sun 02 Jun 2019 at 01:05, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

WARNING: multiple messages have this Message-ID (diff)
From: Loys Ollivier <lollivier@baylibre.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@sifive.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
Date: Tue, 04 Jun 2019 16:41:17 +0200	[thread overview]
Message-ID: <86pnnth0qa.fsf@baylibre.com> (raw)
In-Reply-To: <20190602080500.31700-6-paul.walmsley@sifive.com>

On Sun 02 Jun 2019 at 01:05, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2019-06-04 14:41 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-02  8:04 [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Paul Walmsley
2019-06-02  8:04 ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-04 14:37   ` Loys Ollivier
2019-06-04 14:37     ` Loys Ollivier
2019-06-07  5:12     ` Paul Walmsley
2019-06-07  5:12       ` Paul Walmsley
2019-06-07  9:49       ` Loys Ollivier
2019-06-07  9:49         ` Loys Ollivier
2019-06-08 17:56       ` Palmer Dabbelt
2019-06-08 17:56         ` Palmer Dabbelt
2019-06-09  5:50         ` Paul Walmsley
2019-06-09  5:50           ` Paul Walmsley
2019-06-09  7:49           ` Christoph Hellwig
2019-06-09  7:49             ` Christoph Hellwig
2019-06-02  8:04 ` [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-10 21:44   ` Rob Herring
2019-06-10 21:44     ` Rob Herring
2019-06-16 18:39     ` Paul Walmsley
2019-06-16 18:39       ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-04 14:38   ` Loys Ollivier
2019-06-04 14:38     ` Loys Ollivier
2019-06-02  8:05 ` [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2019-06-02  8:05   ` Paul Walmsley
2019-06-04 14:41   ` Loys Ollivier [this message]
2019-06-04 14:41     ` Loys Ollivier
2019-06-09  6:18   ` Antony Pavlov
2019-06-09  6:18     ` Antony Pavlov
2019-06-09  6:18     ` Antony Pavlov
2019-06-16 18:36     ` Paul Walmsley
2019-06-16 18:36       ` Paul Walmsley
2019-06-16 18:36       ` Paul Walmsley
2019-06-04 14:31 ` [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Loys Ollivier
2019-06-04 14:31   ` Loys Ollivier
2019-06-07  5:14   ` Paul Walmsley
2019-06-07  5:14     ` Paul Walmsley
2019-06-05 17:36 ` Kevin Hilman
2019-06-05 17:36   ` Kevin Hilman
2019-06-06 23:15   ` Atish Patra
2019-06-06 23:15     ` Atish Patra
2019-06-07 16:51     ` Kevin Hilman
2019-06-07 16:51       ` Kevin Hilman
2019-06-07 17:58       ` Atish Patra
2019-06-07 17:58         ` Atish Patra
2019-06-07 20:55         ` Auer, Lukas
2019-06-07 20:55           ` Auer, Lukas
2019-06-07  5:18   ` Paul Walmsley
2019-06-07  5:18     ` Paul Walmsley

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