From: Loys Ollivier <lollivier@baylibre.com> To: Paul Walmsley <paul.walmsley@sifive.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Date: Tue, 04 Jun 2019 16:31:32 +0200 [thread overview] Message-ID: <86y32hh16j.fsf@baylibre.com> (raw) In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote: > Add support for building flattened DT files from DT source files under > arch/riscv/boot/dts. Follow existing kernel precedent from other SoC > architectures. Start our board support by adding initial support for > the SiFive FU540 SoC and the first development board that uses it, the > SiFive HiFive Unleashed A00. > > This third version of the patch set adds I2C data for the chip, > incorporates all remaining changes that riscv-pk was making > automatically, and addresses a comment from Rob Herring > <robh@kernel.org>. > > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the > BBL and open-source FSBL, with modifications to pass in the DTB > file generated by these patches. > > This patch series can be found, along with the PRCI patch set > and the DT macro prerequisite patch, at: > > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1 > > > - Paul > Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed. Tested-by: Loys Ollivier <lollivier@baylibre.com> > > Paul Walmsley (5): > arch: riscv: add support for building DTB files from DT source data > dt-bindings: riscv: sifive: add YAML documentation for the SiFive > FU540 > dt-bindings: riscv: convert cpu binding to json-schema > riscv: dts: add initial support for the SiFive FU540-C000 SoC > riscv: dts: add initial board data for the SiFive HiFive Unleashed > > .../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++ > .../devicetree/bindings/riscv/sifive.yaml | 25 ++ > MAINTAINERS | 9 + > arch/riscv/boot/dts/Makefile | 2 + > arch/riscv/boot/dts/sifive/Makefile | 2 + > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++ > .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++ > 7 files changed, 488 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml > create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml > create mode 100644 arch/riscv/boot/dts/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts Note: the -fu540 was dropped from the previous version which results in a different dtb file. Loys
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From: Loys Ollivier <lollivier@baylibre.com> To: Paul Walmsley <paul.walmsley@sifive.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Date: Tue, 04 Jun 2019 16:31:32 +0200 [thread overview] Message-ID: <86y32hh16j.fsf@baylibre.com> (raw) In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote: > Add support for building flattened DT files from DT source files under > arch/riscv/boot/dts. Follow existing kernel precedent from other SoC > architectures. Start our board support by adding initial support for > the SiFive FU540 SoC and the first development board that uses it, the > SiFive HiFive Unleashed A00. > > This third version of the patch set adds I2C data for the chip, > incorporates all remaining changes that riscv-pk was making > automatically, and addresses a comment from Rob Herring > <robh@kernel.org>. > > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the > BBL and open-source FSBL, with modifications to pass in the DTB > file generated by these patches. > > This patch series can be found, along with the PRCI patch set > and the DT macro prerequisite patch, at: > > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1 > > > - Paul > Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed. Tested-by: Loys Ollivier <lollivier@baylibre.com> > > Paul Walmsley (5): > arch: riscv: add support for building DTB files from DT source data > dt-bindings: riscv: sifive: add YAML documentation for the SiFive > FU540 > dt-bindings: riscv: convert cpu binding to json-schema > riscv: dts: add initial support for the SiFive FU540-C000 SoC > riscv: dts: add initial board data for the SiFive HiFive Unleashed > > .../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++ > .../devicetree/bindings/riscv/sifive.yaml | 25 ++ > MAINTAINERS | 9 + > arch/riscv/boot/dts/Makefile | 2 + > arch/riscv/boot/dts/sifive/Makefile | 2 + > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++ > .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++ > 7 files changed, 488 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml > create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml > create mode 100644 arch/riscv/boot/dts/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts Note: the -fu540 was dropped from the previous version which results in a different dtb file. Loys _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-06-04 14:31 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-02 8:04 [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-04 14:37 ` Loys Ollivier 2019-06-04 14:37 ` Loys Ollivier 2019-06-07 5:12 ` Paul Walmsley 2019-06-07 5:12 ` Paul Walmsley 2019-06-07 9:49 ` Loys Ollivier 2019-06-07 9:49 ` Loys Ollivier 2019-06-08 17:56 ` Palmer Dabbelt 2019-06-08 17:56 ` Palmer Dabbelt 2019-06-09 5:50 ` Paul Walmsley 2019-06-09 5:50 ` Paul Walmsley 2019-06-09 7:49 ` Christoph Hellwig 2019-06-09 7:49 ` Christoph Hellwig 2019-06-02 8:04 ` [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-10 21:44 ` Rob Herring 2019-06-10 21:44 ` Rob Herring 2019-06-16 18:39 ` Paul Walmsley 2019-06-16 18:39 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-02 8:04 ` [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley 2019-06-02 8:04 ` Paul Walmsley 2019-06-04 14:38 ` Loys Ollivier 2019-06-04 14:38 ` Loys Ollivier 2019-06-02 8:05 ` [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley 2019-06-02 8:05 ` Paul Walmsley 2019-06-04 14:41 ` Loys Ollivier 2019-06-04 14:41 ` Loys Ollivier 2019-06-09 6:18 ` Antony Pavlov 2019-06-09 6:18 ` Antony Pavlov 2019-06-09 6:18 ` Antony Pavlov 2019-06-16 18:36 ` Paul Walmsley 2019-06-16 18:36 ` Paul Walmsley 2019-06-16 18:36 ` Paul Walmsley 2019-06-04 14:31 ` Loys Ollivier [this message] 2019-06-04 14:31 ` [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Loys Ollivier 2019-06-07 5:14 ` Paul Walmsley 2019-06-07 5:14 ` Paul Walmsley 2019-06-05 17:36 ` Kevin Hilman 2019-06-05 17:36 ` Kevin Hilman 2019-06-06 23:15 ` Atish Patra 2019-06-06 23:15 ` Atish Patra 2019-06-07 16:51 ` Kevin Hilman 2019-06-07 16:51 ` Kevin Hilman 2019-06-07 17:58 ` Atish Patra 2019-06-07 17:58 ` Atish Patra 2019-06-07 20:55 ` Auer, Lukas 2019-06-07 20:55 ` Auer, Lukas 2019-06-07 5:18 ` Paul Walmsley 2019-06-07 5:18 ` Paul Walmsley
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