* [PATCH 01/28] drm/i915: Add modular FIA
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 15:50 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
` (30 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit. If Modular FIA is
used in the SOC, this register bit exists in all the instances of
Modular FIA. IOM FW is required to program only the MF bit in
first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++---
drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.h | 6 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 13 +++++++---
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
7 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7925a176f900..b717562fcce5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2997,6 +2997,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
enum port port = intel_dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
u32 ln0, ln1, lane_info;
+ enum display_fia fia;
if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
return;
@@ -3009,7 +3010,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
- lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
+ fia = intel_tc_port_to_fia(dev_priv, tc_port);
+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
DP_LANE_ASSIGNMENT_SHIFT(tc_port);
@@ -3598,7 +3600,8 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
+ enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
+ u32 val = I915_READ(PORT_TX_DFLEXDPMLE1(fia));
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
@@ -3617,7 +3620,7 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
default:
MISSING_CASE(pipe_config->lane_count);
}
- I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
+ I915_WRITE(PORT_TX_DFLEXDPMLE1(fia), val);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8592a7d422de..6217b5bcea2a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6590,6 +6590,33 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
return port - PORT_C;
}
+static bool intel_has_modular_fia(struct drm_i915_private *dev_priv)
+{
+ if (!INTEL_INFO(dev_priv)->display.has_modular_fia)
+ return false;
+
+ return I915_READ(PORT_TX_DFLEXDPSP(FIA_1)) & MODULAR_FIA_MASK;
+}
+
+enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
+ enum tc_port tc_port)
+{
+ if (!intel_has_modular_fia(dev_priv))
+ return FIA_1;
+
+ switch (tc_port) {
+ case PORT_TC1:
+ case PORT_TC2:
+ return FIA_1;
+ case PORT_TC3:
+ case PORT_TC4:
+ return FIA_2;
+ default:
+ WARN_ON(tc_port);
+ return FIA_1;
+ }
+}
+
enum intel_display_power_domain intel_port_to_power_domain(enum port port)
{
switch (port) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ee6b8194a459..12ded01ed5d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -196,6 +196,12 @@ enum tc_port_type {
TC_PORT_LEGACY,
};
+enum display_fia {
+ FIA_1 = 0,
+ FIA_2,
+ FIA_3,
+};
+
enum dpio_channel {
DPIO_CH0,
DPIO_CH1
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4336df46fe78..5ed6e49fef33 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -218,13 +218,15 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
intel_wakeref_t wakeref;
u32 lane_info;
+ enum display_fia fia;
if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
return 4;
+ fia = intel_tc_port_to_fia(dev_priv, tc_port);
lane_info = 0;
with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
- lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
DP_LANE_ASSIGNMENT_SHIFT(tc_port);
@@ -5300,12 +5302,14 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
{
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
u32 val;
+ enum display_fia fia;
if (dig_port->tc_type != TC_PORT_LEGACY &&
dig_port->tc_type != TC_PORT_TYPEC)
return true;
- val = I915_READ(PORT_TX_DFLEXDPPMS);
+ fia = intel_tc_port_to_fia(dev_priv, tc_port);
+ val = I915_READ(PORT_TX_DFLEXDPPMS(fia));
if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
WARN_ON(dig_port->tc_legacy_port);
@@ -5316,10 +5320,10 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
* This function may be called many times in a row without an HPD event
* in between, so try to avoid the write when we can.
*/
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
}
/*
@@ -5327,7 +5331,7 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
* became disconnected. Not necessary for legacy mode.
*/
if (dig_port->tc_type == TC_PORT_TYPEC &&
- !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
+ !(I915_READ(PORT_TX_DFLEXDPSP(fia)) & TC_LIVE_STATE_TC(tc_port))) {
DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
icl_tc_phy_disconnect(dev_priv, dig_port);
return false;
@@ -5344,10 +5348,13 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
struct intel_digital_port *dig_port)
{
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ enum display_fia fia;
if (dig_port->tc_type == TC_PORT_UNKNOWN)
return;
+ fia = intel_tc_port_to_fia(dev_priv, tc_port);
+
/*
* TBT disconnection flow is read the live status, what was done in
* caller.
@@ -5356,9 +5363,9 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
dig_port->tc_type == TC_PORT_LEGACY) {
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
}
DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
@@ -5383,6 +5390,7 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
{
enum port port = intel_dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
bool is_legacy, is_typec, is_tbt;
u32 dpsp;
@@ -5402,7 +5410,8 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
* The spec says we shouldn't be using the ISR bits for detecting
* between TC and TBT. We should use DFLEXDPSP.
*/
- dpsp = I915_READ(PORT_TX_DFLEXDPSP);
+
+ dpsp = I915_READ(PORT_TX_DFLEXDPSP(fia));
is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..8047f1bed314 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2201,9 +2201,13 @@ enum i915_power_well_id {
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
#define FIA1_BASE 0x163000
+#define FIA2_BASE 0x16E000
+#define FIA3_BASE 0x16F000
+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
@@ -11461,17 +11465,18 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
+#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
+#define MODULAR_FIA_MASK (1 << 4)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
+#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
+#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..e9dc86ed517b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -136,6 +136,7 @@ enum intel_ppgtt_type {
func(has_gmch); \
func(has_hotplug); \
func(has_ipc); \
+ func(has_modular_fia); \
func(has_overlay); \
func(has_psr); \
func(overlay_needs_physical); \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..e30cb4be4997 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1477,6 +1477,8 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
+enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
+ enum tc_port tc_port);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 01/28] drm/i915: Add modular FIA
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
@ 2019-06-26 15:50 ` Ville Syrjälä
2019-06-26 17:48 ` Lucas De Marchi
0 siblings, 1 reply; 61+ messages in thread
From: Ville Syrjälä @ 2019-06-26 15:50 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:10AM -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular FIA instance has its own IOSF Sideband Port ID
> and it houses only 2 Type-C Port. In SOC that has more than
> two Type-C Ports, there are multiple instances of Modular FIA.
> Gunit will need to use different destination ID when it access
> different pair of Type-C Port.
>
> The DFLEXDPSP register has Modular FIA bit. If Modular FIA is
> used in the SOC, this register bit exists in all the instances of
> Modular FIA. IOM FW is required to program only the MF bit in
> first FIA instance that houses the Type-C Port 0 and Port 1, for
> Display Driver to read from.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++---
> drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.h | 6 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++---
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 7 files changed, 68 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7925a176f900..b717562fcce5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2997,6 +2997,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
> enum port port = intel_dig_port->base.port;
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> u32 ln0, ln1, lane_info;
> + enum display_fia fia;
Can we stick this into the new enum phy namespace we're going to need
anyway for ehl?
>
> if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
> return;
> @@ -3009,7 +3010,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
> ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>
> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>
> @@ -3598,7 +3600,8 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1(fia));
> bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> @@ -3617,7 +3620,7 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> default:
> MISSING_CASE(pipe_config->lane_count);
> }
> - I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> + I915_WRITE(PORT_TX_DFLEXDPMLE1(fia), val);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8592a7d422de..6217b5bcea2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6590,6 +6590,33 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> return port - PORT_C;
> }
>
> +static bool intel_has_modular_fia(struct drm_i915_private *dev_priv)
> +{
> + if (!INTEL_INFO(dev_priv)->display.has_modular_fia)
> + return false;
> +
> + return I915_READ(PORT_TX_DFLEXDPSP(FIA_1)) & MODULAR_FIA_MASK;
> +}
> +
> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
> + enum tc_port tc_port)
> +{
> + if (!intel_has_modular_fia(dev_priv))
> + return FIA_1;
> +
> + switch (tc_port) {
> + case PORT_TC1:
> + case PORT_TC2:
> + return FIA_1;
> + case PORT_TC3:
> + case PORT_TC4:
> + return FIA_2;
> + default:
> + WARN_ON(tc_port);
> + return FIA_1;
> + }
> +}
> +
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> {
> switch (port) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index ee6b8194a459..12ded01ed5d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -196,6 +196,12 @@ enum tc_port_type {
> TC_PORT_LEGACY,
> };
>
> +enum display_fia {
> + FIA_1 = 0,
> + FIA_2,
> + FIA_3,
> +};
> +
> enum dpio_channel {
> DPIO_CH0,
> DPIO_CH1
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4336df46fe78..5ed6e49fef33 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -218,13 +218,15 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> intel_wakeref_t wakeref;
> u32 lane_info;
> + enum display_fia fia;
>
> if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
> return 4;
>
> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> lane_info = 0;
> with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>
> @@ -5300,12 +5302,14 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> {
> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> u32 val;
> + enum display_fia fia;
>
> if (dig_port->tc_type != TC_PORT_LEGACY &&
> dig_port->tc_type != TC_PORT_TYPEC)
> return true;
>
> - val = I915_READ(PORT_TX_DFLEXDPPMS);
> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> + val = I915_READ(PORT_TX_DFLEXDPPMS(fia));
> if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
> DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
> WARN_ON(dig_port->tc_legacy_port);
> @@ -5316,10 +5320,10 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> * This function may be called many times in a row without an HPD event
> * in between, so try to avoid the write when we can.
> */
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
> if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
> }
>
> /*
> @@ -5327,7 +5331,7 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> * became disconnected. Not necessary for legacy mode.
> */
> if (dig_port->tc_type == TC_PORT_TYPEC &&
> - !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
> + !(I915_READ(PORT_TX_DFLEXDPSP(fia)) & TC_LIVE_STATE_TC(tc_port))) {
> DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
> icl_tc_phy_disconnect(dev_priv, dig_port);
> return false;
> @@ -5344,10 +5348,13 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
> struct intel_digital_port *dig_port)
> {
> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + enum display_fia fia;
>
> if (dig_port->tc_type == TC_PORT_UNKNOWN)
> return;
>
> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> +
> /*
> * TBT disconnection flow is read the live status, what was done in
> * caller.
> @@ -5356,9 +5363,9 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
> dig_port->tc_type == TC_PORT_LEGACY) {
> u32 val;
>
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
> val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
> }
>
> DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
> @@ -5383,6 +5390,7 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> {
> enum port port = intel_dig_port->base.port;
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
> bool is_legacy, is_typec, is_tbt;
> u32 dpsp;
>
> @@ -5402,7 +5410,8 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> * The spec says we shouldn't be using the ISR bits for detecting
> * between TC and TBT. We should use DFLEXDPSP.
> */
> - dpsp = I915_READ(PORT_TX_DFLEXDPSP);
> +
> + dpsp = I915_READ(PORT_TX_DFLEXDPSP(fia));
> is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
> is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e6009cefb18..8047f1bed314 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2201,9 +2201,13 @@ enum i915_power_well_id {
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> #define FIA1_BASE 0x163000
> +#define FIA2_BASE 0x16E000
> +#define FIA3_BASE 0x16F000
> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
>
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> @@ -11461,17 +11465,18 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
> +#define MODULAR_FIA_MASK (1 << 4)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index ddafc819bf30..e9dc86ed517b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
> func(has_gmch); \
> func(has_hotplug); \
> func(has_ipc); \
> + func(has_modular_fia); \
> func(has_overlay); \
> func(has_psr); \
> func(overlay_needs_physical); \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1d58f7ec5d84..e30cb4be4997 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1477,6 +1477,8 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
> + enum tc_port tc_port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 01/28] drm/i915: Add modular FIA
2019-06-26 15:50 ` Ville Syrjälä
@ 2019-06-26 17:48 ` Lucas De Marchi
2019-06-26 17:56 ` Ville Syrjälä
0 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-26 17:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jun 26, 2019 at 06:50:14PM +0300, Ville Syrjälä wrote:
>On Tue, Jun 25, 2019 at 10:54:10AM -0700, Lucas De Marchi wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
>> then Display Driver will access the additional instances of
>> FIA based on pre-assigned offset in GTTMADDR space.
>>
>> Each Modular FIA instance has its own IOSF Sideband Port ID
>> and it houses only 2 Type-C Port. In SOC that has more than
>> two Type-C Ports, there are multiple instances of Modular FIA.
>> Gunit will need to use different destination ID when it access
>> different pair of Type-C Port.
>>
>> The DFLEXDPSP register has Modular FIA bit. If Modular FIA is
>> used in the SOC, this register bit exists in all the instances of
>> Modular FIA. IOM FW is required to program only the MF bit in
>> first FIA instance that houses the Type-C Port 0 and Port 1, for
>> Display Driver to read from.
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++---
>> drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_display.h | 6 +++++
>> drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++------
>> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++---
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 7 files changed, 68 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 7925a176f900..b717562fcce5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2997,6 +2997,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>> enum port port = intel_dig_port->base.port;
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>> u32 ln0, ln1, lane_info;
>> + enum display_fia fia;
>
>Can we stick this into the new enum phy namespace we're going to need
>anyway for ehl?
each modular FIA maps up to 2 phys (as opposed to ICL's FIA that has 4
phys). I don't think it should be in the same enum namespace.
Yes, with patch
"drm/i915/gen11: Start distinguishing 'phy' from 'port'" merged we
should rather do the phy -> fia mapping here and it could be as simple
as `phy / 2`.
I would rather merge this as is and convert it when that patch is
applied. Also, that series is still missing the conversion for TC since
EHL has only combo phys. This one is about TC.
Once that series is merged and also the pending one from Imre to
separate the TC handling, I can rework this.
Lucas De Marchi
>
>>
>> if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
>> return;
>> @@ -3009,7 +3010,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>> ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>> ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>>
>> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
>> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>>
>> @@ -3598,7 +3600,8 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>> - u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
>> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1(fia));
>> bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>>
>> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>> @@ -3617,7 +3620,7 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
>> default:
>> MISSING_CASE(pipe_config->lane_count);
>> }
>> - I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
>> + I915_WRITE(PORT_TX_DFLEXDPMLE1(fia), val);
>> }
>>
>> static void
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 8592a7d422de..6217b5bcea2a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -6590,6 +6590,33 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>> return port - PORT_C;
>> }
>>
>> +static bool intel_has_modular_fia(struct drm_i915_private *dev_priv)
>> +{
>> + if (!INTEL_INFO(dev_priv)->display.has_modular_fia)
>> + return false;
>> +
>> + return I915_READ(PORT_TX_DFLEXDPSP(FIA_1)) & MODULAR_FIA_MASK;
>> +}
>> +
>> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
>> + enum tc_port tc_port)
>> +{
>> + if (!intel_has_modular_fia(dev_priv))
>> + return FIA_1;
>> +
>> + switch (tc_port) {
>> + case PORT_TC1:
>> + case PORT_TC2:
>> + return FIA_1;
>> + case PORT_TC3:
>> + case PORT_TC4:
>> + return FIA_2;
>> + default:
>> + WARN_ON(tc_port);
>> + return FIA_1;
>> + }
>> +}
>> +
>> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>> {
>> switch (port) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index ee6b8194a459..12ded01ed5d3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -196,6 +196,12 @@ enum tc_port_type {
>> TC_PORT_LEGACY,
>> };
>>
>> +enum display_fia {
>> + FIA_1 = 0,
>> + FIA_2,
>> + FIA_3,
>> +};
>> +
>> enum dpio_channel {
>> DPIO_CH0,
>> DPIO_CH1
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4336df46fe78..5ed6e49fef33 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -218,13 +218,15 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>> intel_wakeref_t wakeref;
>> u32 lane_info;
>> + enum display_fia fia;
>>
>> if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
>> return 4;
>>
>> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> lane_info = 0;
>> with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
>> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>>
>> @@ -5300,12 +5302,14 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
>> {
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>> u32 val;
>> + enum display_fia fia;
>>
>> if (dig_port->tc_type != TC_PORT_LEGACY &&
>> dig_port->tc_type != TC_PORT_TYPEC)
>> return true;
>>
>> - val = I915_READ(PORT_TX_DFLEXDPPMS);
>> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> + val = I915_READ(PORT_TX_DFLEXDPPMS(fia));
>> if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
>> DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
>> WARN_ON(dig_port->tc_legacy_port);
>> @@ -5316,10 +5320,10 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
>> * This function may be called many times in a row without an HPD event
>> * in between, so try to avoid the write when we can.
>> */
>> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
>> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
>> if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
>> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
>> }
>>
>> /*
>> @@ -5327,7 +5331,7 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
>> * became disconnected. Not necessary for legacy mode.
>> */
>> if (dig_port->tc_type == TC_PORT_TYPEC &&
>> - !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
>> + !(I915_READ(PORT_TX_DFLEXDPSP(fia)) & TC_LIVE_STATE_TC(tc_port))) {
>> DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
>> icl_tc_phy_disconnect(dev_priv, dig_port);
>> return false;
>> @@ -5344,10 +5348,13 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
>> struct intel_digital_port *dig_port)
>> {
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>> + enum display_fia fia;
>>
>> if (dig_port->tc_type == TC_PORT_UNKNOWN)
>> return;
>>
>> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> +
>> /*
>> * TBT disconnection flow is read the live status, what was done in
>> * caller.
>> @@ -5356,9 +5363,9 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
>> dig_port->tc_type == TC_PORT_LEGACY) {
>> u32 val;
>>
>> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
>> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
>> val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
>> }
>>
>> DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
>> @@ -5383,6 +5390,7 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
>> {
>> enum port port = intel_dig_port->base.port;
>> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
>> bool is_legacy, is_typec, is_tbt;
>> u32 dpsp;
>>
>> @@ -5402,7 +5410,8 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
>> * The spec says we shouldn't be using the ISR bits for detecting
>> * between TC and TBT. We should use DFLEXDPSP.
>> */
>> - dpsp = I915_READ(PORT_TX_DFLEXDPSP);
>> +
>> + dpsp = I915_READ(PORT_TX_DFLEXDPSP(fia));
>> is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
>> is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7e6009cefb18..8047f1bed314 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2201,9 +2201,13 @@ enum i915_power_well_id {
>> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>>
>> #define FIA1_BASE 0x163000
>> +#define FIA2_BASE 0x16E000
>> +#define FIA3_BASE 0x16F000
>> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
>> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
>>
>> /* ICL PHY DFLEX registers */
>> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
>> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
>> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
>> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
>> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
>> @@ -11461,17 +11465,18 @@ enum skl_power_gate {
>> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>>
>> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
>> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
>> +#define MODULAR_FIA_MASK (1 << 4)
>> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
>> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
>> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>>
>> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
>> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
>> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>>
>> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
>> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
>> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>>
>> #endif /* _I915_REG_H_ */
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index ddafc819bf30..e9dc86ed517b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>> func(has_gmch); \
>> func(has_hotplug); \
>> func(has_ipc); \
>> + func(has_modular_fia); \
>> func(has_overlay); \
>> func(has_psr); \
>> func(overlay_needs_physical); \
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 1d58f7ec5d84..e30cb4be4997 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1477,6 +1477,8 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>> enum port port);
>> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
>> + enum tc_port tc_port);
>> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
>> struct drm_file *file_priv);
>> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 01/28] drm/i915: Add modular FIA
2019-06-26 17:48 ` Lucas De Marchi
@ 2019-06-26 17:56 ` Ville Syrjälä
0 siblings, 0 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-06-26 17:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Jun 26, 2019 at 10:48:01AM -0700, Lucas De Marchi wrote:
> On Wed, Jun 26, 2019 at 06:50:14PM +0300, Ville Syrjälä wrote:
> >On Tue, Jun 25, 2019 at 10:54:10AM -0700, Lucas De Marchi wrote:
> >> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >>
> >> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> >> then Display Driver will access the additional instances of
> >> FIA based on pre-assigned offset in GTTMADDR space.
> >>
> >> Each Modular FIA instance has its own IOSF Sideband Port ID
> >> and it houses only 2 Type-C Port. In SOC that has more than
> >> two Type-C Ports, there are multiple instances of Modular FIA.
> >> Gunit will need to use different destination ID when it access
> >> different pair of Type-C Port.
> >>
> >> The DFLEXDPSP register has Modular FIA bit. If Modular FIA is
> >> used in the SOC, this register bit exists in all the instances of
> >> Modular FIA. IOM FW is required to program only the MF bit in
> >> first FIA instance that houses the Type-C Port 0 and Port 1, for
> >> Display Driver to read from.
> >>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++---
> >> drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++++++
> >> drivers/gpu/drm/i915/display/intel_display.h | 6 +++++
> >> drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++------
> >> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++---
> >> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> >> 7 files changed, 68 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 7925a176f900..b717562fcce5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -2997,6 +2997,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
> >> enum port port = intel_dig_port->base.port;
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> >> u32 ln0, ln1, lane_info;
> >> + enum display_fia fia;
> >
> >Can we stick this into the new enum phy namespace we're going to need
> >anyway for ehl?
>
> each modular FIA maps up to 2 phys (as opposed to ICL's FIA that has 4
> phys). I don't think it should be in the same enum namespace.
Hmm. I'm thinking I'll probably do that for vlv/chv where each PHY
has two channels. So kinda the same thing there. But hard to really
judge before trying I guess.
>
> Yes, with patch
> "drm/i915/gen11: Start distinguishing 'phy' from 'port'" merged we
> should rather do the phy -> fia mapping here and it could be as simple
> as `phy / 2`.
>
> I would rather merge this as is and convert it when that patch is
> applied. Also, that series is still missing the conversion for TC since
> EHL has only combo phys. This one is about TC.
>
> Once that series is merged and also the pending one from Imre to
> separate the TC handling, I can rework this.
>
>
> Lucas De Marchi
>
> >
> >>
> >> if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
> >> return;
> >> @@ -3009,7 +3010,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
> >> ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> >> ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> >>
> >> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> >> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
> >> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> >> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> >>
> >> @@ -3598,7 +3600,8 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> >> - u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> >> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1(fia));
> >> bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> >>
> >> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> >> @@ -3617,7 +3620,7 @@ static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> >> default:
> >> MISSING_CASE(pipe_config->lane_count);
> >> }
> >> - I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> >> + I915_WRITE(PORT_TX_DFLEXDPMLE1(fia), val);
> >> }
> >>
> >> static void
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 8592a7d422de..6217b5bcea2a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -6590,6 +6590,33 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> >> return port - PORT_C;
> >> }
> >>
> >> +static bool intel_has_modular_fia(struct drm_i915_private *dev_priv)
> >> +{
> >> + if (!INTEL_INFO(dev_priv)->display.has_modular_fia)
> >> + return false;
> >> +
> >> + return I915_READ(PORT_TX_DFLEXDPSP(FIA_1)) & MODULAR_FIA_MASK;
> >> +}
> >> +
> >> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
> >> + enum tc_port tc_port)
> >> +{
> >> + if (!intel_has_modular_fia(dev_priv))
> >> + return FIA_1;
> >> +
> >> + switch (tc_port) {
> >> + case PORT_TC1:
> >> + case PORT_TC2:
> >> + return FIA_1;
> >> + case PORT_TC3:
> >> + case PORT_TC4:
> >> + return FIA_2;
> >> + default:
> >> + WARN_ON(tc_port);
> >> + return FIA_1;
> >> + }
> >> +}
> >> +
> >> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> >> {
> >> switch (port) {
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> index ee6b8194a459..12ded01ed5d3 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> @@ -196,6 +196,12 @@ enum tc_port_type {
> >> TC_PORT_LEGACY,
> >> };
> >>
> >> +enum display_fia {
> >> + FIA_1 = 0,
> >> + FIA_2,
> >> + FIA_3,
> >> +};
> >> +
> >> enum dpio_channel {
> >> DPIO_CH0,
> >> DPIO_CH1
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 4336df46fe78..5ed6e49fef33 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -218,13 +218,15 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> >> intel_wakeref_t wakeref;
> >> u32 lane_info;
> >> + enum display_fia fia;
> >>
> >> if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
> >> return 4;
> >>
> >> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> lane_info = 0;
> >> with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> >> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> >> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP(fia)) &
> >> DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> >> DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> >>
> >> @@ -5300,12 +5302,14 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> >> {
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> >> u32 val;
> >> + enum display_fia fia;
> >>
> >> if (dig_port->tc_type != TC_PORT_LEGACY &&
> >> dig_port->tc_type != TC_PORT_TYPEC)
> >> return true;
> >>
> >> - val = I915_READ(PORT_TX_DFLEXDPPMS);
> >> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> + val = I915_READ(PORT_TX_DFLEXDPPMS(fia));
> >> if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
> >> DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
> >> WARN_ON(dig_port->tc_legacy_port);
> >> @@ -5316,10 +5320,10 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> >> * This function may be called many times in a row without an HPD event
> >> * in between, so try to avoid the write when we can.
> >> */
> >> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> >> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
> >> if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> >> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> >> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> >> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
> >> }
> >>
> >> /*
> >> @@ -5327,7 +5331,7 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
> >> * became disconnected. Not necessary for legacy mode.
> >> */
> >> if (dig_port->tc_type == TC_PORT_TYPEC &&
> >> - !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
> >> + !(I915_READ(PORT_TX_DFLEXDPSP(fia)) & TC_LIVE_STATE_TC(tc_port))) {
> >> DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
> >> icl_tc_phy_disconnect(dev_priv, dig_port);
> >> return false;
> >> @@ -5344,10 +5348,13 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
> >> struct intel_digital_port *dig_port)
> >> {
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> >> + enum display_fia fia;
> >>
> >> if (dig_port->tc_type == TC_PORT_UNKNOWN)
> >> return;
> >>
> >> + fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> +
> >> /*
> >> * TBT disconnection flow is read the live status, what was done in
> >> * caller.
> >> @@ -5356,9 +5363,9 @@ void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
> >> dig_port->tc_type == TC_PORT_LEGACY) {
> >> u32 val;
> >>
> >> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> >> + val = I915_READ(PORT_TX_DFLEXDPCSSS(fia));
> >> val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> >> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> >> + I915_WRITE(PORT_TX_DFLEXDPCSSS(fia), val);
> >> }
> >>
> >> DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
> >> @@ -5383,6 +5390,7 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> >> {
> >> enum port port = intel_dig_port->base.port;
> >> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> >> + enum display_fia fia = intel_tc_port_to_fia(dev_priv, tc_port);
> >> bool is_legacy, is_typec, is_tbt;
> >> u32 dpsp;
> >>
> >> @@ -5402,7 +5410,8 @@ static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
> >> * The spec says we shouldn't be using the ISR bits for detecting
> >> * between TC and TBT. We should use DFLEXDPSP.
> >> */
> >> - dpsp = I915_READ(PORT_TX_DFLEXDPSP);
> >> +
> >> + dpsp = I915_READ(PORT_TX_DFLEXDPSP(fia));
> >> is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
> >> is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 7e6009cefb18..8047f1bed314 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2201,9 +2201,13 @@ enum i915_power_well_id {
> >> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
> >>
> >> #define FIA1_BASE 0x163000
> >> +#define FIA2_BASE 0x16E000
> >> +#define FIA3_BASE 0x16F000
> >> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> >> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
> >>
> >> /* ICL PHY DFLEX registers */
> >> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
> >> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> >> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> >> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> >> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> >> @@ -11461,17 +11465,18 @@ enum skl_power_gate {
> >> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> >> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> >>
> >> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
> >> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
> >> +#define MODULAR_FIA_MASK (1 << 4)
> >> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> >> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> >> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> >> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> >> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
> >>
> >> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
> >> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
> >> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
> >>
> >> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
> >> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> >> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
> >>
> >> #endif /* _I915_REG_H_ */
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index ddafc819bf30..e9dc86ed517b 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
> >> func(has_gmch); \
> >> func(has_hotplug); \
> >> func(has_ipc); \
> >> + func(has_modular_fia); \
> >> func(has_overlay); \
> >> func(has_psr); \
> >> func(overlay_needs_physical); \
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> index 1d58f7ec5d84..e30cb4be4997 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -1477,6 +1477,8 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> >> enum port port);
> >> +enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
> >> + enum tc_port tc_port);
> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> >> struct drm_file *file_priv);
> >> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> >> --
> >> 2.21.0
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 02/28] drm/i915: rework reading pipe disable fuses
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 15:51 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
` (29 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
This prepares to have possibly more than 3 pipes. I didn't want to
continue the previous approach since the check for "are the disabled
pipes the last ones" poses a combinatory explosion. We need that check
because in several places of the code we have that assumption. If that
ever becomes false in a new HW, other parts of the code would have to
change.
Now we start by considering we have info->num_pipes enabled and disable
each pipe that is marked as disabled. Then it's a simple matter of
checking if we have at least one pipe and that all the enabled ones are
the first pipes, i.e. there are no holes in the bitmask.
Cc: Jose Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 36 +++++++++---------------
1 file changed, 13 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7135d8dc32a7..e64536e1fd1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -929,35 +929,25 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
}
} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
u32 dfsm = I915_READ(SKL_DFSM);
- u8 disabled_mask = 0;
- bool invalid;
- int num_bits;
+ u8 enabled_mask = BIT(info->num_pipes) - 1;
if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
- disabled_mask |= BIT(PIPE_A);
+ enabled_mask &= ~BIT(PIPE_A);
if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
- disabled_mask |= BIT(PIPE_B);
+ enabled_mask &= ~BIT(PIPE_B);
if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
- disabled_mask |= BIT(PIPE_C);
-
- num_bits = hweight8(disabled_mask);
-
- switch (disabled_mask) {
- case BIT(PIPE_A):
- case BIT(PIPE_B):
- case BIT(PIPE_A) | BIT(PIPE_B):
- case BIT(PIPE_A) | BIT(PIPE_C):
- invalid = true;
- break;
- default:
- invalid = false;
- }
+ enabled_mask &= ~BIT(PIPE_C);
- if (num_bits > info->num_pipes || invalid)
- DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
- disabled_mask);
+ /*
+ * At least one pipe should be enabled and if there are
+ * disabled pipes, they should be the last ones, with no holes
+ * in the mask.
+ */
+ if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
+ DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
+ enabled_mask);
else
- info->num_pipes -= num_bits;
+ info->num_pipes = hweight8(enabled_mask);
}
/* Initialize slice/subslice/EU info */
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 02/28] drm/i915: rework reading pipe disable fuses
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
@ 2019-06-26 15:51 ` Ville Syrjälä
0 siblings, 0 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-06-26 15:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:11AM -0700, Lucas De Marchi wrote:
> This prepares to have possibly more than 3 pipes. I didn't want to
> continue the previous approach since the check for "are the disabled
> pipes the last ones" poses a combinatory explosion. We need that check
> because in several places of the code we have that assumption. If that
> ever becomes false in a new HW, other parts of the code would have to
> change.
>
> Now we start by considering we have info->num_pipes enabled and disable
> each pipe that is marked as disabled. Then it's a simple matter of
> checking if we have at least one pipe and that all the enabled ones are
> the first pipes, i.e. there are no holes in the bitmask.
>
> Cc: Jose Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 36 +++++++++---------------
> 1 file changed, 13 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7135d8dc32a7..e64536e1fd1b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -929,35 +929,25 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> }
> } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
> u32 dfsm = I915_READ(SKL_DFSM);
> - u8 disabled_mask = 0;
> - bool invalid;
> - int num_bits;
> + u8 enabled_mask = BIT(info->num_pipes) - 1;
>
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> - disabled_mask |= BIT(PIPE_A);
> + enabled_mask &= ~BIT(PIPE_A);
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> - disabled_mask |= BIT(PIPE_B);
> + enabled_mask &= ~BIT(PIPE_B);
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> - disabled_mask |= BIT(PIPE_C);
> -
> - num_bits = hweight8(disabled_mask);
> -
> - switch (disabled_mask) {
> - case BIT(PIPE_A):
> - case BIT(PIPE_B):
> - case BIT(PIPE_A) | BIT(PIPE_B):
> - case BIT(PIPE_A) | BIT(PIPE_C):
> - invalid = true;
> - break;
> - default:
> - invalid = false;
> - }
> + enabled_mask &= ~BIT(PIPE_C);
>
> - if (num_bits > info->num_pipes || invalid)
> - DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> - disabled_mask);
> + /*
> + * At least one pipe should be enabled and if there are
> + * disabled pipes, they should be the last ones, with no holes
> + * in the mask.
> + */
> + if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> + DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
> + enabled_mask);
> else
> - info->num_pipes -= num_bits;
> + info->num_pipes = hweight8(enabled_mask);
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 03/28] drm/i915: Add 4th pipe and transcoder
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-07-08 13:00 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
` (28 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6217b5bcea2a..9b13c62d3d53 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17009,7 +17009,7 @@ struct intel_display_error_state {
u32 vtotal;
u32 vblank;
u32 vsync;
- } transcoder[4];
+ } transcoder[5];
};
struct intel_display_error_state *
@@ -17020,6 +17020,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
TRANSCODER_A,
TRANSCODER_B,
TRANSCODER_C,
+ TRANSCODER_D,
TRANSCODER_EDP,
};
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 12ded01ed5d3..dc9e4615246e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -58,6 +58,7 @@ enum pipe {
PIPE_A = 0,
PIPE_B,
PIPE_C,
+ PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
@@ -75,6 +76,7 @@ enum transcoder {
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
+ TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
@@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder transcoder)
return "B";
case TRANSCODER_C:
return "C";
+ case TRANSCODER_D:
+ return "D";
case TRANSCODER_EDP:
return "EDP";
case TRANSCODER_DSI_A:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8047f1bed314..a63a337eec2c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4219,6 +4219,7 @@ enum {
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
@@ -5765,6 +5766,7 @@ enum {
#define PIPE_A_OFFSET 0x70000
#define PIPE_B_OFFSET 0x71000
#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
#define CHV_PIPE_C_OFFSET 0x74000
/*
* There's actually no pipe EDP. Some pipe registers have
@@ -9331,6 +9333,7 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
#define _TRANS_DDI_FUNC_CTL_C 0x62400
+#define _TRANS_DDI_FUNC_CTL_D 0x63400
#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 03/28] drm/i915: Add 4th pipe and transcoder
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
@ 2019-07-08 13:00 ` Ville Syrjälä
0 siblings, 0 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-07-08 13:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:12AM -0700, Lucas De Marchi wrote:
> Add pipe D and transcoder D to prepare for platforms having them.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_display.h | 4 ++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6217b5bcea2a..9b13c62d3d53 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17009,7 +17009,7 @@ struct intel_display_error_state {
> u32 vtotal;
> u32 vblank;
> u32 vsync;
> - } transcoder[4];
> + } transcoder[5];
> };
>
> struct intel_display_error_state *
> @@ -17020,6 +17020,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
> TRANSCODER_A,
> TRANSCODER_B,
> TRANSCODER_C,
> + TRANSCODER_D,
> TRANSCODER_EDP,
> };
> int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 12ded01ed5d3..dc9e4615246e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -58,6 +58,7 @@ enum pipe {
> PIPE_A = 0,
> PIPE_B,
> PIPE_C,
> + PIPE_D,
> _PIPE_EDP,
>
> I915_MAX_PIPES = _PIPE_EDP
> @@ -75,6 +76,7 @@ enum transcoder {
> TRANSCODER_A = PIPE_A,
> TRANSCODER_B = PIPE_B,
> TRANSCODER_C = PIPE_C,
> + TRANSCODER_D = PIPE_D,
>
> /*
> * The following transcoders can map to any pipe, their enum value
> @@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder transcoder)
> return "B";
> case TRANSCODER_C:
> return "C";
> + case TRANSCODER_D:
> + return "D";
> case TRANSCODER_EDP:
> return "EDP";
> case TRANSCODER_DSI_A:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8047f1bed314..a63a337eec2c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4219,6 +4219,7 @@ enum {
> #define TRANSCODER_B_OFFSET 0x61000
> #define TRANSCODER_C_OFFSET 0x62000
> #define CHV_TRANSCODER_C_OFFSET 0x63000
> +#define TRANSCODER_D_OFFSET 0x63000
> #define TRANSCODER_EDP_OFFSET 0x6f000
> #define TRANSCODER_DSI0_OFFSET 0x6b000
> #define TRANSCODER_DSI1_OFFSET 0x6b800
> @@ -5765,6 +5766,7 @@ enum {
> #define PIPE_A_OFFSET 0x70000
> #define PIPE_B_OFFSET 0x71000
> #define PIPE_C_OFFSET 0x72000
> +#define PIPE_D_OFFSET 0x73000
> #define CHV_PIPE_C_OFFSET 0x74000
> /*
> * There's actually no pipe EDP. Some pipe registers have
> @@ -9331,6 +9333,7 @@ enum skl_power_gate {
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
> #define _TRANS_DDI_FUNC_CTL_C 0x62400
> +#define _TRANS_DDI_FUNC_CTL_D 0x63400
> #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
> #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
> #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (2 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 17:40 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
` (27 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 30 ++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
4 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e981b03face..8d0106b89f24 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2091,6 +2091,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6c9f46fc3e12..29d2d6070f81 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -765,6 +765,36 @@ static const struct intel_device_info intel_elkhartlake_info = {
.ppgtt_size = 36,
};
+#define GEN12_FEATURES \
+ GEN11_FEATURES, \
+ GEN(12), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }
+
+static const struct intel_device_info intel_tigerlake_12_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_TIGERLAKE),
+ .num_pipes = 4,
+ .require_force_probe = 1,
+ .display.has_modular_fia = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e64536e1fd1b..e0d9a7a37994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE),
+ PLATFORM_NAME(TIGERLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e9dc86ed517b..45a9badc9b8e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -78,6 +78,8 @@ enum intel_platform {
/* gen11 */
INTEL_ICELAKE,
INTEL_ELKHARTLAKE,
+ /* gen12 */
+ INTEL_TIGERLAKE,
INTEL_MAX_PLATFORMS
};
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
@ 2019-06-26 17:40 ` Srivatsa, Anusha
0 siblings, 0 replies; 61+ messages in thread
From: Srivatsa, Anusha @ 2019-06-26 17:40 UTC (permalink / raw)
To: intel-gfx; +Cc: De Marchi, Lucas
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Tuesday, June 25, 2019 10:54 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [Intel-gfx] [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions
>
>From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
>Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
>
>This is just an initial Tiger Lake definition. PCI IDs, generic support and new
>features coming in following patches.
>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 30 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> 4 files changed, 34 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 7e981b03face..8d0106b89f24 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2091,6 +2091,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
>*i915,
> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv,
>INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv,
>INTEL_ELKHARTLAKE)
>+#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv,
>INTEL_TIGERLAKE)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>#define IS_BDW_ULT(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c
>b/drivers/gpu/drm/i915/i915_pci.c index 6c9f46fc3e12..29d2d6070f81 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -765,6 +765,36 @@ static const struct intel_device_info
>intel_elkhartlake_info = {
> .ppgtt_size = 36,
> };
>
>+#define GEN12_FEATURES \
>+ GEN11_FEATURES, \
>+ GEN(12), \
>+ .pipe_offsets = { \
>+ [TRANSCODER_A] = PIPE_A_OFFSET, \
>+ [TRANSCODER_B] = PIPE_B_OFFSET, \
>+ [TRANSCODER_C] = PIPE_C_OFFSET, \
>+ [TRANSCODER_D] = PIPE_D_OFFSET, \
>+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
>+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
>+ }, \
>+ .trans_offsets = { \
>+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
>+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>+ }
>+
>+static const struct intel_device_info intel_tigerlake_12_info = {
>+ GEN12_FEATURES,
>+ PLATFORM(INTEL_TIGERLAKE),
>+ .num_pipes = 4,
>+ .require_force_probe = 1,
>+ .display.has_modular_fia = 1,
>+ .engine_mask =
>+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), };
>+
> #undef GEN
> #undef PLATFORM
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>b/drivers/gpu/drm/i915/intel_device_info.c
>index e64536e1fd1b..e0d9a7a37994 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(CANNONLAKE),
> PLATFORM_NAME(ICELAKE),
> PLATFORM_NAME(ELKHARTLAKE),
>+ PLATFORM_NAME(TIGERLAKE),
> };
> #undef PLATFORM_NAME
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>b/drivers/gpu/drm/i915/intel_device_info.h
>index e9dc86ed517b..45a9badc9b8e 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -78,6 +78,8 @@ enum intel_platform {
> /* gen11 */
> INTEL_ICELAKE,
> INTEL_ELKHARTLAKE,
>+ /* gen12 */
>+ INTEL_TIGERLAKE,
> INTEL_MAX_PLATFORMS
> };
>
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (3 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-07-07 10:49 ` Gupta, Anshuman
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
` (26 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Add the enum additions to TGP.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: David Weinehall <david.weinehall@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 96b7bbc58155..4c26c7f662ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
+ case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
+ WARN_ON(!IS_TIGERLAKE(dev_priv));
+ return PCH_TGP;
default:
return PCH_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d0106b89f24..a77c63a0d48a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -536,6 +536,7 @@ enum intel_pch {
PCH_CNP, /* Cannon/Comet Lake PCH */
PCH_ICP, /* Ice Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
+ PCH_TGP, /* Tiger Lake PCH */
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -2325,6 +2326,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
@@ -2332,6 +2334,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
@ 2019-07-07 10:49 ` Gupta, Anshuman
2019-07-08 10:59 ` Gupta, Anshuman
0 siblings, 1 reply; 61+ messages in thread
From: Gupta, Anshuman @ 2019-07-07 10:49 UTC (permalink / raw)
To: intel-gfx
Looks good to me, there in one minor comment.
On 6/25/2019 11:24 PM, Lucas De Marchi wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Add the enum additions to TGP.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: David Weinehall <david.weinehall@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 96b7bbc58155..4c26c7f662ad 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
> DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
> WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> return PCH_MCC;
> + case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> + DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
> + WARN_ON(!IS_TIGERLAKE(dev_priv));
> + return PCH_TGP;
> default:
> return PCH_NONE;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8d0106b89f24..a77c63a0d48a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -536,6 +536,7 @@ enum intel_pch {
> PCH_CNP, /* Cannon/Comet Lake PCH */
> PCH_ICP, /* Ice Lake PCH */
> PCH_MCC, /* Mule Creek Canyon PCH */
> + PCH_TGP, /* Tiger Lake PCH */
> };
>
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> @@ -2325,6 +2326,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
> #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
> #define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
> +#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
> @@ -2332,6 +2334,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> +#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)This macro could be defined before HAS_PCH_MCC to follow the order in
which intel_pch enum are defined.
> #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
> #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
> #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH
2019-07-07 10:49 ` Gupta, Anshuman
@ 2019-07-08 10:59 ` Gupta, Anshuman
0 siblings, 0 replies; 61+ messages in thread
From: Gupta, Anshuman @ 2019-07-08 10:59 UTC (permalink / raw)
To: intel-gfx, radhakrishna.sripada
On 7/7/2019 4:19 PM, Gupta, Anshuman wrote:
> Looks good to me, there in one minor comment.
>
> On 6/25/2019 11:24 PM, Lucas De Marchi wrote:
>> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>>
>> Add the enum additions to TGP.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: David Weinehall <david.weinehall@intel.com>
>> Cc: James Ausmus <james.ausmus@intel.com>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> drivers/gpu/drm/i915/i915_drv.h | 3 +++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 96b7bbc58155..4c26c7f662ad 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private
>> *dev_priv, unsigned short id)
>> DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
>> WARN_ON(!IS_ELKHARTLAKE(dev_priv));
>> return PCH_MCC;
>> + case INTEL_PCH_TGP_DEVICE_ID_TYPE:
>> + DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
>> + WARN_ON(!IS_TIGERLAKE(dev_priv));
>> + return PCH_TGP;
>> default:
>> return PCH_NONE;
>> }
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 8d0106b89f24..a77c63a0d48a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -536,6 +536,7 @@ enum intel_pch {
>> PCH_CNP, /* Cannon/Comet Lake PCH */
>> PCH_ICP, /* Ice Lake PCH */
>> PCH_MCC, /* Mule Creek Canyon PCH */
>> + PCH_TGP, /* Tiger Lake PCH */
>> };
>> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
>> @@ -2325,6 +2326,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
>> #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
>> #define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
>> +#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
>> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
>> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
>> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has
>> 2918 */
>> @@ -2332,6 +2334,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
>> #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
>> +#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
>> PCH_TGP)This macro could be defined before HAS_PCH_MCC to follow the
>> order in
> which intel_pch enum are defined.
>> #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
>> #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
>> #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (4 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 18:27 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
` (25 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4c26c7f662ad..1fcfd46702e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
* make an educated guess as to which PCH is really there.
*/
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_TIGERLAKE(dev_priv))
+ id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
+ else if (IS_ELKHARTLAKE(dev_priv))
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
else if (IS_ICELAKE(dev_priv))
id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
@ 2019-06-26 18:27 ` Srivatsa, Anusha
0 siblings, 0 replies; 61+ messages in thread
From: Srivatsa, Anusha @ 2019-06-26 18:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, De Marchi, Lucas
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Tuesday, June 25, 2019 10:54 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mahesh Kumar <mahesh1.kumar@intel.com>; De Marchi, Lucas
><lucas.demarchi@intel.com>
>Subject: [Intel-gfx] [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in
>virtualized environment
>
>From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
>Assume PCH_TGP when platform is TGL.
>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 4c26c7f662ad..1fcfd46702e5 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private
>*dev_priv)
> * make an educated guess as to which PCH is really there.
> */
>
>- if (IS_ELKHARTLAKE(dev_priv))
>+ if (IS_TIGERLAKE(dev_priv))
>+ id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
>+ else if (IS_ELKHARTLAKE(dev_priv))
> id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> else if (IS_ICELAKE(dev_priv))
> id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (5 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-07-08 10:55 ` Gupta, Anshuman
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
` (24 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 29d2d6070f81..b758dccf4803 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -866,6 +866,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
+ INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6d60ea68c171..ce4c4b5d5ba8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -582,4 +582,14 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info)
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
+
#endif /* _I915_PCIIDS_H */
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
@ 2019-07-08 10:55 ` Gupta, Anshuman
2019-07-08 13:31 ` Lucas De Marchi
0 siblings, 1 reply; 61+ messages in thread
From: Gupta, Anshuman @ 2019-07-08 10:55 UTC (permalink / raw)
To: intel-gfx, lucas.demarchi
On 6/25/2019 11:24 PM, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 10 ++++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 29d2d6070f81..b758dccf4803 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -866,6 +866,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CNL_IDS(&intel_cannonlake_info),
> INTEL_ICL_11_IDS(&intel_icelake_11_info),
> INTEL_EHL_IDS(&intel_elkhartlake_info),
> + INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 6d60ea68c171..ce4c4b5d5ba8 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -582,4 +582,14 @@
> INTEL_VGA_DEVICE(0x4551, info), \
> INTEL_VGA_DEVICE(0x4541, info)
>
> +/* TGL */
> +#define INTEL_TGL_12_IDS(info) \
> + INTEL_VGA_DEVICE(0x9A49, info), \
> + INTEL_VGA_DEVICE(0x9A40, info), \
> + INTEL_VGA_DEVICE(0x9A59, info), \
> + INTEL_VGA_DEVICE(0x9A60, info), \
> + INTEL_VGA_DEVICE(0x9A68, info), \
> + INTEL_VGA_DEVICE(0x9A70, info), \
> + INTEL_VGA_DEVICE(0x9A78, info)
B. Specs index 44455 has display only SKU and its device id 0x9A7F,
don't we require this pci device id?
> +
> #endif /* _I915_PCIIDS_H */
>
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^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs
2019-07-08 10:55 ` Gupta, Anshuman
@ 2019-07-08 13:31 ` Lucas De Marchi
0 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-07-08 13:31 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: intel-gfx
On Mon, Jul 08, 2019 at 04:25:19PM +0530, Gupta, Anshuman wrote:
>
>
>On 6/25/2019 11:24 PM, Lucas De Marchi wrote:
>>Current list of PCI IDs for Tiger Lake.
>>
>>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>> drivers/gpu/drm/i915/i915_pci.c | 1 +
>> include/drm/i915_pciids.h | 10 ++++++++++
>> 2 files changed, 11 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>>index 29d2d6070f81..b758dccf4803 100644
>>--- a/drivers/gpu/drm/i915/i915_pci.c
>>+++ b/drivers/gpu/drm/i915/i915_pci.c
>>@@ -866,6 +866,7 @@ static const struct pci_device_id pciidlist[] = {
>> INTEL_CNL_IDS(&intel_cannonlake_info),
>> INTEL_ICL_11_IDS(&intel_icelake_11_info),
>> INTEL_EHL_IDS(&intel_elkhartlake_info),
>>+ INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
>> {0, 0, 0}
>> };
>> MODULE_DEVICE_TABLE(pci, pciidlist);
>>diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>index 6d60ea68c171..ce4c4b5d5ba8 100644
>>--- a/include/drm/i915_pciids.h
>>+++ b/include/drm/i915_pciids.h
>>@@ -582,4 +582,14 @@
>> INTEL_VGA_DEVICE(0x4551, info), \
>> INTEL_VGA_DEVICE(0x4541, info)
>>+/* TGL */
>>+#define INTEL_TGL_12_IDS(info) \
>>+ INTEL_VGA_DEVICE(0x9A49, info), \
>>+ INTEL_VGA_DEVICE(0x9A40, info), \
>>+ INTEL_VGA_DEVICE(0x9A59, info), \
>>+ INTEL_VGA_DEVICE(0x9A60, info), \
>>+ INTEL_VGA_DEVICE(0x9A68, info), \
>>+ INTEL_VGA_DEVICE(0x9A70, info), \
>>+ INTEL_VGA_DEVICE(0x9A78, info)
>B. Specs index 44455 has display only SKU and its device id 0x9A7F,
>don't we require this pci device id?
I wouldn't expect a "display only" device to work with the code we
are adding here. So I don't think we should add it.
Lucas De Marchi
>>+
>> #endif /* _I915_PCIIDS_H */
>>
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^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 08/28] x86/gpu: add TGL stolen memory support
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (6 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-07-09 12:03 ` Rodrigo Vivi
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
` (23 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Lucas De Marchi
From: Michel Thierry <michel.thierry@intel.com>
Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
register (and format).
Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: x86@kernel.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6c4f01540833..6f6b1d04dadf 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_CNL_IDS(&gen9_early_ops),
INTEL_ICL_11_IDS(&gen11_early_ops),
INTEL_EHL_IDS(&gen11_early_ops),
+ INTEL_TGL_12_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 08/28] x86/gpu: add TGL stolen memory support
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
@ 2019-07-09 12:03 ` Rodrigo Vivi
0 siblings, 0 replies; 61+ messages in thread
From: Rodrigo Vivi @ 2019-07-09 12:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx
On Tue, Jun 25, 2019 at 10:54:17AM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
> register (and format).
>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: x86@kernel.org
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 6c4f01540833..6f6b1d04dadf 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
> INTEL_CNL_IDS(&gen9_early_ops),
> INTEL_ICL_11_IDS(&gen11_early_ops),
> INTEL_EHL_IDS(&gen11_early_ops),
> + INTEL_TGL_12_IDS(&gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (7 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 21:24 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
` (22 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: José Roberto de Souza <jose.souza@intel.com>
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a63a337eec2c..95fdc8dbca31 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7618,6 +7618,7 @@ enum {
#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
#define SKL_DSSM _MMIO(0x51004)
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
enabled_mask &= ~BIT(PIPE_B);
if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
enabled_mask &= ~BIT(PIPE_C);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+ enabled_mask &= ~BIT(PIPE_D);
/*
* At least one pipe should be enabled and if there are
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
@ 2019-06-26 21:24 ` Srivatsa, Anusha
0 siblings, 0 replies; 61+ messages in thread
From: Srivatsa, Anusha @ 2019-06-26 21:24 UTC (permalink / raw)
To: intel-gfx; +Cc: De Marchi, Lucas
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Tuesday, June 25, 2019 10:54 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [Intel-gfx] [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused
>
>From: José Roberto de Souza <jose.souza@intel.com>
>
>On Tiger Lake there is one more pipe - check if it's fused.
>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> 2 files changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a63a337eec2c..95fdc8dbca31 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7618,6 +7618,7 @@ enum {
> #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>+#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
>
> #define SKL_DSSM _MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>b/drivers/gpu/drm/i915/intel_device_info.c
>index e0d9a7a37994..f99c9fd497b2 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct
>drm_i915_private *dev_priv)
> enabled_mask &= ~BIT(PIPE_B);
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> enabled_mask &= ~BIT(PIPE_C);
>+ if (INTEL_GEN(dev_priv) >= 12 &&
>+ (dfsm & TGL_DFSM_PIPE_D_DISABLE))
>+ enabled_mask &= ~BIT(PIPE_D);
>
> /*
> * At least one pipe should be enabled and if there are
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 10/28] drm/i915/tgl: Add power well support
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (8 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-27 19:15 ` Manasi Navare
2019-06-27 19:31 ` Souza, Jose
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
` (21 subsequent siblings)
31 siblings, 2 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Imre Deak <imre.deak@intel.com>
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
specific IO power wells (only for the non-TBT modes) and 4 port
specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
eDP and MIPI DSI (TODO)
On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI#C-F
Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI TC#1-6
To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 474 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 18 +
4 files changed, 502 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c93ad512014c..20b2009cecc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain)
{
+ bool ddi_tc_ports = IS_GEN(i915, 12);
+
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -60,11 +63,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+ POWER_DOMAIN_PORT_DDI_TC1_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+ POWER_DOMAIN_PORT_DDI_TC2_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+ POWER_DOMAIN_PORT_DDI_TC3_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+ return "PORT_DDI_TC4_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+ return "PORT_DDI_TC5_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+ return "PORT_DDI_TC6_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -72,11 +87,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+ POWER_DOMAIN_PORT_DDI_TC1_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
+ POWER_DOMAIN_PORT_DDI_TC2_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
case POWER_DOMAIN_PORT_DDI_F_IO:
- return "PORT_DDI_F_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
+ POWER_DOMAIN_PORT_DDI_TC3_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
+ case POWER_DOMAIN_PORT_DDI_TC4_IO:
+ return "PORT_DDI_TC4_IO";
+ case POWER_DOMAIN_PORT_DDI_TC5_IO:
+ return "PORT_DDI_TC5_IO";
+ case POWER_DOMAIN_PORT_DDI_TC6_IO:
+ return "PORT_DDI_TC6_IO";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -94,11 +121,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
case POWER_DOMAIN_AUX_C:
return "AUX_C";
case POWER_DOMAIN_AUX_D:
- return "AUX_D";
+ BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
+ return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
case POWER_DOMAIN_AUX_E:
- return "AUX_E";
+ BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
+ return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
case POWER_DOMAIN_AUX_F:
- return "AUX_F";
+ BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
+ return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
+ case POWER_DOMAIN_AUX_TC4:
+ return "AUX_TC4";
+ case POWER_DOMAIN_AUX_TC5:
+ return "AUX_TC5";
+ case POWER_DOMAIN_AUX_TC6:
+ return "AUX_TC6";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT1:
@@ -109,6 +145,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_TBT3";
case POWER_DOMAIN_AUX_TBT4:
return "AUX_TBT4";
+ case POWER_DOMAIN_AUX_TBT5:
+ return "AUX_TBT5";
+ case POWER_DOMAIN_AUX_TBT6:
+ return "AUX_TBT6";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
static void print_power_domains(struct i915_power_domains *power_domains,
const char *prefix, u64 mask)
{
+ struct drm_i915_private *i915 =
+ container_of(power_domains, struct drm_i915_private,
+ power_domains);
enum intel_display_power_domain domain;
DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
for_each_power_domain(domain, mask)
DRM_DEBUG_DRIVER("%s use_count %d\n",
- intel_display_power_domain_str(domain),
+ intel_display_power_domain_str(i915, domain),
power_domains->domain_use_count[domain]);
}
@@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
{
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
- const char *name = intel_display_power_domain_str(domain);
+ const char *name = intel_display_power_domain_str(dev_priv, domain);
power_domains = &dev_priv->power_domains;
@@ -2307,11 +2350,14 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
* ICL PW_1/PG_1 domains (HW/DMC control):
* - DBUF function
* - PIPE_A and its planes, except VGA
- * - transcoder EDP + PSR
+ * - GEN 11: transcoder EDP + PSR
+ * GEN 12: transcoder A + PSR
* - transcoder DSI
- * - DDI_A
+ * - GEN 11: DDI_A
+ * GEN 12: DDI_A-C
* - FBC
*/
+/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
@@ -2346,22 +2392,67 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_3_POWER_DOMAINS ( \
+ ICL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ /* TODO: TRANSCODER_D */ \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
/*
* - transcoder WD
* - KVMR (HW control)
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_2_POWER_DOMAINS ( \
+ TGL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - KVMR (HW control)
+ * - GEN 11: eDP/DSI VDSC
+ * - GEN 12: PIPE A VDSC/joining
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
ICL_PW_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define ICL_DDI_IO_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
@@ -2371,10 +2462,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
#define ICL_DDI_IO_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
+#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
#define ICL_DDI_IO_E_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
+#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
#define ICL_DDI_IO_F_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
+#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
+#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
+#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
+#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
#define ICL_AUX_A_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
@@ -2385,10 +2488,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_C))
#define ICL_AUX_D_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D))
+#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC1))
#define ICL_AUX_E_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_E))
+#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC2))
#define ICL_AUX_F_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_F))
+#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC3))
+#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC4))
+#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC5))
+#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TC6))
#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_TBT1))
#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
@@ -2397,6 +2512,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_TBT3))
#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5))
+#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6))
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
@@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
+static const struct i915_power_well_desc tgl_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 2",
+ .domains = TGL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = TGL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ },
+ {
+ .name = "DDI TC1 IO",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ },
+ {
+ .name = "DDI TC2 IO",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ },
+ {
+ .name = "DDI TC3 IO",
+ .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ },
+ },
+ {
+ .name = "DDI TC4 IO",
+ .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ },
+ },
+ {
+ .name = "DDI TC5 IO",
+ .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+ },
+ },
+ {
+ .name = "DDI TC6 IO",
+ .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_combo_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_combo_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX C",
+ .domains = ICL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_combo_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
+ },
+ {
+ .name = "AUX TC1",
+ .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TC2",
+ .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TC3",
+ .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TC4",
+ .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TC5",
+ .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TC6",
+ .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
+ .ops = &icl_tc_phy_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TBT1",
+ .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT2",
+ .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT3",
+ .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT4",
+ .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT5",
+ .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT6",
+ .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = ICL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ },
+ /* TODO: power well 5 for pipe D */
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_GEN(dev_priv, 11)) {
+ if (IS_GEN(dev_priv, 12)) {
+ err = set_power_wells(power_domains, tgl_power_wells);
+ } else if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4546,7 +4985,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
for_each_power_domain(domain, power_well->desc->domains)
DRM_DEBUG_DRIVER(" %-23s %d\n",
- intel_display_power_domain_str(domain),
+ intel_display_power_domain_str(i915,
+ domain),
power_domains->domain_use_count[domain]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index ff57b0a7fe59..8f81b769bc2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -32,14 +32,29 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_B_LANES,
POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES,
+ POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES,
+ POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
POWER_DOMAIN_PORT_DDI_F_LANES,
+ POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
+ POWER_DOMAIN_PORT_DDI_TC4_LANES,
+ POWER_DOMAIN_PORT_DDI_TC5_LANES,
+ POWER_DOMAIN_PORT_DDI_TC6_LANES,
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO,
+ POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO,
+ POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
POWER_DOMAIN_PORT_DDI_F_IO,
+ POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
+ POWER_DOMAIN_PORT_DDI_G_IO,
+ POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
+ POWER_DOMAIN_PORT_DDI_H_IO,
+ POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
+ POWER_DOMAIN_PORT_DDI_I_IO,
+ POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -49,13 +64,21 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E,
+ POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
+ POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
+ POWER_DOMAIN_AUX_TC4,
+ POWER_DOMAIN_AUX_TC5,
+ POWER_DOMAIN_AUX_TC6,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_AUX_TBT5,
+ POWER_DOMAIN_AUX_TBT6,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
@@ -227,7 +250,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain);
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index eeecdad0e3ca..5247fa69dfec 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
for_each_power_domain(power_domain, power_well->desc->domains)
seq_printf(m, " %-23s %d\n",
- intel_display_power_domain_str(power_domain),
+ intel_display_power_domain_str(dev_priv,
+ power_domain),
power_domains->domain_use_count[power_domain]);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95fdc8dbca31..a2010b30ca89 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9141,13 +9141,25 @@ enum {
#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
+#define TGL_PW_CTL_IDX_AUX_TBT6 14
+#define TGL_PW_CTL_IDX_AUX_TBT5 13
+#define TGL_PW_CTL_IDX_AUX_TBT4 12
#define ICL_PW_CTL_IDX_AUX_TBT4 11
+#define TGL_PW_CTL_IDX_AUX_TBT3 11
#define ICL_PW_CTL_IDX_AUX_TBT3 10
+#define TGL_PW_CTL_IDX_AUX_TBT2 10
#define ICL_PW_CTL_IDX_AUX_TBT2 9
+#define TGL_PW_CTL_IDX_AUX_TBT1 9
#define ICL_PW_CTL_IDX_AUX_TBT1 8
+#define TGL_PW_CTL_IDX_AUX_TC6 8
+#define TGL_PW_CTL_IDX_AUX_TC5 7
+#define TGL_PW_CTL_IDX_AUX_TC4 6
#define ICL_PW_CTL_IDX_AUX_F 5
+#define TGL_PW_CTL_IDX_AUX_TC3 5
#define ICL_PW_CTL_IDX_AUX_E 4
+#define TGL_PW_CTL_IDX_AUX_TC2 4
#define ICL_PW_CTL_IDX_AUX_D 3
+#define TGL_PW_CTL_IDX_AUX_TC1 3
#define ICL_PW_CTL_IDX_AUX_C 2
#define ICL_PW_CTL_IDX_AUX_B 1
#define ICL_PW_CTL_IDX_AUX_A 0
@@ -9155,9 +9167,15 @@ enum {
#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
+#define TGL_PW_CTL_IDX_DDI_TC6 8
+#define TGL_PW_CTL_IDX_DDI_TC5 7
+#define TGL_PW_CTL_IDX_DDI_TC4 6
#define ICL_PW_CTL_IDX_DDI_F 5
+#define TGL_PW_CTL_IDX_DDI_TC3 5
#define ICL_PW_CTL_IDX_DDI_E 4
+#define TGL_PW_CTL_IDX_DDI_TC2 4
#define ICL_PW_CTL_IDX_DDI_D 3
+#define TGL_PW_CTL_IDX_DDI_TC1 3
#define ICL_PW_CTL_IDX_DDI_C 2
#define ICL_PW_CTL_IDX_DDI_B 1
#define ICL_PW_CTL_IDX_DDI_A 0
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 10/28] drm/i915/tgl: Add power well support
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
@ 2019-06-27 19:15 ` Manasi Navare
2019-06-27 20:23 ` Lucas De Marchi
2019-06-27 19:31 ` Souza, Jose
1 sibling, 1 reply; 61+ messages in thread
From: Manasi Navare @ 2019-06-27 19:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:19AM -0700, Lucas De Marchi wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
> low-power mode instead)
> - Transcoder#A is now backed by power well#1 instead of power well#3
> - The DDI#B/C combo PHY ports are now backed by power well#1 instead of
> power well#3
> - New power well#5 added for pipe#D functionality (TODO)
> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
> specific IO power wells (only for the non-TBT modes) and 4 port
> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
> eDP and MIPI DSI (TODO)
>
> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
> have the following naming for ports:
>
> - Combo PHYs (native DP/HDMI):
> DDI#A-B
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI#C-F
>
> Starting from GEN 12 we have the following naming for ports:
> - Combo PHYs (native DP/HDMI):
> DDI#A-C
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI TC#1-6
>
> To save some space in the power domain enum the power domain naming in
> the driver reflects the above change, that is power domains TC#1-3 are
> added as aliases for DDI#D-F and new power domains are reserved for
> TC#4-6.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 474 +++++++++++++++++-
> .../drm/i915/display/intel_display_power.h | 26 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 18 +
> 4 files changed, 502 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c93ad512014c..20b2009cecc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> enum i915_power_well_id power_well_id);
>
> const char *
> -intel_display_power_domain_str(enum intel_display_power_domain domain)
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> + enum intel_display_power_domain domain)
> {
> + bool ddi_tc_ports = IS_GEN(i915, 12);
> +
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -60,11 +63,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - return "PORT_DDI_D_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - return "PORT_DDI_E_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - return "PORT_DDI_F_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> + return "PORT_DDI_TC4_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> + return "PORT_DDI_TC5_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> + return "PORT_DDI_TC6_LANES";
> case POWER_DOMAIN_PORT_DDI_A_IO:
> return "PORT_DDI_A_IO";
> case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -72,11 +87,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_IO:
> return "PORT_DDI_C_IO";
> case POWER_DOMAIN_PORT_DDI_D_IO:
> - return "PORT_DDI_D_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> + POWER_DOMAIN_PORT_DDI_TC1_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
> case POWER_DOMAIN_PORT_DDI_E_IO:
> - return "PORT_DDI_E_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> + POWER_DOMAIN_PORT_DDI_TC2_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
> case POWER_DOMAIN_PORT_DDI_F_IO:
> - return "PORT_DDI_F_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> + POWER_DOMAIN_PORT_DDI_TC3_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
> + case POWER_DOMAIN_PORT_DDI_TC4_IO:
> + return "PORT_DDI_TC4_IO";
> + case POWER_DOMAIN_PORT_DDI_TC5_IO:
> + return "PORT_DDI_TC5_IO";
> + case POWER_DOMAIN_PORT_DDI_TC6_IO:
> + return "PORT_DDI_TC6_IO";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> @@ -94,11 +121,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> case POWER_DOMAIN_AUX_C:
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> - return "AUX_D";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
> + return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> case POWER_DOMAIN_AUX_E:
> - return "AUX_E";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
> + return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> case POWER_DOMAIN_AUX_F:
> - return "AUX_F";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
> + return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> + case POWER_DOMAIN_AUX_TC4:
> + return "AUX_TC4";
> + case POWER_DOMAIN_AUX_TC5:
> + return "AUX_TC5";
> + case POWER_DOMAIN_AUX_TC6:
> + return "AUX_TC6";
> case POWER_DOMAIN_AUX_IO_A:
> return "AUX_IO_A";
> case POWER_DOMAIN_AUX_TBT1:
> @@ -109,6 +145,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "AUX_TBT3";
> case POWER_DOMAIN_AUX_TBT4:
> return "AUX_TBT4";
> + case POWER_DOMAIN_AUX_TBT5:
> + return "AUX_TBT5";
> + case POWER_DOMAIN_AUX_TBT6:
> + return "AUX_TBT6";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> case POWER_DOMAIN_INIT:
> @@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
> static void print_power_domains(struct i915_power_domains *power_domains,
> const char *prefix, u64 mask)
> {
> + struct drm_i915_private *i915 =
> + container_of(power_domains, struct drm_i915_private,
> + power_domains);
> enum intel_display_power_domain domain;
>
> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> for_each_power_domain(domain, mask)
> DRM_DEBUG_DRIVER("%s use_count %d\n",
> - intel_display_power_domain_str(domain),
> + intel_display_power_domain_str(i915, domain),
> power_domains->domain_use_count[domain]);
> }
>
> @@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains;
> struct i915_power_well *power_well;
> - const char *name = intel_display_power_domain_str(domain);
> + const char *name = intel_display_power_domain_str(dev_priv, domain);
>
> power_domains = &dev_priv->power_domains;
>
> @@ -2307,11 +2350,14 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> * ICL PW_1/PG_1 domains (HW/DMC control):
> * - DBUF function
> * - PIPE_A and its planes, except VGA
> - * - transcoder EDP + PSR
> + * - GEN 11: transcoder EDP + PSR
> + * GEN 12: transcoder A + PSR
> * - transcoder DSI
> - * - DDI_A
> + * - GEN 11: DDI_A
> + * GEN 12: DDI_A-C
> * - FBC
> */
> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> #define ICL_PW_4_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> @@ -2346,22 +2392,67 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_3_POWER_DOMAINS ( \
> + ICL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + /* TODO: TRANSCODER_D */ \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> /*
> * - transcoder WD
> * - KVMR (HW control)
> */
> #define ICL_PW_2_POWER_DOMAINS ( \
> ICL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_2_POWER_DOMAINS ( \
> + TGL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
Shouldn't this be POWER_DOMAIN_TRANSCODER_A_VDSC for VDSC/joining on Pipe A or
Transcoder A?
Patch 12 of this series then asisgns POWER_DOMAIN_TRANSCODER_A_VDSC
Manasi
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
> * - KVMR (HW control)
> + * - GEN 11: eDP/DSI VDSC
> + * - GEN 12: PIPE A VDSC/joining
> */
> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> ICL_PW_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + TGL_PW_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
> @@ -2371,10 +2462,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
> #define ICL_DDI_IO_D_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> +#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> #define ICL_DDI_IO_E_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> +#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> #define ICL_DDI_IO_F_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> +#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> +#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> +#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> +#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>
> #define ICL_AUX_A_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> @@ -2385,10 +2488,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_C))
> #define ICL_AUX_D_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D))
> +#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC1))
> #define ICL_AUX_E_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_E))
> +#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC2))
> #define ICL_AUX_F_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_F))
> +#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC3))
> +#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC4))
> +#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC5))
> +#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC6))
> #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> @@ -2397,6 +2512,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> };
>
> +static const struct i915_power_well_desc tgl_power_wells[] = {
> + {
> + .name = "always-on",
> + .always_on = true,
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .always_on = true,
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DC off",
> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 2",
> + .domains = TGL_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "power well 3",
> + .domains = TGL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + },
> + {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + },
> + {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + }
> + },
> + {
> + .name = "DDI TC1 IO",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + },
> + {
> + .name = "DDI TC2 IO",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + },
> + {
> + .name = "DDI TC3 IO",
> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> + },
> + },
> + {
> + .name = "DDI TC4 IO",
> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> + },
> + },
> + {
> + .name = "DDI TC5 IO",
> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> + },
> + },
> + {
> + .name = "DDI TC6 IO",
> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> + },
> + },
> + {
> + .name = "AUX A",
> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + },
> + {
> + .name = "AUX B",
> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + },
> + {
> + .name = "AUX C",
> + .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + },
> + },
> + {
> + .name = "AUX TC1",
> + .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC2",
> + .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC3",
> + .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC4",
> + .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC5",
> + .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC6",
> + .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TBT1",
> + .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT2",
> + .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT3",
> + .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT4",
> + .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT5",
> + .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT6",
> + .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "power well 4",
> + .domains = ICL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + },
> + /* TODO: power well 5 for pipe D */
> +};
> +
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> int disable_power_well)
> @@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
> - if (IS_GEN(dev_priv, 11)) {
> + if (IS_GEN(dev_priv, 12)) {
> + err = set_power_wells(power_domains, tgl_power_wells);
> + } else if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4546,7 +4985,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
>
> for_each_power_domain(domain, power_well->desc->domains)
> DRM_DEBUG_DRIVER(" %-23s %d\n",
> - intel_display_power_domain_str(domain),
> + intel_display_power_domain_str(i915,
> + domain),
> power_domains->domain_use_count[domain]);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ff57b0a7fe59..8f81b769bc2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_DDI_B_LANES,
> POWER_DOMAIN_PORT_DDI_C_LANES,
> POWER_DOMAIN_PORT_DDI_D_LANES,
> + POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
> POWER_DOMAIN_PORT_DDI_E_LANES,
> + POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DDI_F_LANES,
> + POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
> + POWER_DOMAIN_PORT_DDI_TC4_LANES,
> + POWER_DOMAIN_PORT_DDI_TC5_LANES,
> + POWER_DOMAIN_PORT_DDI_TC6_LANES,
> POWER_DOMAIN_PORT_DDI_A_IO,
> POWER_DOMAIN_PORT_DDI_B_IO,
> POWER_DOMAIN_PORT_DDI_C_IO,
> POWER_DOMAIN_PORT_DDI_D_IO,
> + POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> POWER_DOMAIN_PORT_DDI_E_IO,
> + POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> POWER_DOMAIN_PORT_DDI_F_IO,
> + POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> + POWER_DOMAIN_PORT_DDI_G_IO,
> + POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> + POWER_DOMAIN_PORT_DDI_H_IO,
> + POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> + POWER_DOMAIN_PORT_DDI_I_IO,
> + POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_AUX_E,
> + POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> POWER_DOMAIN_AUX_F,
> + POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> + POWER_DOMAIN_AUX_TC4,
> + POWER_DOMAIN_AUX_TC5,
> + POWER_DOMAIN_AUX_TC6,
> POWER_DOMAIN_AUX_IO_A,
> POWER_DOMAIN_AUX_TBT1,
> POWER_DOMAIN_AUX_TBT2,
> POWER_DOMAIN_AUX_TBT3,
> POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_AUX_TBT5,
> + POWER_DOMAIN_AUX_TBT6,
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> @@ -227,7 +250,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>
> const char *
> -intel_display_power_domain_str(enum intel_display_power_domain domain);
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> + enum intel_display_power_domain domain);
>
> bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
> enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index eeecdad0e3ca..5247fa69dfec 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>
> for_each_power_domain(power_domain, power_well->desc->domains)
> seq_printf(m, " %-23s %d\n",
> - intel_display_power_domain_str(power_domain),
> + intel_display_power_domain_str(dev_priv,
> + power_domain),
> power_domains->domain_use_count[power_domain]);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95fdc8dbca31..a2010b30ca89 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9141,13 +9141,25 @@ enum {
> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
> #define ICL_PW_CTL_IDX_AUX_TBT4 11
> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
> #define ICL_PW_CTL_IDX_AUX_TBT3 10
> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
> #define ICL_PW_CTL_IDX_AUX_TBT2 9
> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
> #define ICL_PW_CTL_IDX_AUX_TBT1 8
> +#define TGL_PW_CTL_IDX_AUX_TC6 8
> +#define TGL_PW_CTL_IDX_AUX_TC5 7
> +#define TGL_PW_CTL_IDX_AUX_TC4 6
> #define ICL_PW_CTL_IDX_AUX_F 5
> +#define TGL_PW_CTL_IDX_AUX_TC3 5
> #define ICL_PW_CTL_IDX_AUX_E 4
> +#define TGL_PW_CTL_IDX_AUX_TC2 4
> #define ICL_PW_CTL_IDX_AUX_D 3
> +#define TGL_PW_CTL_IDX_AUX_TC1 3
> #define ICL_PW_CTL_IDX_AUX_C 2
> #define ICL_PW_CTL_IDX_AUX_B 1
> #define ICL_PW_CTL_IDX_AUX_A 0
> @@ -9155,9 +9167,15 @@ enum {
> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
> +#define TGL_PW_CTL_IDX_DDI_TC6 8
> +#define TGL_PW_CTL_IDX_DDI_TC5 7
> +#define TGL_PW_CTL_IDX_DDI_TC4 6
> #define ICL_PW_CTL_IDX_DDI_F 5
> +#define TGL_PW_CTL_IDX_DDI_TC3 5
> #define ICL_PW_CTL_IDX_DDI_E 4
> +#define TGL_PW_CTL_IDX_DDI_TC2 4
> #define ICL_PW_CTL_IDX_DDI_D 3
> +#define TGL_PW_CTL_IDX_DDI_TC1 3
> #define ICL_PW_CTL_IDX_DDI_C 2
> #define ICL_PW_CTL_IDX_DDI_B 1
> #define ICL_PW_CTL_IDX_DDI_A 0
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 10/28] drm/i915/tgl: Add power well support
2019-06-27 19:15 ` Manasi Navare
@ 2019-06-27 20:23 ` Lucas De Marchi
0 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-27 20:23 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Jun 27, 2019 at 12:15:26PM -0700, Manasi Navare wrote:
>On Tue, Jun 25, 2019 at 10:54:19AM -0700, Lucas De Marchi wrote:
>> From: Imre Deak <imre.deak@intel.com>
>>
>> The patch adds the new power wells introduced by TGL (GEN 12) and
>> maps these to existing/new power domains. The changes for GEN 12 wrt
>> to GEN 11 are the following:
>>
>> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
>> low-power mode instead)
>> - Transcoder#A is now backed by power well#1 instead of power well#3
>> - The DDI#B/C combo PHY ports are now backed by power well#1 instead of
>> power well#3
>> - New power well#5 added for pipe#D functionality (TODO)
>> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
>> specific IO power wells (only for the non-TBT modes) and 4 port
>> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
>> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
>> eDP and MIPI DSI (TODO)
>>
>> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
>> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
>> have the following naming for ports:
>>
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-B
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI#C-F
>>
>> Starting from GEN 12 we have the following naming for ports:
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-C
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI TC#1-6
>>
>> To save some space in the power domain enum the power domain naming in
>> the driver reflects the above change, that is power domains TC#1-3 are
>> added as aliases for DDI#D-F and new power domains are reserved for
>> TC#4-6.
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 474 +++++++++++++++++-
>> .../drm/i915/display/intel_display_power.h | 26 +-
>> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
>> drivers/gpu/drm/i915/i915_reg.h | 18 +
>> 4 files changed, 502 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index c93ad512014c..20b2009cecc6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>> enum i915_power_well_id power_well_id);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain domain)
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain)
>> {
>> + bool ddi_tc_ports = IS_GEN(i915, 12);
>> +
>> switch (domain) {
>> case POWER_DOMAIN_DISPLAY_CORE:
>> return "DISPLAY_CORE";
>> @@ -60,11 +63,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_LANES:
>> return "PORT_DDI_C_LANES";
>> case POWER_DOMAIN_PORT_DDI_D_LANES:
>> - return "PORT_DDI_D_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
>> case POWER_DOMAIN_PORT_DDI_E_LANES:
>> - return "PORT_DDI_E_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
>> case POWER_DOMAIN_PORT_DDI_F_LANES:
>> - return "PORT_DDI_F_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
>> + return "PORT_DDI_TC4_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
>> + return "PORT_DDI_TC5_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
>> + return "PORT_DDI_TC6_LANES";
>> case POWER_DOMAIN_PORT_DDI_A_IO:
>> return "PORT_DDI_A_IO";
>> case POWER_DOMAIN_PORT_DDI_B_IO:
>> @@ -72,11 +87,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_IO:
>> return "PORT_DDI_C_IO";
>> case POWER_DOMAIN_PORT_DDI_D_IO:
>> - return "PORT_DDI_D_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC1_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
>> case POWER_DOMAIN_PORT_DDI_E_IO:
>> - return "PORT_DDI_E_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC2_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
>> case POWER_DOMAIN_PORT_DDI_F_IO:
>> - return "PORT_DDI_F_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC3_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC4_IO:
>> + return "PORT_DDI_TC4_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC5_IO:
>> + return "PORT_DDI_TC5_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC6_IO:
>> + return "PORT_DDI_TC6_IO";
>> case POWER_DOMAIN_PORT_DSI:
>> return "PORT_DSI";
>> case POWER_DOMAIN_PORT_CRT:
>> @@ -94,11 +121,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>> case POWER_DOMAIN_AUX_C:
>> return "AUX_C";
>> case POWER_DOMAIN_AUX_D:
>> - return "AUX_D";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
>> + return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
>> case POWER_DOMAIN_AUX_E:
>> - return "AUX_E";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
>> + return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
>> case POWER_DOMAIN_AUX_F:
>> - return "AUX_F";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
>> + return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
>> + case POWER_DOMAIN_AUX_TC4:
>> + return "AUX_TC4";
>> + case POWER_DOMAIN_AUX_TC5:
>> + return "AUX_TC5";
>> + case POWER_DOMAIN_AUX_TC6:
>> + return "AUX_TC6";
>> case POWER_DOMAIN_AUX_IO_A:
>> return "AUX_IO_A";
>> case POWER_DOMAIN_AUX_TBT1:
>> @@ -109,6 +145,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>> return "AUX_TBT3";
>> case POWER_DOMAIN_AUX_TBT4:
>> return "AUX_TBT4";
>> + case POWER_DOMAIN_AUX_TBT5:
>> + return "AUX_TBT5";
>> + case POWER_DOMAIN_AUX_TBT6:
>> + return "AUX_TBT6";
>> case POWER_DOMAIN_GMBUS:
>> return "GMBUS";
>> case POWER_DOMAIN_INIT:
>> @@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
>> static void print_power_domains(struct i915_power_domains *power_domains,
>> const char *prefix, u64 mask)
>> {
>> + struct drm_i915_private *i915 =
>> + container_of(power_domains, struct drm_i915_private,
>> + power_domains);
>> enum intel_display_power_domain domain;
>>
>> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
>> for_each_power_domain(domain, mask)
>> DRM_DEBUG_DRIVER("%s use_count %d\n",
>> - intel_display_power_domain_str(domain),
>> + intel_display_power_domain_str(i915, domain),
>> power_domains->domain_use_count[domain]);
>> }
>>
>> @@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>> {
>> struct i915_power_domains *power_domains;
>> struct i915_power_well *power_well;
>> - const char *name = intel_display_power_domain_str(domain);
>> + const char *name = intel_display_power_domain_str(dev_priv, domain);
>>
>> power_domains = &dev_priv->power_domains;
>>
>> @@ -2307,11 +2350,14 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> * ICL PW_1/PG_1 domains (HW/DMC control):
>> * - DBUF function
>> * - PIPE_A and its planes, except VGA
>> - * - transcoder EDP + PSR
>> + * - GEN 11: transcoder EDP + PSR
>> + * GEN 12: transcoder A + PSR
>> * - transcoder DSI
>> - * - DDI_A
>> + * - GEN 11: DDI_A
>> + * GEN 12: DDI_A-C
>> * - FBC
>> */
>> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>> #define ICL_PW_4_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
>> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
>> @@ -2346,22 +2392,67 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_VGA) | \
>> BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_3_POWER_DOMAINS ( \
>> + ICL_PW_4_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
>> + /* TODO: TRANSCODER_D */ \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
>> + BIT_ULL(POWER_DOMAIN_VGA) | \
>> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - transcoder WD
>> * - KVMR (HW control)
>> */
>> #define ICL_PW_2_POWER_DOMAINS ( \
>> ICL_PW_3_POWER_DOMAINS | \
>> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_2_POWER_DOMAINS ( \
>> + TGL_PW_3_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>
>Shouldn't this be POWER_DOMAIN_TRANSCODER_A_VDSC for VDSC/joining on Pipe A or
>Transcoder A?
>Patch 12 of this series then asisgns POWER_DOMAIN_TRANSCODER_A_VDSC
that patch should be renaming this to TRANSCODER_A_VDSC, but maybe
reordering the patches like Jose suggested would be better.
Lucas De Marchi
>
>Manasi
>
>> BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - KVMR (HW control)
>> + * - GEN 11: eDP/DSI VDSC
>> + * - GEN 12: PIPE A VDSC/joining
>> */
>> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> ICL_PW_2_POWER_DOMAINS | \
>> BIT_ULL(POWER_DOMAIN_MODESET) | \
>> BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> + TGL_PW_2_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_MODESET) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>>
>> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
>> @@ -2371,10 +2462,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
>> #define ICL_DDI_IO_D_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
>> +#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
>> #define ICL_DDI_IO_E_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
>> +#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
>> #define ICL_DDI_IO_F_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
>> +#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
>> +#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
>> +#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
>> +#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>>
>> #define ICL_AUX_A_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
>> @@ -2385,10 +2488,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_C))
>> #define ICL_AUX_D_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_D))
>> +#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1))
>> #define ICL_AUX_E_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_E))
>> +#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2))
>> #define ICL_AUX_F_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_F))
>> +#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3))
>> +#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4))
>> +#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5))
>> +#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6))
>> #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT1))
>> #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
>> @@ -2397,6 +2512,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_TBT3))
>> #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5))
>> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>>
>> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>> .sync_hw = i9xx_power_well_sync_hw_noop,
>> @@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
>> },
>> };
>>
>> +static const struct i915_power_well_desc tgl_power_wells[] = {
>> + {
>> + .name = "always-on",
>> + .always_on = true,
>> + .domains = POWER_DOMAIN_MASK,
>> + .ops = &i9xx_always_on_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 1",
>> + /* Handled by the DMC firmware */
>> + .always_on = true,
>> + .domains = 0,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_1,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DC off",
>> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>> + .ops = &gen9_dc_off_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 2",
>> + .domains = TGL_PW_2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_2,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "power well 3",
>> + .domains = TGL_PW_3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
>> + .hsw.irq_pipe_mask = BIT(PIPE_B),
>> + .hsw.has_vga = true,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DDI A IO",
>> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>> + }
>> + },
>> + {
>> + .name = "DDI B IO",
>> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>> + }
>> + },
>> + {
>> + .name = "DDI C IO",
>> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
>> + }
>> + },
>> + {
>> + .name = "DDI TC1 IO",
>> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>> + },
>> + },
>> + {
>> + .name = "DDI TC2 IO",
>> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>> + },
>> + },
>> + {
>> + .name = "DDI TC3 IO",
>> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
>> + },
>> + },
>> + {
>> + .name = "DDI TC4 IO",
>> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
>> + },
>> + },
>> + {
>> + .name = "DDI TC5 IO",
>> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
>> + },
>> + },
>> + {
>> + .name = "DDI TC6 IO",
>> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
>> + },
>> + },
>> + {
>> + .name = "AUX A",
>> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>> + },
>> + },
>> + {
>> + .name = "AUX B",
>> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>> + },
>> + },
>> + {
>> + .name = "AUX C",
>> + .domains = ICL_AUX_C_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
>> + },
>> + },
>> + {
>> + .name = "AUX TC1",
>> + .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC2",
>> + .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC3",
>> + .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC4",
>> + .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC5",
>> + .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC6",
>> + .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT1",
>> + .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT2",
>> + .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT3",
>> + .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT4",
>> + .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT5",
>> + .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT6",
>> + .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "power well 4",
>> + .domains = ICL_PW_4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
>> + .hsw.has_fuses = true,
>> + .hsw.irq_pipe_mask = BIT(PIPE_C),
>> + }
>> + },
>> + /* TODO: power well 5 for pipe D */
>> +};
>> +
>> static int
>> sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>> int disable_power_well)
>> @@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>> * The enabling order will be from lower to higher indexed wells,
>> * the disabling order is reversed.
>> */
>> - if (IS_GEN(dev_priv, 11)) {
>> + if (IS_GEN(dev_priv, 12)) {
>> + err = set_power_wells(power_domains, tgl_power_wells);
>> + } else if (IS_GEN(dev_priv, 11)) {
>> err = set_power_wells(power_domains, icl_power_wells);
>> } else if (IS_CANNONLAKE(dev_priv)) {
>> err = set_power_wells(power_domains, cnl_power_wells);
>> @@ -4546,7 +4985,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
>>
>> for_each_power_domain(domain, power_well->desc->domains)
>> DRM_DEBUG_DRIVER(" %-23s %d\n",
>> - intel_display_power_domain_str(domain),
>> + intel_display_power_domain_str(i915,
>> + domain),
>> power_domains->domain_use_count[domain]);
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index ff57b0a7fe59..8f81b769bc2e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_PORT_DDI_B_LANES,
>> POWER_DOMAIN_PORT_DDI_C_LANES,
>> POWER_DOMAIN_PORT_DDI_D_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
>> POWER_DOMAIN_PORT_DDI_E_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
>> POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC4_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC5_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC6_LANES,
>> POWER_DOMAIN_PORT_DDI_A_IO,
>> POWER_DOMAIN_PORT_DDI_B_IO,
>> POWER_DOMAIN_PORT_DDI_C_IO,
>> POWER_DOMAIN_PORT_DDI_D_IO,
>> + POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
>> POWER_DOMAIN_PORT_DDI_E_IO,
>> + POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
>> POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_I_IO,
>> + POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
>> POWER_DOMAIN_PORT_DSI,
>> POWER_DOMAIN_PORT_CRT,
>> POWER_DOMAIN_PORT_OTHER,
>> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_AUX_B,
>> POWER_DOMAIN_AUX_C,
>> POWER_DOMAIN_AUX_D,
>> + POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
>> POWER_DOMAIN_AUX_E,
>> + POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
>> POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC4,
>> + POWER_DOMAIN_AUX_TC5,
>> + POWER_DOMAIN_AUX_TC6,
>> POWER_DOMAIN_AUX_IO_A,
>> POWER_DOMAIN_AUX_TBT1,
>> POWER_DOMAIN_AUX_TBT2,
>> POWER_DOMAIN_AUX_TBT3,
>> POWER_DOMAIN_AUX_TBT4,
>> + POWER_DOMAIN_AUX_TBT5,
>> + POWER_DOMAIN_AUX_TBT6,
>> POWER_DOMAIN_GMBUS,
>> POWER_DOMAIN_MODESET,
>> POWER_DOMAIN_GT_IRQ,
>> @@ -227,7 +250,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
>> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain domain);
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain);
>>
>> bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
>> enum intel_display_power_domain domain);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index eeecdad0e3ca..5247fa69dfec 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>>
>> for_each_power_domain(power_domain, power_well->desc->domains)
>> seq_printf(m, " %-23s %d\n",
>> - intel_display_power_domain_str(power_domain),
>> + intel_display_power_domain_str(dev_priv,
>> + power_domain),
>> power_domains->domain_use_count[power_domain]);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 95fdc8dbca31..a2010b30ca89 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9141,13 +9141,25 @@ enum {
>> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
>> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
>> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
>> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
>> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
>> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
>> #define ICL_PW_CTL_IDX_AUX_TBT4 11
>> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
>> #define ICL_PW_CTL_IDX_AUX_TBT3 10
>> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
>> #define ICL_PW_CTL_IDX_AUX_TBT2 9
>> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
>> #define ICL_PW_CTL_IDX_AUX_TBT1 8
>> +#define TGL_PW_CTL_IDX_AUX_TC6 8
>> +#define TGL_PW_CTL_IDX_AUX_TC5 7
>> +#define TGL_PW_CTL_IDX_AUX_TC4 6
>> #define ICL_PW_CTL_IDX_AUX_F 5
>> +#define TGL_PW_CTL_IDX_AUX_TC3 5
>> #define ICL_PW_CTL_IDX_AUX_E 4
>> +#define TGL_PW_CTL_IDX_AUX_TC2 4
>> #define ICL_PW_CTL_IDX_AUX_D 3
>> +#define TGL_PW_CTL_IDX_AUX_TC1 3
>> #define ICL_PW_CTL_IDX_AUX_C 2
>> #define ICL_PW_CTL_IDX_AUX_B 1
>> #define ICL_PW_CTL_IDX_AUX_A 0
>> @@ -9155,9 +9167,15 @@ enum {
>> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
>> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
>> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
>> +#define TGL_PW_CTL_IDX_DDI_TC6 8
>> +#define TGL_PW_CTL_IDX_DDI_TC5 7
>> +#define TGL_PW_CTL_IDX_DDI_TC4 6
>> #define ICL_PW_CTL_IDX_DDI_F 5
>> +#define TGL_PW_CTL_IDX_DDI_TC3 5
>> #define ICL_PW_CTL_IDX_DDI_E 4
>> +#define TGL_PW_CTL_IDX_DDI_TC2 4
>> #define ICL_PW_CTL_IDX_DDI_D 3
>> +#define TGL_PW_CTL_IDX_DDI_TC1 3
>> #define ICL_PW_CTL_IDX_DDI_C 2
>> #define ICL_PW_CTL_IDX_DDI_B 1
>> #define ICL_PW_CTL_IDX_DDI_A 0
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH 10/28] drm/i915/tgl: Add power well support
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
2019-06-27 19:15 ` Manasi Navare
@ 2019-06-27 19:31 ` Souza, Jose
2019-06-27 20:22 ` Lucas De Marchi
1 sibling, 1 reply; 61+ messages in thread
From: Souza, Jose @ 2019-06-27 19:31 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
> low-power mode instead)
> - Transcoder#A is now backed by power well#1 instead of power well#3
> - The DDI#B/C combo PHY ports are now backed by power well#1 instead
> of
> power well#3
> - New power well#5 added for pipe#D functionality (TODO)
> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
> specific IO power wells (only for the non-TBT modes) and 4 port
> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
> eDP and MIPI DSI (TODO)
>
> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL
> we
> have the following naming for ports:
>
> - Combo PHYs (native DP/HDMI):
> DDI#A-B
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI#C-F
>
> Starting from GEN 12 we have the following naming for ports:
> - Combo PHYs (native DP/HDMI):
> DDI#A-C
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI TC#1-6
>
> To save some space in the power domain enum the power domain naming
> in
> the driver reflects the above change, that is power domains TC#1-3
> are
> added as aliases for DDI#D-F and new power domains are reserved for
> TC#4-6.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 474
> +++++++++++++++++-
> .../drm/i915/display/intel_display_power.h | 26 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 18 +
> 4 files changed, 502 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c93ad512014c..20b2009cecc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
> enum i915_power_well_id
> power_well_id);
>
> const char *
> -intel_display_power_domain_str(enum intel_display_power_domain
> domain)
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> + enum intel_display_power_domain domain)
> {
> + bool ddi_tc_ports = IS_GEN(i915, 12);
> +
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -60,11 +63,23 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - return "PORT_DDI_D_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
> "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - return "PORT_DDI_E_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
> "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - return "PORT_DDI_F_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
> "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> + return "PORT_DDI_TC4_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> + return "PORT_DDI_TC5_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> + return "PORT_DDI_TC6_LANES";
> case POWER_DOMAIN_PORT_DDI_A_IO:
> return "PORT_DDI_A_IO";
> case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -72,11 +87,23 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_IO:
> return "PORT_DDI_C_IO";
> case POWER_DOMAIN_PORT_DDI_D_IO:
> - return "PORT_DDI_D_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> + POWER_DOMAIN_PORT_DDI_TC1_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
> "PORT_DDI_D_IO";
> case POWER_DOMAIN_PORT_DDI_E_IO:
> - return "PORT_DDI_E_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> + POWER_DOMAIN_PORT_DDI_TC2_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
> "PORT_DDI_E_IO";
> case POWER_DOMAIN_PORT_DDI_F_IO:
> - return "PORT_DDI_F_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> + POWER_DOMAIN_PORT_DDI_TC3_IO);
> + return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
> "PORT_DDI_F_IO";
> + case POWER_DOMAIN_PORT_DDI_TC4_IO:
> + return "PORT_DDI_TC4_IO";
> + case POWER_DOMAIN_PORT_DDI_TC5_IO:
> + return "PORT_DDI_TC5_IO";
> + case POWER_DOMAIN_PORT_DDI_TC6_IO:
> + return "PORT_DDI_TC6_IO";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> @@ -94,11 +121,20 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> case POWER_DOMAIN_AUX_C:
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> - return "AUX_D";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
> POWER_DOMAIN_AUX_TC1);
> + return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> case POWER_DOMAIN_AUX_E:
> - return "AUX_E";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
> POWER_DOMAIN_AUX_TC2);
> + return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> case POWER_DOMAIN_AUX_F:
> - return "AUX_F";
> + BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
> POWER_DOMAIN_AUX_TC3);
> + return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> + case POWER_DOMAIN_AUX_TC4:
> + return "AUX_TC4";
> + case POWER_DOMAIN_AUX_TC5:
> + return "AUX_TC5";
> + case POWER_DOMAIN_AUX_TC6:
> + return "AUX_TC6";
> case POWER_DOMAIN_AUX_IO_A:
> return "AUX_IO_A";
> case POWER_DOMAIN_AUX_TBT1:
> @@ -109,6 +145,10 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "AUX_TBT3";
> case POWER_DOMAIN_AUX_TBT4:
> return "AUX_TBT4";
> + case POWER_DOMAIN_AUX_TBT5:
> + return "AUX_TBT5";
> + case POWER_DOMAIN_AUX_TBT6:
> + return "AUX_TBT6";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> case POWER_DOMAIN_INIT:
> @@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct
> i915_power_domains *power_domains)
> static void print_power_domains(struct i915_power_domains
> *power_domains,
> const char *prefix, u64 mask)
> {
> + struct drm_i915_private *i915 =
> + container_of(power_domains, struct drm_i915_private,
> + power_domains);
> enum intel_display_power_domain domain;
>
> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> for_each_power_domain(domain, mask)
> DRM_DEBUG_DRIVER("%s use_count %d\n",
> - intel_display_power_domain_str(domain)
> ,
> + intel_display_power_domain_str(i915,
> domain),
> power_domains-
> >domain_use_count[domain]);
> }
>
> @@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct
> drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains;
> struct i915_power_well *power_well;
> - const char *name = intel_display_power_domain_str(domain);
> + const char *name = intel_display_power_domain_str(dev_priv,
> domain);
>
> power_domains = &dev_priv->power_domains;
>
> @@ -2307,11 +2350,14 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> * ICL PW_1/PG_1 domains (HW/DMC control):
> * - DBUF function
> * - PIPE_A and its planes, except VGA
> - * - transcoder EDP + PSR
> + * - GEN 11: transcoder EDP + PSR
> + * GEN 12: transcoder A + PSR
> * - transcoder DSI
> - * - DDI_A
> + * - GEN 11: DDI_A
> + * GEN 12: DDI_A-C
> * - FBC
> */
> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> #define ICL_PW_4_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> @@ -2346,22 +2392,67 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_3_POWER_DOMAINS ( \
> + ICL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + /* TODO: TRANSCODER_D */ \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> /*
> * - transcoder WD
> * - KVMR (HW control)
> */
> #define ICL_PW_2_POWER_DOMAINS ( \
> ICL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_2_POWER_DOMAINS ( \
> + TGL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
There is no POWER_DOMAIN_TRANSCODER_EDP_VDSC on TGL, maybe reorder the
patches to have "drm/i915/tgl: Add TRANSCODER_A_VDSC power domain"
first then you can add TRANSCODER_A_VDSC here.
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
> * - KVMR (HW control)
> + * - GEN 11: eDP/DSI VDSC
> + * - GEN 12: PIPE A VDSC/joining
> */
> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> ICL_PW_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + TGL_PW_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
> @@ -2371,10 +2462,22 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
> #define ICL_DDI_IO_D_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> +#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> #define ICL_DDI_IO_E_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> +#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> #define ICL_DDI_IO_F_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> +#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> +#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> +#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> +#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>
> #define ICL_AUX_A_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> @@ -2385,10 +2488,22 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_C))
> #define ICL_AUX_D_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D))
> +#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC1))
> #define ICL_AUX_E_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_E))
> +#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC2))
> #define ICL_AUX_F_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_F))
> +#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC3))
> +#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC4))
> +#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC5))
> +#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TC6))
> #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> @@ -2397,6 +2512,10 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>
> static const struct i915_power_well_ops
> i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> };
>
> +static const struct i915_power_well_desc tgl_power_wells[] = {
> + {
> + .name = "always-on",
> + .always_on = true,
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .always_on = true,
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DC off",
> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 2",
> + .domains = TGL_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "power well 3",
> + .domains = TGL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + },
> + {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + },
> + {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + }
> + },
> + {
> + .name = "DDI TC1 IO",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + },
> + {
> + .name = "DDI TC2 IO",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + },
> + {
> + .name = "DDI TC3 IO",
> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> + },
> + },
> + {
> + .name = "DDI TC4 IO",
> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> + },
> + },
> + {
> + .name = "DDI TC5 IO",
> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> + },
> + },
> + {
> + .name = "DDI TC6 IO",
> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> + },
> + },
> + {
> + .name = "AUX A",
> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + },
> + {
> + .name = "AUX B",
> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + },
> + {
> + .name = "AUX C",
> + .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .ops = &icl_combo_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + },
> + },
> + {
> + .name = "AUX TC1",
> + .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC2",
> + .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC3",
> + .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC4",
> + .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC5",
> + .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TC6",
> + .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> + .ops = &icl_tc_phy_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX TBT1",
> + .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT2",
> + .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT3",
> + .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT4",
> + .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT5",
> + .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT6",
> + .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "power well 4",
> + .domains = ICL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + },
> + /* TODO: power well 5 for pipe D */
> +};
> +
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private
> *dev_priv,
> int disable_power_well)
> @@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed
> wells,
> * the disabling order is reversed.
> */
> - if (IS_GEN(dev_priv, 11)) {
> + if (IS_GEN(dev_priv, 12)) {
> + err = set_power_wells(power_domains, tgl_power_wells);
> + } else if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4546,7 +4985,8 @@ static void
> intel_power_domains_dump_info(struct drm_i915_private *i915)
>
> for_each_power_domain(domain, power_well->desc-
> >domains)
> DRM_DEBUG_DRIVER(" %-23s %d\n",
> - intel_display_power_domain_str
> (domain),
> + intel_display_power_domain_str
> (i915,
> +
> domain),
> power_domains-
> >domain_use_count[domain]);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ff57b0a7fe59..8f81b769bc2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_DDI_B_LANES,
> POWER_DOMAIN_PORT_DDI_C_LANES,
> POWER_DOMAIN_PORT_DDI_D_LANES,
> + POWER_DOMAIN_PORT_DDI_TC1_LANES =
> POWER_DOMAIN_PORT_DDI_D_LANES,
> POWER_DOMAIN_PORT_DDI_E_LANES,
> + POWER_DOMAIN_PORT_DDI_TC2_LANES =
> POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DDI_F_LANES,
> + POWER_DOMAIN_PORT_DDI_TC3_LANES =
> POWER_DOMAIN_PORT_DDI_F_LANES,
> + POWER_DOMAIN_PORT_DDI_TC4_LANES,
> + POWER_DOMAIN_PORT_DDI_TC5_LANES,
> + POWER_DOMAIN_PORT_DDI_TC6_LANES,
> POWER_DOMAIN_PORT_DDI_A_IO,
> POWER_DOMAIN_PORT_DDI_B_IO,
> POWER_DOMAIN_PORT_DDI_C_IO,
> POWER_DOMAIN_PORT_DDI_D_IO,
> + POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> POWER_DOMAIN_PORT_DDI_E_IO,
> + POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> POWER_DOMAIN_PORT_DDI_F_IO,
> + POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> + POWER_DOMAIN_PORT_DDI_G_IO,
> + POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> + POWER_DOMAIN_PORT_DDI_H_IO,
> + POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> + POWER_DOMAIN_PORT_DDI_I_IO,
> + POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_AUX_E,
> + POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> POWER_DOMAIN_AUX_F,
> + POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> + POWER_DOMAIN_AUX_TC4,
> + POWER_DOMAIN_AUX_TC5,
> + POWER_DOMAIN_AUX_TC6,
> POWER_DOMAIN_AUX_IO_A,
> POWER_DOMAIN_AUX_TBT1,
> POWER_DOMAIN_AUX_TBT2,
> POWER_DOMAIN_AUX_TBT3,
> POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_AUX_TBT5,
> + POWER_DOMAIN_AUX_TBT6,
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> @@ -227,7 +250,8 @@ void bxt_display_core_init(struct
> drm_i915_private *dev_priv, bool resume);
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>
> const char *
> -intel_display_power_domain_str(enum intel_display_power_domain
> domain);
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> + enum intel_display_power_domain domain);
>
> bool intel_display_power_is_enabled(struct drm_i915_private
> *dev_priv,
> enum intel_display_power_domain
> domain);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index eeecdad0e3ca..5247fa69dfec 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct
> seq_file *m, void *unused)
>
> for_each_power_domain(power_domain, power_well->desc-
> >domains)
> seq_printf(m, " %-23s %d\n",
> - intel_display_power_domain_str(power_d
> omain),
> + intel_display_power_domain_str(dev_pri
> v,
> + power_d
> omain),
> power_domains-
> >domain_use_count[power_domain]);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 95fdc8dbca31..a2010b30ca89 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9141,13 +9141,25 @@ enum {
> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
> #define ICL_PW_CTL_IDX_AUX_TBT4 11
> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
> #define ICL_PW_CTL_IDX_AUX_TBT3 10
> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
> #define ICL_PW_CTL_IDX_AUX_TBT2 9
> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
> #define ICL_PW_CTL_IDX_AUX_TBT1 8
> +#define TGL_PW_CTL_IDX_AUX_TC6 8
> +#define TGL_PW_CTL_IDX_AUX_TC5 7
> +#define TGL_PW_CTL_IDX_AUX_TC4 6
> #define ICL_PW_CTL_IDX_AUX_F 5
> +#define TGL_PW_CTL_IDX_AUX_TC3 5
> #define ICL_PW_CTL_IDX_AUX_E 4
> +#define TGL_PW_CTL_IDX_AUX_TC2 4
> #define ICL_PW_CTL_IDX_AUX_D 3
> +#define TGL_PW_CTL_IDX_AUX_TC1 3
> #define ICL_PW_CTL_IDX_AUX_C 2
> #define ICL_PW_CTL_IDX_AUX_B 1
> #define ICL_PW_CTL_IDX_AUX_A 0
> @@ -9155,9 +9167,15 @@ enum {
> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
> +#define TGL_PW_CTL_IDX_DDI_TC6 8
> +#define TGL_PW_CTL_IDX_DDI_TC5 7
> +#define TGL_PW_CTL_IDX_DDI_TC4 6
> #define ICL_PW_CTL_IDX_DDI_F 5
> +#define TGL_PW_CTL_IDX_DDI_TC3 5
> #define ICL_PW_CTL_IDX_DDI_E 4
> +#define TGL_PW_CTL_IDX_DDI_TC2 4
> #define ICL_PW_CTL_IDX_DDI_D 3
> +#define TGL_PW_CTL_IDX_DDI_TC1 3
> #define ICL_PW_CTL_IDX_DDI_C 2
> #define ICL_PW_CTL_IDX_DDI_B 1
> #define ICL_PW_CTL_IDX_DDI_A 0
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^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 10/28] drm/i915/tgl: Add power well support
2019-06-27 19:31 ` Souza, Jose
@ 2019-06-27 20:22 ` Lucas De Marchi
0 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-27 20:22 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Jun 27, 2019 at 12:31:30PM -0700, Jose Souza wrote:
>On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
>> From: Imre Deak <imre.deak@intel.com>
>>
>> The patch adds the new power wells introduced by TGL (GEN 12) and
>> maps these to existing/new power domains. The changes for GEN 12 wrt
>> to GEN 11 are the following:
>>
>> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
>> low-power mode instead)
>> - Transcoder#A is now backed by power well#1 instead of power well#3
>> - The DDI#B/C combo PHY ports are now backed by power well#1 instead
>> of
>> power well#3
>> - New power well#5 added for pipe#D functionality (TODO)
>> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
>> specific IO power wells (only for the non-TBT modes) and 4 port
>> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
>> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
>> eDP and MIPI DSI (TODO)
>>
>> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
>> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL
>> we
>> have the following naming for ports:
>>
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-B
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI#C-F
>>
>> Starting from GEN 12 we have the following naming for ports:
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-C
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI TC#1-6
>>
>> To save some space in the power domain enum the power domain naming
>> in
>> the driver reflects the above change, that is power domains TC#1-3
>> are
>> added as aliases for DDI#D-F and new power domains are reserved for
>> TC#4-6.
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 474
>> +++++++++++++++++-
>> .../drm/i915/display/intel_display_power.h | 26 +-
>> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
>> drivers/gpu/drm/i915/i915_reg.h | 18 +
>> 4 files changed, 502 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index c93ad512014c..20b2009cecc6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct
>> drm_i915_private *dev_priv,
>> enum i915_power_well_id
>> power_well_id);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain
>> domain)
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain)
>> {
>> + bool ddi_tc_ports = IS_GEN(i915, 12);
>> +
>> switch (domain) {
>> case POWER_DOMAIN_DISPLAY_CORE:
>> return "DISPLAY_CORE";
>> @@ -60,11 +63,23 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_LANES:
>> return "PORT_DDI_C_LANES";
>> case POWER_DOMAIN_PORT_DDI_D_LANES:
>> - return "PORT_DDI_D_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
>> "PORT_DDI_D_LANES";
>> case POWER_DOMAIN_PORT_DDI_E_LANES:
>> - return "PORT_DDI_E_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
>> "PORT_DDI_E_LANES";
>> case POWER_DOMAIN_PORT_DDI_F_LANES:
>> - return "PORT_DDI_F_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
>> "PORT_DDI_F_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
>> + return "PORT_DDI_TC4_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
>> + return "PORT_DDI_TC5_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
>> + return "PORT_DDI_TC6_LANES";
>> case POWER_DOMAIN_PORT_DDI_A_IO:
>> return "PORT_DDI_A_IO";
>> case POWER_DOMAIN_PORT_DDI_B_IO:
>> @@ -72,11 +87,23 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_IO:
>> return "PORT_DDI_C_IO";
>> case POWER_DOMAIN_PORT_DDI_D_IO:
>> - return "PORT_DDI_D_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC1_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
>> "PORT_DDI_D_IO";
>> case POWER_DOMAIN_PORT_DDI_E_IO:
>> - return "PORT_DDI_E_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC2_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
>> "PORT_DDI_E_IO";
>> case POWER_DOMAIN_PORT_DDI_F_IO:
>> - return "PORT_DDI_F_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC3_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
>> "PORT_DDI_F_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC4_IO:
>> + return "PORT_DDI_TC4_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC5_IO:
>> + return "PORT_DDI_TC5_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC6_IO:
>> + return "PORT_DDI_TC6_IO";
>> case POWER_DOMAIN_PORT_DSI:
>> return "PORT_DSI";
>> case POWER_DOMAIN_PORT_CRT:
>> @@ -94,11 +121,20 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_AUX_C:
>> return "AUX_C";
>> case POWER_DOMAIN_AUX_D:
>> - return "AUX_D";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
>> POWER_DOMAIN_AUX_TC1);
>> + return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
>> case POWER_DOMAIN_AUX_E:
>> - return "AUX_E";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
>> POWER_DOMAIN_AUX_TC2);
>> + return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
>> case POWER_DOMAIN_AUX_F:
>> - return "AUX_F";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
>> POWER_DOMAIN_AUX_TC3);
>> + return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
>> + case POWER_DOMAIN_AUX_TC4:
>> + return "AUX_TC4";
>> + case POWER_DOMAIN_AUX_TC5:
>> + return "AUX_TC5";
>> + case POWER_DOMAIN_AUX_TC6:
>> + return "AUX_TC6";
>> case POWER_DOMAIN_AUX_IO_A:
>> return "AUX_IO_A";
>> case POWER_DOMAIN_AUX_TBT1:
>> @@ -109,6 +145,10 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> return "AUX_TBT3";
>> case POWER_DOMAIN_AUX_TBT4:
>> return "AUX_TBT4";
>> + case POWER_DOMAIN_AUX_TBT5:
>> + return "AUX_TBT5";
>> + case POWER_DOMAIN_AUX_TBT6:
>> + return "AUX_TBT6";
>> case POWER_DOMAIN_GMBUS:
>> return "GMBUS";
>> case POWER_DOMAIN_INIT:
>> @@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct
>> i915_power_domains *power_domains)
>> static void print_power_domains(struct i915_power_domains
>> *power_domains,
>> const char *prefix, u64 mask)
>> {
>> + struct drm_i915_private *i915 =
>> + container_of(power_domains, struct drm_i915_private,
>> + power_domains);
>> enum intel_display_power_domain domain;
>>
>> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
>> for_each_power_domain(domain, mask)
>> DRM_DEBUG_DRIVER("%s use_count %d\n",
>> - intel_display_power_domain_str(domain)
>> ,
>> + intel_display_power_domain_str(i915,
>> domain),
>> power_domains-
>> >domain_use_count[domain]);
>> }
>>
>> @@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct
>> drm_i915_private *dev_priv,
>> {
>> struct i915_power_domains *power_domains;
>> struct i915_power_well *power_well;
>> - const char *name = intel_display_power_domain_str(domain);
>> + const char *name = intel_display_power_domain_str(dev_priv,
>> domain);
>>
>> power_domains = &dev_priv->power_domains;
>>
>> @@ -2307,11 +2350,14 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> * ICL PW_1/PG_1 domains (HW/DMC control):
>> * - DBUF function
>> * - PIPE_A and its planes, except VGA
>> - * - transcoder EDP + PSR
>> + * - GEN 11: transcoder EDP + PSR
>> + * GEN 12: transcoder A + PSR
>> * - transcoder DSI
>> - * - DDI_A
>> + * - GEN 11: DDI_A
>> + * GEN 12: DDI_A-C
>> * - FBC
>> */
>> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>> #define ICL_PW_4_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
>> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
>> @@ -2346,22 +2392,67 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_VGA) | \
>> BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_3_POWER_DOMAINS ( \
>> + ICL_PW_4_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
>> + /* TODO: TRANSCODER_D */ \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
>> + BIT_ULL(POWER_DOMAIN_VGA) | \
>> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - transcoder WD
>> * - KVMR (HW control)
>> */
>> #define ICL_PW_2_POWER_DOMAINS ( \
>> ICL_PW_3_POWER_DOMAINS | \
>> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_2_POWER_DOMAINS ( \
>> + TGL_PW_3_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>
>There is no POWER_DOMAIN_TRANSCODER_EDP_VDSC on TGL, maybe reorder the
>patches to have "drm/i915/tgl: Add TRANSCODER_A_VDSC power domain"
>first then you can add TRANSCODER_A_VDSC here.
makes sense,
thanks
Lucas De Marchi
>
>> BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - KVMR (HW control)
>> + * - GEN 11: eDP/DSI VDSC
>> + * - GEN 12: PIPE A VDSC/joining
>> */
>> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> ICL_PW_2_POWER_DOMAINS | \
>> BIT_ULL(POWER_DOMAIN_MODESET) | \
>> BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> + TGL_PW_2_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_MODESET) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>>
>> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
>> @@ -2371,10 +2462,22 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
>> #define ICL_DDI_IO_D_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
>> +#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
>> #define ICL_DDI_IO_E_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
>> +#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
>> #define ICL_DDI_IO_F_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
>> +#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
>> +#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
>> +#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
>> +#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>>
>> #define ICL_AUX_A_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
>> @@ -2385,10 +2488,22 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_C))
>> #define ICL_AUX_D_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_D))
>> +#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1))
>> #define ICL_AUX_E_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_E))
>> +#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2))
>> #define ICL_AUX_F_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_F))
>> +#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3))
>> +#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4))
>> +#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5))
>> +#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6))
>> #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT1))
>> #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
>> @@ -2397,6 +2512,10 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_TBT3))
>> #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5))
>> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>>
>> static const struct i915_power_well_ops
>> i9xx_always_on_power_well_ops = {
>> .sync_hw = i9xx_power_well_sync_hw_noop,
>> @@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc
>> icl_power_wells[] = {
>> },
>> };
>>
>> +static const struct i915_power_well_desc tgl_power_wells[] = {
>> + {
>> + .name = "always-on",
>> + .always_on = true,
>> + .domains = POWER_DOMAIN_MASK,
>> + .ops = &i9xx_always_on_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 1",
>> + /* Handled by the DMC firmware */
>> + .always_on = true,
>> + .domains = 0,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_1,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DC off",
>> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>> + .ops = &gen9_dc_off_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 2",
>> + .domains = TGL_PW_2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_2,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "power well 3",
>> + .domains = TGL_PW_3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
>> + .hsw.irq_pipe_mask = BIT(PIPE_B),
>> + .hsw.has_vga = true,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DDI A IO",
>> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>> + }
>> + },
>> + {
>> + .name = "DDI B IO",
>> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>> + }
>> + },
>> + {
>> + .name = "DDI C IO",
>> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
>> + }
>> + },
>> + {
>> + .name = "DDI TC1 IO",
>> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>> + },
>> + },
>> + {
>> + .name = "DDI TC2 IO",
>> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>> + },
>> + },
>> + {
>> + .name = "DDI TC3 IO",
>> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
>> + },
>> + },
>> + {
>> + .name = "DDI TC4 IO",
>> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
>> + },
>> + },
>> + {
>> + .name = "DDI TC5 IO",
>> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
>> + },
>> + },
>> + {
>> + .name = "DDI TC6 IO",
>> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
>> + },
>> + },
>> + {
>> + .name = "AUX A",
>> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>> + },
>> + },
>> + {
>> + .name = "AUX B",
>> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>> + },
>> + },
>> + {
>> + .name = "AUX C",
>> + .domains = ICL_AUX_C_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
>> + },
>> + },
>> + {
>> + .name = "AUX TC1",
>> + .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC2",
>> + .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC3",
>> + .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC4",
>> + .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC5",
>> + .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC6",
>> + .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT1",
>> + .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT2",
>> + .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT3",
>> + .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT4",
>> + .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT5",
>> + .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT6",
>> + .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "power well 4",
>> + .domains = ICL_PW_4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
>> + .hsw.has_fuses = true,
>> + .hsw.irq_pipe_mask = BIT(PIPE_C),
>> + }
>> + },
>> + /* TODO: power well 5 for pipe D */
>> +};
>> +
>> static int
>> sanitize_disable_power_well_option(const struct drm_i915_private
>> *dev_priv,
>> int disable_power_well)
>> @@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct
>> drm_i915_private *dev_priv)
>> * The enabling order will be from lower to higher indexed
>> wells,
>> * the disabling order is reversed.
>> */
>> - if (IS_GEN(dev_priv, 11)) {
>> + if (IS_GEN(dev_priv, 12)) {
>> + err = set_power_wells(power_domains, tgl_power_wells);
>> + } else if (IS_GEN(dev_priv, 11)) {
>> err = set_power_wells(power_domains, icl_power_wells);
>> } else if (IS_CANNONLAKE(dev_priv)) {
>> err = set_power_wells(power_domains, cnl_power_wells);
>> @@ -4546,7 +4985,8 @@ static void
>> intel_power_domains_dump_info(struct drm_i915_private *i915)
>>
>> for_each_power_domain(domain, power_well->desc-
>> >domains)
>> DRM_DEBUG_DRIVER(" %-23s %d\n",
>> - intel_display_power_domain_str
>> (domain),
>> + intel_display_power_domain_str
>> (i915,
>> +
>> domain),
>> power_domains-
>> >domain_use_count[domain]);
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index ff57b0a7fe59..8f81b769bc2e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_PORT_DDI_B_LANES,
>> POWER_DOMAIN_PORT_DDI_C_LANES,
>> POWER_DOMAIN_PORT_DDI_D_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES =
>> POWER_DOMAIN_PORT_DDI_D_LANES,
>> POWER_DOMAIN_PORT_DDI_E_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES =
>> POWER_DOMAIN_PORT_DDI_E_LANES,
>> POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES =
>> POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC4_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC5_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC6_LANES,
>> POWER_DOMAIN_PORT_DDI_A_IO,
>> POWER_DOMAIN_PORT_DDI_B_IO,
>> POWER_DOMAIN_PORT_DDI_C_IO,
>> POWER_DOMAIN_PORT_DDI_D_IO,
>> + POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
>> POWER_DOMAIN_PORT_DDI_E_IO,
>> + POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
>> POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_I_IO,
>> + POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
>> POWER_DOMAIN_PORT_DSI,
>> POWER_DOMAIN_PORT_CRT,
>> POWER_DOMAIN_PORT_OTHER,
>> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_AUX_B,
>> POWER_DOMAIN_AUX_C,
>> POWER_DOMAIN_AUX_D,
>> + POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
>> POWER_DOMAIN_AUX_E,
>> + POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
>> POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC4,
>> + POWER_DOMAIN_AUX_TC5,
>> + POWER_DOMAIN_AUX_TC6,
>> POWER_DOMAIN_AUX_IO_A,
>> POWER_DOMAIN_AUX_TBT1,
>> POWER_DOMAIN_AUX_TBT2,
>> POWER_DOMAIN_AUX_TBT3,
>> POWER_DOMAIN_AUX_TBT4,
>> + POWER_DOMAIN_AUX_TBT5,
>> + POWER_DOMAIN_AUX_TBT6,
>> POWER_DOMAIN_GMBUS,
>> POWER_DOMAIN_MODESET,
>> POWER_DOMAIN_GT_IRQ,
>> @@ -227,7 +250,8 @@ void bxt_display_core_init(struct
>> drm_i915_private *dev_priv, bool resume);
>> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain
>> domain);
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain);
>>
>> bool intel_display_power_is_enabled(struct drm_i915_private
>> *dev_priv,
>> enum intel_display_power_domain
>> domain);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index eeecdad0e3ca..5247fa69dfec 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct
>> seq_file *m, void *unused)
>>
>> for_each_power_domain(power_domain, power_well->desc-
>> >domains)
>> seq_printf(m, " %-23s %d\n",
>> - intel_display_power_domain_str(power_d
>> omain),
>> + intel_display_power_domain_str(dev_pri
>> v,
>> + power_d
>> omain),
>> power_domains-
>> >domain_use_count[power_domain]);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 95fdc8dbca31..a2010b30ca89 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9141,13 +9141,25 @@ enum {
>> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
>> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
>> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
>> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
>> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
>> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
>> #define ICL_PW_CTL_IDX_AUX_TBT4 11
>> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
>> #define ICL_PW_CTL_IDX_AUX_TBT3 10
>> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
>> #define ICL_PW_CTL_IDX_AUX_TBT2 9
>> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
>> #define ICL_PW_CTL_IDX_AUX_TBT1 8
>> +#define TGL_PW_CTL_IDX_AUX_TC6 8
>> +#define TGL_PW_CTL_IDX_AUX_TC5 7
>> +#define TGL_PW_CTL_IDX_AUX_TC4 6
>> #define ICL_PW_CTL_IDX_AUX_F 5
>> +#define TGL_PW_CTL_IDX_AUX_TC3 5
>> #define ICL_PW_CTL_IDX_AUX_E 4
>> +#define TGL_PW_CTL_IDX_AUX_TC2 4
>> #define ICL_PW_CTL_IDX_AUX_D 3
>> +#define TGL_PW_CTL_IDX_AUX_TC1 3
>> #define ICL_PW_CTL_IDX_AUX_C 2
>> #define ICL_PW_CTL_IDX_AUX_B 1
>> #define ICL_PW_CTL_IDX_AUX_A 0
>> @@ -9155,9 +9167,15 @@ enum {
>> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
>> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
>> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
>> +#define TGL_PW_CTL_IDX_DDI_TC6 8
>> +#define TGL_PW_CTL_IDX_DDI_TC5 7
>> +#define TGL_PW_CTL_IDX_DDI_TC4 6
>> #define ICL_PW_CTL_IDX_DDI_F 5
>> +#define TGL_PW_CTL_IDX_DDI_TC3 5
>> #define ICL_PW_CTL_IDX_DDI_E 4
>> +#define TGL_PW_CTL_IDX_DDI_TC2 4
>> #define ICL_PW_CTL_IDX_DDI_D 3
>> +#define TGL_PW_CTL_IDX_DDI_TC1 3
>> #define ICL_PW_CTL_IDX_DDI_C 2
>> #define ICL_PW_CTL_IDX_DDI_B 1
>> #define ICL_PW_CTL_IDX_DDI_A 0
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^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (9 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-07-01 17:54 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
` (20 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Mika Kahola <mika.kahola@intel.com>
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 33 ++++++++++++++++---
.../drm/i915/display/intel_display_power.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +-
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 20b2009cecc6..0c7d4a363deb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -36,18 +36,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
@@ -2357,11 +2363,17 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
* GEN 12: DDI_A-C
* - FBC
*/
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS | \
+ ICL_PW_4_POWER_DOMAINS)
/* VDSC/joining */
#define ICL_PW_3_POWER_DOMAINS ( \
ICL_PW_4_POWER_DOMAINS | \
@@ -2393,11 +2405,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
+ TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- /* TODO: TRANSCODER_D */ \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3779,7 +3791,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
{
.name = "power well 4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3789,7 +3801,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f81b769bc2e..79262a5bceb4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_D,
POWER_DOMAIN_PIPE_A_PANEL_FITTER,
POWER_DOMAIN_PIPE_B_PANEL_FITTER,
POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_D_PANEL_FITTER,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2010b30ca89..687b065216eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9132,7 +9132,8 @@ enum {
#define GLK_PW_CTL_IDX_DDI_A 1
#define SKL_PW_CTL_IDX_MISC_IO 0
-/* ICL - power wells */
+/* ICL/TGL - power wells */
+#define TGL_PW_CTL_IDX_PW_5 4
#define ICL_PW_CTL_IDX_PW_4 3
#define ICL_PW_CTL_IDX_PW_3 2
#define ICL_PW_CTL_IDX_PW_2 1
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
@ 2019-07-01 17:54 ` Ville Syrjälä
0 siblings, 0 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-07-01 17:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:20AM -0700, Lucas De Marchi wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Add power well 5 to support 4th pipe and transcoder on TGL.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 33 ++++++++++++++++---
> .../drm/i915/display/intel_display_power.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> 3 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 20b2009cecc6..0c7d4a363deb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -36,18 +36,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> return "PIPE_B";
> case POWER_DOMAIN_PIPE_C:
> return "PIPE_C";
> + case POWER_DOMAIN_PIPE_D:
> + return "PIPE_D";
> case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> return "PIPE_A_PANEL_FITTER";
> case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> return "PIPE_B_PANEL_FITTER";
> case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> return "PIPE_C_PANEL_FITTER";
> + case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> + return "PIPE_D_PANEL_FITTER";
> case POWER_DOMAIN_TRANSCODER_A:
> return "TRANSCODER_A";
> case POWER_DOMAIN_TRANSCODER_B:
> return "TRANSCODER_B";
> case POWER_DOMAIN_TRANSCODER_C:
> return "TRANSCODER_C";
> + case POWER_DOMAIN_TRANSCODER_D:
> + return "TRANSCODER_D";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> @@ -2357,11 +2363,17 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> * GEN 12: DDI_A-C
> * - FBC
> */
> -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> +#define TGL_PW_5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define ICL_PW_4_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_4_POWER_DOMAINS ( \
> + TGL_PW_5_POWER_DOMAINS | \
> + ICL_PW_4_POWER_DOMAINS)
I don't like mixing icl and tgl power wells like this. Makes it super
hard to figure out what goes where. So IMO do a clean split for these.
> /* VDSC/joining */
> #define ICL_PW_3_POWER_DOMAINS ( \
> ICL_PW_4_POWER_DOMAINS | \
> @@ -2393,11 +2405,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define TGL_PW_3_POWER_DOMAINS ( \
> - ICL_PW_4_POWER_DOMAINS | \
> + TGL_PW_4_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - /* TODO: TRANSCODER_D */ \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
> @@ -3779,7 +3791,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> {
> .name = "power well 4",
> - .domains = ICL_PW_4_POWER_DOMAINS,
> + .domains = TGL_PW_4_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3789,7 +3801,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> .hsw.irq_pipe_mask = BIT(PIPE_C),
> }
> },
> - /* TODO: power well 5 for pipe D */
> + {
> + .name = "power well 5",
> + .domains = TGL_PW_5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_D),
> + },
> + },
> };
>
> static int
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f81b769bc2e..79262a5bceb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -18,12 +18,15 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PIPE_A,
> POWER_DOMAIN_PIPE_B,
> POWER_DOMAIN_PIPE_C,
> + POWER_DOMAIN_PIPE_D,
> POWER_DOMAIN_PIPE_A_PANEL_FITTER,
> POWER_DOMAIN_PIPE_B_PANEL_FITTER,
> POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> + POWER_DOMAIN_PIPE_D_PANEL_FITTER,
> POWER_DOMAIN_TRANSCODER_A,
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> + POWER_DOMAIN_TRANSCODER_D,
> POWER_DOMAIN_TRANSCODER_EDP,
> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> POWER_DOMAIN_TRANSCODER_DSI_A,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2010b30ca89..687b065216eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9132,7 +9132,8 @@ enum {
> #define GLK_PW_CTL_IDX_DDI_A 1
> #define SKL_PW_CTL_IDX_MISC_IO 0
>
> -/* ICL - power wells */
> +/* ICL/TGL - power wells */
> +#define TGL_PW_CTL_IDX_PW_5 4
> #define ICL_PW_CTL_IDX_PW_4 3
> #define ICL_PW_CTL_IDX_PW_3 2
> #define ICL_PW_CTL_IDX_PW_2 1
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (10 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-27 19:16 ` Manasi Navare
` (2 more replies)
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
` (19 subsequent siblings)
31 siblings, 3 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: José Roberto de Souza <jose.souza@intel.com>
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
distinction clear and update vdsc code path.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0c7d4a363deb..15582841fefc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
return "TRANSCODER_EDP_VDSC";
+ case POWER_DOMAIN_TRANSCODER_A_VDSC:
+ return "TRANSCODER_A_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 79262a5bceb4..7761b493608a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -29,6 +29,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+ POWER_DOMAIN_TRANSCODER_A_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..0c75b408d6ba 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
- * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
- * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+ * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
+ * PW2. This requires
+ * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
+ * domain.
* For any other transcoder, VDSC/joining uses the power well associated
* with the pipe/transcoder in use. Hence another reference on the
* transcoder power domain will suffice.
*/
- if (cpu_transcoder == TRANSCODER_EDP)
+ if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_A_VDSC;
+ else if (cpu_transcoder == TRANSCODER_EDP)
return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
@ 2019-06-27 19:16 ` Manasi Navare
2019-06-27 19:28 ` Souza, Jose
2019-06-28 9:55 ` Ville Syrjälä
2 siblings, 0 replies; 61+ messages in thread
From: Manasi Navare @ 2019-06-27 19:16 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good to me.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> 3 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0c7d4a363deb..15582841fefc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> return "TRANSCODER_EDP";
> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> return "TRANSCODER_EDP_VDSC";
> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> + return "TRANSCODER_A_VDSC";
> case POWER_DOMAIN_TRANSCODER_DSI_A:
> return "TRANSCODER_DSI_A";
> case POWER_DOMAIN_TRANSCODER_DSI_C:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 79262a5bceb4..7761b493608a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_D,
> POWER_DOMAIN_TRANSCODER_EDP,
> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> + POWER_DOMAIN_TRANSCODER_A_VDSC,
> POWER_DOMAIN_TRANSCODER_DSI_A,
> POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..0c75b408d6ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
> + * PW2. This requires
> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
> + * domain.
> * For any other transcoder, VDSC/joining uses the power well associated
> * with the pipe/transcoder in use. Hence another reference on the
> * transcoder power domain will suffice.
> */
> - if (cpu_transcoder == TRANSCODER_EDP)
> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
2019-06-27 19:16 ` Manasi Navare
@ 2019-06-27 19:28 ` Souza, Jose
2019-06-27 19:30 ` Souza, Jose
2019-06-27 19:33 ` Manasi Navare
2019-06-28 9:55 ` Ville Syrjälä
2 siblings, 2 replies; 61+ messages in thread
From: Souza, Jose @ 2019-06-27 19:28 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> 3 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0c7d4a363deb..15582841fefc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> return "TRANSCODER_EDP";
> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> return "TRANSCODER_EDP_VDSC";
> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> + return "TRANSCODER_A_VDSC";
> case POWER_DOMAIN_TRANSCODER_DSI_A:
> return "TRANSCODER_DSI_A";
> case POWER_DOMAIN_TRANSCODER_DSI_C:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 79262a5bceb4..7761b493608a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_D,
> POWER_DOMAIN_TRANSCODER_EDP,
> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> + POWER_DOMAIN_TRANSCODER_A_VDSC,
> POWER_DOMAIN_TRANSCODER_DSI_A,
> POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..0c75b408d6ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.state->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power
> well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> power well
> + * PW2. This requires
> + *
> POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
> + * domain.
> * For any other transcoder, VDSC/joining uses the power well
> associated
> * with the pipe/transcoder in use. Hence another reference on
> the
> * transcoder power domain will suffice.
> */
> - if (cpu_transcoder == TRANSCODER_EDP)
> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder ==
> TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
This is missing the change adding POWER_DOMAIN_TRANSCODER_EDP_VDSC to
TGL_PW_2_POWER_DOMAINS.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-27 19:28 ` Souza, Jose
@ 2019-06-27 19:30 ` Souza, Jose
2019-06-27 19:33 ` Manasi Navare
1 sibling, 0 replies; 61+ messages in thread
From: Souza, Jose @ 2019-06-27 19:30 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Thu, 2019-06-27 at 12:28 -0700, José Roberto de Souza wrote:
> On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > On TGL the special EDP transcoder is gone and it should be handled
> > by
> > transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> > distinction clear and update vdsc code path.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> > drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++
> > ---
> > 3 files changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 0c7d4a363deb..15582841fefc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct
> > drm_i915_private *i915,
> > return "TRANSCODER_EDP";
> > case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > return "TRANSCODER_EDP_VDSC";
> > + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> > + return "TRANSCODER_A_VDSC";
> > case POWER_DOMAIN_TRANSCODER_DSI_A:
> > return "TRANSCODER_DSI_A";
> > case POWER_DOMAIN_TRANSCODER_DSI_C:
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index 79262a5bceb4..7761b493608a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_TRANSCODER_D,
> > POWER_DOMAIN_TRANSCODER_EDP,
> > POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > + POWER_DOMAIN_TRANSCODER_A_VDSC,
> > POWER_DOMAIN_TRANSCODER_DSI_A,
> > POWER_DOMAIN_TRANSCODER_DSI_C,
> > POWER_DOMAIN_PORT_DDI_A_LANES,
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ffec807b8960..0c75b408d6ba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct
> > intel_dp
> > *intel_dp,
> > enum intel_display_power_domain
> > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > > base.state->dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> > /*
> > - * On ICL VDSC/joining for eDP transcoder uses a separate power
> > well PW2
> > - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> > power well
> > + * PW2. This requires
> > + *
> > POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC
> > power
> > + * domain.
> > * For any other transcoder, VDSC/joining uses the power well
> > associated
> > * with the pipe/transcoder in use. Hence another reference on
> > the
> > * transcoder power domain will suffice.
> > */
> > - if (cpu_transcoder == TRANSCODER_EDP)
> > + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder ==
> > TRANSCODER_A)
> > + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> > + else if (cpu_transcoder == TRANSCODER_EDP)
> > return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > else
> > return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>
> This is missing the change adding POWER_DOMAIN_TRANSCODER_EDP_VDSC to
> TGL_PW_2_POWER_DOMAINS.
* TRANSCODER_A_VDSC *
Missing the change adding TRANSCODER_A_VDSC to TGL_PW_2_POWER_DOMAINS
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-27 19:28 ` Souza, Jose
2019-06-27 19:30 ` Souza, Jose
@ 2019-06-27 19:33 ` Manasi Navare
1 sibling, 0 replies; 61+ messages in thread
From: Manasi Navare @ 2019-06-27 19:33 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, De Marchi, Lucas
On Thu, Jun 27, 2019 at 07:28:15PM +0000, Souza, Jose wrote:
> On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > On TGL the special EDP transcoder is gone and it should be handled by
> > transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> > distinction clear and update vdsc code path.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> > drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> > 3 files changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 0c7d4a363deb..15582841fefc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct
> > drm_i915_private *i915,
> > return "TRANSCODER_EDP";
> > case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > return "TRANSCODER_EDP_VDSC";
> > + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> > + return "TRANSCODER_A_VDSC";
> > case POWER_DOMAIN_TRANSCODER_DSI_A:
> > return "TRANSCODER_DSI_A";
> > case POWER_DOMAIN_TRANSCODER_DSI_C:
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index 79262a5bceb4..7761b493608a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_TRANSCODER_D,
> > POWER_DOMAIN_TRANSCODER_EDP,
> > POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > + POWER_DOMAIN_TRANSCODER_A_VDSC,
> > POWER_DOMAIN_TRANSCODER_DSI_A,
> > POWER_DOMAIN_TRANSCODER_DSI_C,
> > POWER_DOMAIN_PORT_DDI_A_LANES,
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ffec807b8960..0c75b408d6ba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> > enum intel_display_power_domain
> > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >base.state->dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> > /*
> > - * On ICL VDSC/joining for eDP transcoder uses a separate power
> > well PW2
> > - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> > power well
> > + * PW2. This requires
> > + *
> > POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
> > + * domain.
> > * For any other transcoder, VDSC/joining uses the power well
> > associated
> > * with the pipe/transcoder in use. Hence another reference on
> > the
> > * transcoder power domain will suffice.
> > */
> > - if (cpu_transcoder == TRANSCODER_EDP)
> > + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder ==
> > TRANSCODER_A)
> > + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> > + else if (cpu_transcoder == TRANSCODER_EDP)
> > return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > else
> > return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>
>
> This is missing the change adding POWER_DOMAIN_TRANSCODER_EDP_VDSC to
> TGL_PW_2_POWER_DOMAINS.
You mean POWER_DOMAIN_TRANSCODER_A_VDSC?
Manasi
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
2019-06-27 19:16 ` Manasi Navare
2019-06-27 19:28 ` Souza, Jose
@ 2019-06-28 9:55 ` Ville Syrjälä
2019-06-28 16:31 ` Lucas De Marchi
2 siblings, 1 reply; 61+ messages in thread
From: Ville Syrjälä @ 2019-06-28 9:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> 3 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0c7d4a363deb..15582841fefc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> return "TRANSCODER_EDP";
> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> return "TRANSCODER_EDP_VDSC";
> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> + return "TRANSCODER_A_VDSC";
> case POWER_DOMAIN_TRANSCODER_DSI_A:
> return "TRANSCODER_DSI_A";
> case POWER_DOMAIN_TRANSCODER_DSI_C:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 79262a5bceb4..7761b493608a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_D,
> POWER_DOMAIN_TRANSCODER_EDP,
> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> + POWER_DOMAIN_TRANSCODER_A_VDSC,
Two power domains for essentially the same thing seems a bit wasteful.
> POWER_DOMAIN_TRANSCODER_DSI_A,
> POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..0c75b408d6ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
> + * PW2. This requires
> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
> + * domain.
> * For any other transcoder, VDSC/joining uses the power well associated
> * with the pipe/transcoder in use. Hence another reference on the
> * transcoder power domain will suffice.
> */
> - if (cpu_transcoder == TRANSCODER_EDP)
> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-28 9:55 ` Ville Syrjälä
@ 2019-06-28 16:31 ` Lucas De Marchi
2019-07-01 17:32 ` Ville Syrjälä
0 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-28 16:31 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
>On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> On TGL the special EDP transcoder is gone and it should be handled by
>> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
>> distinction clear and update vdsc code path.
>>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
>> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
>> 3 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 0c7d4a363deb..15582841fefc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>> return "TRANSCODER_EDP";
>> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>> return "TRANSCODER_EDP_VDSC";
>> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
>> + return "TRANSCODER_A_VDSC";
>> case POWER_DOMAIN_TRANSCODER_DSI_A:
>> return "TRANSCODER_DSI_A";
>> case POWER_DOMAIN_TRANSCODER_DSI_C:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 79262a5bceb4..7761b493608a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_TRANSCODER_D,
>> POWER_DOMAIN_TRANSCODER_EDP,
>> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>> + POWER_DOMAIN_TRANSCODER_A_VDSC,
>
>Two power domains for essentially the same thing seems a bit wasteful.
just reuse the name then?
and on gen12+ check for TRANSCODER_A like below?
Lucas De Marchi
>
>> POWER_DOMAIN_TRANSCODER_DSI_A,
>> POWER_DOMAIN_TRANSCODER_DSI_C,
>> POWER_DOMAIN_PORT_DDI_A_LANES,
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index ffec807b8960..0c75b408d6ba 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>> enum intel_display_power_domain
>> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>> {
>> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>
>> /*
>> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
>> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
>> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
>> + * PW2. This requires
>> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
>> + * domain.
>> * For any other transcoder, VDSC/joining uses the power well associated
>> * with the pipe/transcoder in use. Hence another reference on the
>> * transcoder power domain will suffice.
>> */
>> - if (cpu_transcoder == TRANSCODER_EDP)
>> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
>> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
>> + else if (cpu_transcoder == TRANSCODER_EDP)
>> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>> else
>> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-06-28 16:31 ` Lucas De Marchi
@ 2019-07-01 17:32 ` Ville Syrjälä
2019-07-01 17:36 ` Ville Syrjälä
2019-07-08 21:05 ` Lucas De Marchi
0 siblings, 2 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-07-01 17:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Jun 28, 2019 at 09:31:04AM -0700, Lucas De Marchi wrote:
> On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
> >On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> >> From: José Roberto de Souza <jose.souza@intel.com>
> >>
> >> On TGL the special EDP transcoder is gone and it should be handled by
> >> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> >> distinction clear and update vdsc code path.
> >>
> >> Cc: Imre Deak <imre.deak@intel.com>
> >> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> >> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> >> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> >> 3 files changed, 11 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> >> index 0c7d4a363deb..15582841fefc 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> >> return "TRANSCODER_EDP";
> >> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> >> return "TRANSCODER_EDP_VDSC";
> >> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> >> + return "TRANSCODER_A_VDSC";
> >> case POWER_DOMAIN_TRANSCODER_DSI_A:
> >> return "TRANSCODER_DSI_A";
> >> case POWER_DOMAIN_TRANSCODER_DSI_C:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> >> index 79262a5bceb4..7761b493608a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> >> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> >> POWER_DOMAIN_TRANSCODER_D,
> >> POWER_DOMAIN_TRANSCODER_EDP,
> >> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> >> + POWER_DOMAIN_TRANSCODER_A_VDSC,
> >
> >Two power domains for essentially the same thing seems a bit wasteful.
>
> just reuse the name then?
>
> and on gen12+ check for TRANSCODER_A like below?
That was my initial idea yes. In theory it would be nice to have fully
abstracted power domains but that would lead to a lot of bits getting
used. I suspect we might have to switch to using the kernel bitmask
stuff in that case. Not sure how many bits we have free ATM.
>
> Lucas De Marchi
>
> >
> >> POWER_DOMAIN_TRANSCODER_DSI_A,
> >> POWER_DOMAIN_TRANSCODER_DSI_C,
> >> POWER_DOMAIN_PORT_DDI_A_LANES,
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> index ffec807b8960..0c75b408d6ba 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> >> enum intel_display_power_domain
> >> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> >> {
> >> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
> >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>
> >> /*
> >> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> >> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> >> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
> >> + * PW2. This requires
> >> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
> >> + * domain.
> >> * For any other transcoder, VDSC/joining uses the power well associated
> >> * with the pipe/transcoder in use. Hence another reference on the
> >> * transcoder power domain will suffice.
> >> */
> >> - if (cpu_transcoder == TRANSCODER_EDP)
> >> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
> >> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
> >> + else if (cpu_transcoder == TRANSCODER_EDP)
> >> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> >> else
> >> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> >> --
> >> 2.21.0
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-07-01 17:32 ` Ville Syrjälä
@ 2019-07-01 17:36 ` Ville Syrjälä
2019-07-08 21:05 ` Lucas De Marchi
1 sibling, 0 replies; 61+ messages in thread
From: Ville Syrjälä @ 2019-07-01 17:36 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Jul 01, 2019 at 08:32:59PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 28, 2019 at 09:31:04AM -0700, Lucas De Marchi wrote:
> > On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
> > >On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> > >> From: José Roberto de Souza <jose.souza@intel.com>
> > >>
> > >> On TGL the special EDP transcoder is gone and it should be handled by
> > >> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> > >> distinction clear and update vdsc code path.
> > >>
> > >> Cc: Imre Deak <imre.deak@intel.com>
> > >> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
> > >> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> > >> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
> > >> 3 files changed, 11 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > >> index 0c7d4a363deb..15582841fefc 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > >> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> > >> return "TRANSCODER_EDP";
> > >> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > >> return "TRANSCODER_EDP_VDSC";
> > >> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
> > >> + return "TRANSCODER_A_VDSC";
> > >> case POWER_DOMAIN_TRANSCODER_DSI_A:
> > >> return "TRANSCODER_DSI_A";
> > >> case POWER_DOMAIN_TRANSCODER_DSI_C:
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > >> index 79262a5bceb4..7761b493608a 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > >> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
> > >> POWER_DOMAIN_TRANSCODER_D,
> > >> POWER_DOMAIN_TRANSCODER_EDP,
> > >> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > >> + POWER_DOMAIN_TRANSCODER_A_VDSC,
> > >
> > >Two power domains for essentially the same thing seems a bit wasteful.
> >
> > just reuse the name then?
> >
> > and on gen12+ check for TRANSCODER_A like below?
>
> That was my initial idea yes. In theory it would be nice to have fully
> abstracted power domains but that would lead to a lot of bits getting
> used. I suspect we might have to switch to using the kernel bitmask
> stuff in that case. Not sure how many bits we have free ATM.
I've also pondered about shaving off a few bits by special casing the
HSW panel fitter stuff in a similar fashion.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
2019-07-01 17:32 ` Ville Syrjälä
2019-07-01 17:36 ` Ville Syrjälä
@ 2019-07-08 21:05 ` Lucas De Marchi
1 sibling, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-07-08 21:05 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jul 01, 2019 at 08:32:59PM +0300, Ville Syrjälä wrote:
>On Fri, Jun 28, 2019 at 09:31:04AM -0700, Lucas De Marchi wrote:
>> On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
>> >On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
>> >> From: José Roberto de Souza <jose.souza@intel.com>
>> >>
>> >> On TGL the special EDP transcoder is gone and it should be handled by
>> >> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
>> >> distinction clear and update vdsc code path.
>> >>
>> >> Cc: Imre Deak <imre.deak@intel.com>
>> >> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
>> >> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
>> >> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ++++++++---
>> >> 3 files changed, 11 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> >> index 0c7d4a363deb..15582841fefc 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> >> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>> >> return "TRANSCODER_EDP";
>> >> case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>> >> return "TRANSCODER_EDP_VDSC";
>> >> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
>> >> + return "TRANSCODER_A_VDSC";
>> >> case POWER_DOMAIN_TRANSCODER_DSI_A:
>> >> return "TRANSCODER_DSI_A";
>> >> case POWER_DOMAIN_TRANSCODER_DSI_C:
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> >> index 79262a5bceb4..7761b493608a 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> >> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
>> >> POWER_DOMAIN_TRANSCODER_D,
>> >> POWER_DOMAIN_TRANSCODER_EDP,
>> >> POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>> >> + POWER_DOMAIN_TRANSCODER_A_VDSC,
>> >
>> >Two power domains for essentially the same thing seems a bit wasteful.
>>
>> just reuse the name then?
>>
>> and on gen12+ check for TRANSCODER_A like below?
>
>That was my initial idea yes. In theory it would be nice to have fully
>abstracted power domains but that would lead to a lot of bits getting
>used. I suspect we might have to switch to using the kernel bitmask
>stuff in that case. Not sure how many bits we have free ATM.
we are currently using 45 and with TGL we will jump to 60. 4 more until
we have to swap out that logic in favor of bitmap.h
Lucas De Marchi
>
>>
>> Lucas De Marchi
>>
>> >
>> >> POWER_DOMAIN_TRANSCODER_DSI_A,
>> >> POWER_DOMAIN_TRANSCODER_DSI_C,
>> >> POWER_DOMAIN_PORT_DDI_A_LANES,
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> >> index ffec807b8960..0c75b408d6ba 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> >> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>> >> enum intel_display_power_domain
>> >> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>> >> {
>> >> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.state->dev);
>> >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> >>
>> >> /*
>> >> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
>> >> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
>> >> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
>> >> + * PW2. This requires
>> >> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC power
>> >> + * domain.
>> >> * For any other transcoder, VDSC/joining uses the power well associated
>> >> * with the pipe/transcoder in use. Hence another reference on the
>> >> * transcoder power domain will suffice.
>> >> */
>> >> - if (cpu_transcoder == TRANSCODER_EDP)
>> >> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
>> >> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
>> >> + else if (cpu_transcoder == TRANSCODER_EDP)
>> >> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>> >> else
>> >> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>> >> --
>> >> 2.21.0
>> >>
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> >--
>> >Ville Syrjälä
>> >Intel
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 13/28] drm/i915/tgl: Add new pll ids
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (11 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 23:12 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 14/28] drm/i915/tgl: Add pll manager Lucas De Marchi
` (18 subsequent siblings)
31 siblings, 1 reply; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d0570414f3d1..b943f5e3f143 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -110,35 +110,48 @@ enum intel_dpll_id {
/**
- * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+ * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
*/
DPLL_ID_ICL_DPLL0 = 0,
/**
- * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+ * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
/**
- * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+ * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
*/
DPLL_ID_ICL_TBTPLL = 2,
/**
- * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+ * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+ * TGL TC PLL 1 port 1 (TC1)
*/
DPLL_ID_ICL_MGPLL1 = 3,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+ * TGL TC PLL 1 port 2 (TC2)
*/
DPLL_ID_ICL_MGPLL2 = 4,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+ * TGL TC PLL 1 port 3 (TC3)
*/
DPLL_ID_ICL_MGPLL3 = 5,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+ * TGL TC PLL 1 port 4 (TC4)
*/
DPLL_ID_ICL_MGPLL4 = 6,
+ /**
+ * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+ */
+ DPLL_ID_TGL_MGPLL5 = 7,
+ /**
+ * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+ */
+ DPLL_ID_TGL_MGPLL6 = 8,
};
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
struct intel_dpll_hw_state {
/* i9xx, pch plls */
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 13/28] drm/i915/tgl: Add new pll ids
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
@ 2019-06-26 23:12 ` Srivatsa, Anusha
0 siblings, 0 replies; 61+ messages in thread
From: Srivatsa, Anusha @ 2019-06-26 23:12 UTC (permalink / raw)
To: intel-gfx; +Cc: De Marchi, Lucas
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Tuesday, June 25, 2019 10:54 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [Intel-gfx] [PATCH 13/28] drm/i915/tgl: Add new pll ids
>
>From: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
>Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL changed,
>but most registers remained the same, like MGPLL5_ENABLE, MGPLL6_ENABLE.
>So continue to use the name from ICL.
>
>Cc: Madhav Chauhan <madhav.chauhan@intel.com>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++++++++++++++----
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>index d0570414f3d1..b943f5e3f143 100644
>--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>@@ -110,35 +110,48 @@ enum intel_dpll_id {
>
>
> /**
>- * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
>+ * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
> */
> DPLL_ID_ICL_DPLL0 = 0,
> /**
>- * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
>+ * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
> */
> DPLL_ID_ICL_DPLL1 = 1,
> /**
>- * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
>+ * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
> */
> DPLL_ID_ICL_TBTPLL = 2,
> /**
>- * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
>+ * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
>+ * TGL TC PLL 1 port 1 (TC1)
> */
> DPLL_ID_ICL_MGPLL1 = 3,
> /**
> * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
>+ * TGL TC PLL 1 port 2 (TC2)
> */
> DPLL_ID_ICL_MGPLL2 = 4,
> /**
> * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
>+ * TGL TC PLL 1 port 3 (TC3)
> */
> DPLL_ID_ICL_MGPLL3 = 5,
> /**
> * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
>+ * TGL TC PLL 1 port 4 (TC4)
> */
> DPLL_ID_ICL_MGPLL4 = 6,
>+ /**
>+ * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
>+ */
>+ DPLL_ID_TGL_MGPLL5 = 7,
>+ /**
>+ * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
>+ */
>+ DPLL_ID_TGL_MGPLL6 = 8,
> };
>-#define I915_NUM_PLLS 7
>+
>+#define I915_NUM_PLLS 9
>
> struct intel_dpll_hw_state {
> /* i9xx, pch plls */
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 14/28] drm/i915/tgl: Add pll manager
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (12 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
` (17 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2d4e7b9a7b9d..f83add4fe94d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3239,6 +3239,20 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info tgl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ /* TODO: Add typeC plls */
+ { },
+};
+
+static const struct intel_dpll_mgr tgl_pll_mgr = {
+ .dpll_info = tgl_plls,
+ .get_dpll = icl_get_dpll,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3252,7 +3266,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ dpll_mgr = &tgl_pll_mgr;
+ else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (13 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 14/28] drm/i915/tgl: Add pll manager Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
` (16 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
include/drm/i915_component.h | 2 +-
include/drm/i915_drm.h | 3 +++
5 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b717562fcce5..84b0a58d1f68 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4293,6 +4293,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_F_IO;
break;
+ case PORT_G:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_G_IO;
+ break;
+ case PORT_H:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_H_IO;
+ break;
+ case PORT_I:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_I_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9b13c62d3d53..4d5832a3bf45 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6611,6 +6611,9 @@ enum display_fia intel_tc_port_to_fia(struct drm_i915_private *dev_priv,
case PORT_TC3:
case PORT_TC4:
return FIA_2;
+ case PORT_TC5:
+ case PORT_TC6:
+ return FIA_3;
default:
WARN_ON(tc_port);
return FIA_1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index dc9e4615246e..09e517068262 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -189,6 +189,8 @@ enum tc_port {
PORT_TC2,
PORT_TC3,
PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
I915_MAX_TC_PORTS
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index dcb95bd9dee6..55c3b123581b 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,7 +34,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 6
+#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7523e9a7b6e2..eb30062359d1 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -109,6 +109,9 @@ enum port {
PORT_D,
PORT_E,
PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
I915_MAX_PORTS
};
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (14 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
` (15 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 687b065216eb..da708286d452 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9708,9 +9708,11 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
(port) + 10))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \
+ (port) + 10))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 + 21))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (15 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
` (14 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 ++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 09e517068262..b5d6ae953d0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
GPIOK,
GPIOL,
GPIOM,
+ GPION,
+ GPIOO,
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd5af47..b42c79aea61a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+ [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+ [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ return &gmbus_pins_tgp[pin];
+ else if (HAS_PCH_MCC(dev_priv))
return &gmbus_pins_mcc[pin];
else if (HAS_PCH_ICP(dev_priv))
return &gmbus_pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_tgp);
+ else if (HAS_PCH_MCC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_mcc);
else if (HAS_PCH_ICP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da708286d452..51b589fe651a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3256,8 +3256,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
#define GMBUS_PIN_12_TC4_ICP 12
+#define GMBUS_PIN_13_TC5_TGP 13
+#define GMBUS_PIN_14_TC6_TGP 14
-#define GMBUS_NUM_PINS 13 /* including 0 */
+#define GMBUS_NUM_PINS 15 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (16 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 19/28] drm/i915/tgl: select correct bit for port select Lucas De Marchi
` (13 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Create a helper function to get ddc pin according to port number.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..3b33e7626d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return ddc_pin;
}
+static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (intel_port_is_combophy(dev_priv, port))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_port_is_tc(dev_priv, port))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
+
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
return info->alternate_ddc_pin;
}
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
+ else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 19/28] drm/i915/tgl: select correct bit for port select
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (17 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 20/28] drm/i915/tgl: Add third combophy offset Lucas De Marchi
` (12 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 5 +++
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 84b0a58d1f68..0a123d677619 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1770,7 +1770,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- temp |= TRANS_DDI_SELECT_PORT(port);
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+ else
+ temp |= TRANS_DDI_SELECT_PORT(port);
switch (crtc_state->pipe_bpp) {
case 18:
@@ -1850,8 +1853,14 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
u32 val = I915_READ(reg);
- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
- val |= TRANS_DDI_PORT_NONE;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ } else {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ val |= TRANS_DDI_PORT_NONE;
+ }
I915_WRITE(reg, val);
if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2003,10 +2012,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
mst_pipe_mask = 0;
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
+ unsigned int port_mask, ddi_select;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ port_mask = TGL_TRANS_DDI_PORT_MASK;
+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+ } else {
+ port_mask = TRANS_DDI_PORT_MASK;
+ ddi_select = TRANS_DDI_SELECT_PORT(port);
+ }
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+ if ((tmp & port_mask) != ddi_select)
continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2122,9 +2140,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_PORT(port));
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
+ }
}
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2132,9 +2155,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_DISABLED);
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
+ }
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 51b589fe651a..cd52b34dad45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9364,8 +9364,10 @@ enum skl_power_gate {
#define TRANS_DDI_FUNC_ENABLE (1 << 31)
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
#define TRANS_DDI_PORT_MASK (7 << 28)
+#define TGL_TRANS_DDI_PORT_MASK (0xf << 27)
#define TRANS_DDI_PORT_SHIFT 28
#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
+#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << 27)
#define TRANS_DDI_PORT_NONE (0 << 28)
#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
@@ -9576,6 +9578,9 @@ enum skl_power_gate {
/* For each transcoder, we need to select the corresponding port clock */
#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
+#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
+#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
+
#define CDCLK_FREQ _MMIO(0x46200)
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 20/28] drm/i915/tgl: Add third combophy offset
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (18 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 19/28] drm/i915/tgl: select correct bit for port select Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
` (11 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
TGL has 3 combo-phy ports. This patch adds offset of third port to
combo-phy port register macros.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd52b34dad45..64ff887275a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1789,12 +1789,14 @@ enum i915_power_well_id {
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
/*
- * CNL/ICL Port/COMBO-PHY Registers
+ * CNL/ICL/TGL Port/COMBO-PHY Registers
*/
#define _ICL_COMBOPHY_A 0x162000
#define _ICL_COMBOPHY_B 0x6C000
+#define _TGL_COMBOPHY_C 0x160000
#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
- _ICL_COMBOPHY_B)
+ _ICL_COMBOPHY_B, \
+ _TGL_COMBOPHY_C)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (19 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 20/28] drm/i915/tgl: Add third combophy offset Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
` (10 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4d5832a3bf45..72bd85e98b8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6565,10 +6565,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
if (port == PORT_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
return port <= PORT_C;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_GEN(dev_priv, 11))
return port <= PORT_B;
return false;
@@ -6576,7 +6576,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port >= PORT_D && port <= PORT_I;
+
+ if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
@@ -6587,6 +6590,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
if (!intel_port_is_tc(dev_priv, port))
return PORT_TC_NONE;
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port - PORT_D;
+
return port - PORT_C;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (20 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
` (9 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 72bd85e98b8d..adbcce3b05b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15150,12 +15150,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ } else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (IS_GEN(dev_priv, 11)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (21 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
` (8 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar, Lucas De Marchi
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 ++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..a08bc4f617c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
};
+static const u8 tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+ [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+ [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+ [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+ [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+ [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+ [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_MCC(dev_priv)) {
+ if (HAS_PCH_TGP(dev_priv)) {
+ ddc_pin_map = tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+ } else if (HAS_PCH_MCC(dev_priv)) {
ddc_pin_map = mcc_ddc_pin_map;
n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_F,
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
+ TGL_DDC_BUS_DDI_C,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
ICL_DDC_BUS_PORT_4,
+ TGL_DDC_BUS_PORT_5,
+ TGL_DDC_BUS_PORT_6,
MCC_DDC_BUS_DDI_A = 0x1,
MCC_DDC_BUS_DDI_B,
MCC_DDC_BUS_DDI_C = 0x4,
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (22 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 25/28] drm/i915/gen12: MBUS B credit change Lucas De Marchi
` (7 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ++++++++---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 15582841fefc..fb0706f92b29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -446,6 +446,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -455,9 +456,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl */
- if (IS_ICELAKE(dev_priv) &&
- pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
+ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
!intel_bios_is_port_edp(dev_priv, port)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64ff887275a0..dc42a0ea5f13 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9233,9 +9233,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A 0x162398
#define _ICL_AUX_ANAOVRD1_B 0x6C398
+#define _TGL_AUX_ANAOVRD1_C 0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 25/28] drm/i915/gen12: MBUS B credit change
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (23 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
` (6 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adbcce3b05b0..1e8be9345b4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6310,8 +6310,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
u32 val;
val = MBUS_DBOX_A_CREDIT(2);
- val |= MBUS_DBOX_BW_CREDIT(1);
- val |= MBUS_DBOX_B_CREDIT(8);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(12);
+ } else {
+ val |= MBUS_DBOX_BW_CREDIT(1);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ }
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (24 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 25/28] drm/i915/gen12: MBUS B credit change Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 27/28] drm/i915/tgl: Add DPLL registers Lucas De Marchi
` (5 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so just check for IS_TIGERLAKE() inside it.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fb0706f92b29..a8d3b0541edb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -451,8 +451,10 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+ if (!IS_TIGERLAKE(dev_priv)) {
+ val = I915_READ(ICL_PORT_CL_DW12(port));
+ I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+ }
hsw_wait_for_power_well_enable(dev_priv, power_well);
@@ -479,8 +481,10 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+ if (!IS_TIGERLAKE(dev_priv)) {
+ val = I915_READ(ICL_PORT_CL_DW12(port));
+ I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+ }
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 27/28] drm/i915/tgl: Add DPLL registers
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (25 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
` (4 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 15 ++++++++++++
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f83add4fe94d..295661a3f697 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2932,8 +2932,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
ret = true;
out:
@@ -2961,10 +2966,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+ cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
- I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
- I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
- POSTING_READ(ICL_DPLL_CFGCR1(id));
+ I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+ I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+ POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc42a0ea5f13..96017207e809 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -9945,6 +9946,20 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+#define _TGL_TBTPLL_CFGCR0 0x16429C
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1)
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
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^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (26 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 27/28] drm/i915/tgl: Add DPLL registers Lucas De Marchi
@ 2019-06-25 17:54 ` Lucas De Marchi
2019-06-26 0:00 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake Patchwork
` (3 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Lucas De Marchi @ 2019-06-25 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: José Roberto de Souza <jose.souza@intel.com>
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 295661a3f697..1e8fd0e2f37d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2530,8 +2530,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params.kdiv) |
- DPLL_CFGCR1_PDIV(pll_params.pdiv) |
- DPLL_CFGCR1_CENTRAL_FREQ_8400;
+ DPLL_CFGCR1_PDIV(pll_params.pdiv);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ else
+ cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96017207e809..3744a7b3a045 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9934,6 +9934,7 @@ enum skl_power_gate {
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
#define _ICL_DPLL0_CFGCR0 0x164000
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 61+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (27 preceding siblings ...)
2019-06-25 17:54 ` [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
@ 2019-06-26 0:00 ` Patchwork
2019-06-26 0:54 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
31 siblings, 0 replies; 61+ messages in thread
From: Patchwork @ 2019-06-26 0:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
11acbbf944b4 drm/i915: Add modular FIA
68a37855e4a8 drm/i915: rework reading pipe disable fuses
8deb258dbdfa drm/i915: Add 4th pipe and transcoder
97e5552d3dda drm/i915/tgl: add initial Tiger Lake definitions
d37ae0840709 drm/i915/tgl: Introduce Tiger Lake PCH
3fd4f1dc5286 drm/i915/tgl: Add TGL PCH detection in virtualized environment
766b92a4b2f2 drm/i915/tgl: Add TGL PCI IDs
-:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#32: FILE: include/drm/i915_pciids.h:586:
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#32: FILE: include/drm/i915_pciids.h:586:
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
total: 1 errors, 0 warnings, 1 checks, 21 lines checked
395ace571e5f x86/gpu: add TGL stolen memory support
8970927b20d1 drm/i915/tgl: Check if pipe D is fused
66ee79950737 drm/i915/tgl: Add power well support
4f73b6dd1f06 drm/i915/tgl: Add power well to support 4th pipe
6385567b0fae drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
0f07f1b15921 drm/i915/tgl: Add new pll ids
3832dc4784d1 drm/i915/tgl: Add pll manager
288f822662c0 drm/i915/tgl: Add additional ports for Tiger Lake
30da2d6e342c drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9711:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \
+ (port) + 10))
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9713:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 + 21))
total: 0 errors, 0 warnings, 2 checks, 14 lines checked
222d322189e1 drm/i915/tgl: Add gmbus gpio pin to port mapping
1c10181bd3f8 drm/i915/tgl: port to ddc pin mapping
f478ac4c8a3b drm/i915/tgl: select correct bit for port select
01cf9f0351e2 drm/i915/tgl: Add third combophy offset
aaa5baacdec1 drm/i915/tgl: extend intel_port_is_combophy/tc
a62421eb814e drm/i915/tgl: init ddi port A-C for Tiger Lake
233d6f91e009 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
ca7dac50ecf6 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
e6fa903800d4 drm/i915/gen12: MBUS B credit change
848e93a32472 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
5acfca8cab42 drm/i915/tgl: Add DPLL registers
a2fb3635e01b drm/i915/tgl: Update DPLL clock reference register
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* ✓ Fi.CI.BAT: success for Initial support for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (28 preceding siblings ...)
2019-06-26 0:00 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake Patchwork
@ 2019-06-26 0:54 ` Patchwork
2019-06-26 1:43 ` [PATCH 00/28] " Souza, Jose
2019-06-26 5:10 ` ✓ Fi.CI.IGT: success for " Patchwork
31 siblings, 0 replies; 61+ messages in thread
From: Patchwork @ 2019-06-26 0:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13424
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/
Known issues
------------
Here are the changes found in Patchwork_13424 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_create@basic:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-u2/igt@gem_exec_create@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-icl-u2/igt@gem_exec_create@basic.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [DMESG-WARN][5] ([fdo#106387]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@basic-default:
- fi-icl-guc: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (51 -> 45)
------------------------------
Additional (2): fi-gdg-551 fi-bwr-2160
Missing (8): fi-ilk-m540 fi-skl-gvtdvm fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6351 -> Patchwork_13424
CI_DRM_6351: 841a5e9b5d0b617cea39d2de4492cf3474d3f555 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13424: a2fb3635e01b3835f5b3a2bea3ba96c1df6c9bad @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a2fb3635e01b drm/i915/tgl: Update DPLL clock reference register
5acfca8cab42 drm/i915/tgl: Add DPLL registers
848e93a32472 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
e6fa903800d4 drm/i915/gen12: MBUS B credit change
ca7dac50ecf6 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
233d6f91e009 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
a62421eb814e drm/i915/tgl: init ddi port A-C for Tiger Lake
aaa5baacdec1 drm/i915/tgl: extend intel_port_is_combophy/tc
01cf9f0351e2 drm/i915/tgl: Add third combophy offset
f478ac4c8a3b drm/i915/tgl: select correct bit for port select
1c10181bd3f8 drm/i915/tgl: port to ddc pin mapping
222d322189e1 drm/i915/tgl: Add gmbus gpio pin to port mapping
30da2d6e342c drm/i915/tgl: update ddi/tc clock_off bits
288f822662c0 drm/i915/tgl: Add additional ports for Tiger Lake
3832dc4784d1 drm/i915/tgl: Add pll manager
0f07f1b15921 drm/i915/tgl: Add new pll ids
6385567b0fae drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
4f73b6dd1f06 drm/i915/tgl: Add power well to support 4th pipe
66ee79950737 drm/i915/tgl: Add power well support
8970927b20d1 drm/i915/tgl: Check if pipe D is fused
395ace571e5f x86/gpu: add TGL stolen memory support
766b92a4b2f2 drm/i915/tgl: Add TGL PCI IDs
3fd4f1dc5286 drm/i915/tgl: Add TGL PCH detection in virtualized environment
d37ae0840709 drm/i915/tgl: Introduce Tiger Lake PCH
97e5552d3dda drm/i915/tgl: add initial Tiger Lake definitions
8deb258dbdfa drm/i915: Add 4th pipe and transcoder
68a37855e4a8 drm/i915: rework reading pipe disable fuses
11acbbf944b4 drm/i915: Add modular FIA
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 00/28] Initial support for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (29 preceding siblings ...)
2019-06-26 0:54 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-06-26 1:43 ` Souza, Jose
2019-06-26 5:10 ` ✓ Fi.CI.IGT: success for " Patchwork
31 siblings, 0 replies; 61+ messages in thread
From: Souza, Jose @ 2019-06-26 1:43 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
s/Initial support for Tiger Lake/Warning: tigers inside
On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
> Basic pumbling to add Tiger Lake platform to i915, support for the
> 4th
> pipe, additional combo phy, power well definitions, clock changes,
> DDI
> changes and registers moving around.
> More to come soon.
>
> Anusha Srivatsa (1):
> drm/i915: Add modular FIA
>
> Daniele Ceraolo Spurio (1):
> drm/i915/tgl: add initial Tiger Lake definitions
>
> Imre Deak (1):
> drm/i915/tgl: Add power well support
>
> José Roberto de Souza (3):
> drm/i915/tgl: Check if pipe D is fused
> drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
> drm/i915/tgl: Update DPLL clock reference register
>
> Lucas De Marchi (6):
> drm/i915: rework reading pipe disable fuses
> drm/i915: Add 4th pipe and transcoder
> drm/i915/tgl: Add TGL PCI IDs
> drm/i915/tgl: apply Display WA #1178 to fix type C dongles
> drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
> drm/i915/tgl: Add DPLL registers
>
> Mahesh Kumar (9):
> drm/i915/tgl: Add TGL PCH detection in virtualized environment
> drm/i915/tgl: update ddi/tc clock_off bits
> drm/i915/tgl: Add gmbus gpio pin to port mapping
> drm/i915/tgl: port to ddc pin mapping
> drm/i915/tgl: select correct bit for port select
> drm/i915/tgl: Add third combophy offset
> drm/i915/tgl: extend intel_port_is_combophy/tc
> drm/i915/tgl: init ddi port A-C for Tiger Lake
> drm/i915/tgl: Add vbt value mapping for DDC Bus pin
>
> Michel Thierry (1):
> x86/gpu: add TGL stolen memory support
>
> Mika Kahola (1):
> drm/i915/tgl: Add power well to support 4th pipe
>
> Radhakrishna Sripada (1):
> drm/i915/tgl: Introduce Tiger Lake PCH
>
> Rodrigo Vivi (1):
> drm/i915/gen12: MBUS B credit change
>
> Vandita Kulkarni (3):
> drm/i915/tgl: Add new pll ids
> drm/i915/tgl: Add pll manager
> drm/i915/tgl: Add additional ports for Tiger Lake
>
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/display/intel_bios.c | 17 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 69 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 64 ++-
> drivers/gpu/drm/i915/display/intel_display.h | 14 +
> .../drm/i915/display/intel_display_power.c | 522
> +++++++++++++++++-
> .../drm/i915/display/intel_display_power.h | 30 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 20 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/i915_drv.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_pci.c | 31 ++
> drivers/gpu/drm/i915/i915_reg.h | 81 ++-
> drivers/gpu/drm/i915/intel_device_info.c | 40 +-
> drivers/gpu/drm/i915/intel_device_info.h | 3 +
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> include/drm/i915_component.h | 2 +-
> include/drm/i915_drm.h | 3 +
> include/drm/i915_pciids.h | 10 +
> 25 files changed, 940 insertions(+), 112 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 61+ messages in thread* ✓ Fi.CI.IGT: success for Initial support for Tiger Lake
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
` (30 preceding siblings ...)
2019-06-26 1:43 ` [PATCH 00/28] " Souza, Jose
@ 2019-06-26 5:10 ` Patchwork
31 siblings, 0 replies; 61+ messages in thread
From: Patchwork @ 2019-06-26 5:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Initial support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6351_full -> Patchwork_13424_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13424_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-internal-10ms:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl1/igt@gem_eio@in-flight-internal-10ms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-apl6/igt@gem_eio@in-flight-internal-10ms.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@gem_exec_balancer@smoke.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb5/igt@gem_exec_balancer@smoke.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-hsw: [PASS][5] -> [DMESG-WARN][6] ([fdo#110789] / [fdo#110913 ]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-glk6/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
* igt@gem_persistent_relocs@forked-thrash-inactive:
- shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([fdo#110913 ])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@gem_persistent_relocs@forked-thrash-inactive.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb3/igt@gem_persistent_relocs@forked-thrash-inactive.html
* igt@gem_softpin@overlap:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#110789] / [fdo#110913 ])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb7/igt@gem_softpin@overlap.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-snb7/igt@gem_softpin@overlap.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-hsw: [PASS][15] -> [SKIP][16] ([fdo#109271]) +12 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#103313] / [fdo#105345])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl1/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-kbl2/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#105363])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([fdo#110913 ])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-apl: [PASS][29] -> [INCOMPLETE][30] ([fdo#103927])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl5/igt@kms_rotation_crc@sprite-rotation-270.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-apl7/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_sysfs_edid_timing:
- shard-hsw: [PASS][31] -> [FAIL][32] ([fdo#100047])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@kms_sysfs_edid_timing.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw1/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@gem_eio@context-create:
- shard-hsw: [DMESG-WARN][33] ([fdo#110789] / [fdo#110913 ]) -> [PASS][34] +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@gem_eio@context-create.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw5/igt@gem_eio@context-create.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [DMESG-WARN][35] ([fdo#110913 ]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl2/igt@gem_eio@in-flight-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-apl2/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@wait-wedge-1us:
- shard-kbl: [DMESG-WARN][37] ([fdo#110913 ]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl7/igt@gem_eio@wait-wedge-1us.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-kbl3/igt@gem_eio@wait-wedge-1us.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd:
- shard-apl: [INCOMPLETE][39] ([fdo#103927]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl2/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-apl3/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-snb: [DMESG-WARN][41] ([fdo#110789] / [fdo#110913 ]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-snb7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-skl: [DMESG-WARN][43] ([fdo#110913 ]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-glk: [DMESG-WARN][45] ([fdo#110913 ]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_rpm@universal-planes-dpms:
- shard-hsw: [INCOMPLETE][47] ([fdo#103540] / [fdo#107807]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw5/igt@i915_pm_rpm@universal-planes-dpms.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw1/igt@i915_pm_rpm@universal-planes-dpms.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][49] ([fdo#110741]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-hsw: [SKIP][51] ([fdo#109271]) -> [PASS][52] +21 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][53] ([fdo#105363]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [FAIL][55] ([fdo#103060]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk9/igt@kms_flip@2x-modeset-vs-vblank-race.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-glk4/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-iclb: [FAIL][57] ([fdo#105363]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][59] ([fdo#103167]) -> [PASS][60] +7 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-iclb: [DMESG-WARN][61] ([fdo#110913 ]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [INCOMPLETE][63] ([fdo#104108]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][65] ([fdo#108145]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][67] ([fdo#103166]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][69] ([fdo#109642]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][71] ([fdo#108341]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_psr@no_drrs.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb3/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][75] ([fdo#99912]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@kms_setmode@basic.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-hsw1/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][77] ([fdo#99912]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl7/igt@kms_setmode@basic.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-query-busy-hang:
- shard-iclb: [INCOMPLETE][79] ([fdo#107713]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb7/igt@kms_vblank@pipe-a-query-busy-hang.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-iclb7/igt@kms_vblank@pipe-a-query-busy-hang.html
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- shard-snb: [SKIP][81] ([fdo#109271]) -> [PASS][82] +9 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-snb7/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
#### Warnings ####
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-snb: [SKIP][83] ([fdo#109271]) -> [SKIP][84] ([fdo#109271] / [fdo#109278])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/shard-snb7/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6351 -> Patchwork_13424
CI_DRM_6351: 841a5e9b5d0b617cea39d2de4492cf3474d3f555 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13424: a2fb3635e01b3835f5b3a2bea3ba96c1df6c9bad @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13424/
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Intel-gfx@lists.freedesktop.org
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