From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/15] riscv: provide a flat entry loader Date: Tue, 13 Aug 2019 17:47:38 +0200 [thread overview] Message-ID: <20190813154747.24256-7-hch@lst.de> (raw) In-Reply-To: <20190813154747.24256-1-hch@lst.de> This allows just loading the kernel at a pre-set address without qemu going bonkers trying to map the ELF file. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/Makefile | 13 +++++++++---- arch/riscv/boot/Makefile | 7 ++++++- arch/riscv/boot/loader.S | 8 ++++++++ arch/riscv/boot/loader.lds | 14 ++++++++++++++ 4 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/boot/loader.S create mode 100644 arch/riscv/boot/loader.lds diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 7a117be8297c..aa9e377400e2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -80,13 +80,18 @@ PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ -all: Image.gz +ifeq ($(CONFIG_M_MODE),y) +KBUILD_IMAGE := $(boot)/loader +else +KBUILD_IMAGE := $(boot)/Image.gz +endif +BOOT_TARGETS := Image Image.gz loader -Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ +all: $(notdir $(KBUILD_IMAGE)) -Image.%: Image +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + @$(kecho) ' Kernel: $(boot)/$@ is ready' zinstall install: $(Q)$(MAKE) $(build)=$(boot) $@ diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile index 0990a9fdbe5d..32d2addeddba 100644 --- a/arch/riscv/boot/Makefile +++ b/arch/riscv/boot/Makefile @@ -16,7 +16,7 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image +targets := Image loader $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) @@ -24,6 +24,11 @@ $(obj)/Image: vmlinux FORCE $(obj)/Image.gz: $(obj)/Image FORCE $(call if_changed,gzip) +loader.o: $(src)/loader.S $(obj)/Image + +$(obj)/loader: $(obj)/loader.o $(obj)/Image FORCE + $(Q)$(LD) -T $(src)/loader.lds -o $@ $(obj)/loader.o + install: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" diff --git a/arch/riscv/boot/loader.S b/arch/riscv/boot/loader.S new file mode 100644 index 000000000000..5586e2610dbb --- /dev/null +++ b/arch/riscv/boot/loader.S @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + + .align 4 + .section .payload, "ax", %progbits + .globl _start +_start: + .incbin "arch/riscv/boot/Image" + diff --git a/arch/riscv/boot/loader.lds b/arch/riscv/boot/loader.lds new file mode 100644 index 000000000000..da9efd57bf44 --- /dev/null +++ b/arch/riscv/boot/loader.lds @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + + .payload : { + *(.payload) + . = ALIGN(8); + } +} -- 2.20.1
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From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/15] riscv: provide a flat entry loader Date: Tue, 13 Aug 2019 17:47:38 +0200 [thread overview] Message-ID: <20190813154747.24256-7-hch@lst.de> (raw) In-Reply-To: <20190813154747.24256-1-hch@lst.de> This allows just loading the kernel at a pre-set address without qemu going bonkers trying to map the ELF file. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/Makefile | 13 +++++++++---- arch/riscv/boot/Makefile | 7 ++++++- arch/riscv/boot/loader.S | 8 ++++++++ arch/riscv/boot/loader.lds | 14 ++++++++++++++ 4 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/boot/loader.S create mode 100644 arch/riscv/boot/loader.lds diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 7a117be8297c..aa9e377400e2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -80,13 +80,18 @@ PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ -all: Image.gz +ifeq ($(CONFIG_M_MODE),y) +KBUILD_IMAGE := $(boot)/loader +else +KBUILD_IMAGE := $(boot)/Image.gz +endif +BOOT_TARGETS := Image Image.gz loader -Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ +all: $(notdir $(KBUILD_IMAGE)) -Image.%: Image +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + @$(kecho) ' Kernel: $(boot)/$@ is ready' zinstall install: $(Q)$(MAKE) $(build)=$(boot) $@ diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile index 0990a9fdbe5d..32d2addeddba 100644 --- a/arch/riscv/boot/Makefile +++ b/arch/riscv/boot/Makefile @@ -16,7 +16,7 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image +targets := Image loader $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) @@ -24,6 +24,11 @@ $(obj)/Image: vmlinux FORCE $(obj)/Image.gz: $(obj)/Image FORCE $(call if_changed,gzip) +loader.o: $(src)/loader.S $(obj)/Image + +$(obj)/loader: $(obj)/loader.o $(obj)/Image FORCE + $(Q)$(LD) -T $(src)/loader.lds -o $@ $(obj)/loader.o + install: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" diff --git a/arch/riscv/boot/loader.S b/arch/riscv/boot/loader.S new file mode 100644 index 000000000000..5586e2610dbb --- /dev/null +++ b/arch/riscv/boot/loader.S @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + + .align 4 + .section .payload, "ax", %progbits + .globl _start +_start: + .incbin "arch/riscv/boot/Image" + diff --git a/arch/riscv/boot/loader.lds b/arch/riscv/boot/loader.lds new file mode 100644 index 000000000000..da9efd57bf44 --- /dev/null +++ b/arch/riscv/boot/loader.lds @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + + .payload : { + *(.payload) + . = ALIGN(8); + } +} -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-08-13 15:48 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 17:44 ` Paul Walmsley 2019-08-13 17:44 ` Paul Walmsley 2019-08-14 9:06 ` Marc Zyngier 2019-08-14 9:06 ` Marc Zyngier 2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 4:41 ` Paul Walmsley 2019-08-14 4:41 ` Paul Walmsley 2019-08-19 10:18 ` Christoph Hellwig 2019-08-19 10:18 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig [this message] 2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig 2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:29 ` Mark Rutland 2019-08-13 16:29 ` Mark Rutland 2019-08-19 10:16 ` Christoph Hellwig 2019-08-19 10:16 ` Christoph Hellwig 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-28 6:11 ` Christoph Hellwig 2019-08-28 6:11 ` Christoph Hellwig 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-04 2:05 ` Alan Kao 2019-09-04 2:05 ` Alan Kao 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:42 ` hch 2019-08-21 0:42 ` hch 2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:04 ` Atish Patra 2019-08-20 21:04 ` Atish Patra 2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:05 ` Atish Patra 2019-08-20 21:05 ` Atish Patra 2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 4:35 ` Christoph Hellwig 2019-08-14 4:35 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:07 ` Atish Patra 2019-08-20 21:07 ` Atish Patra 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:32 ` Troy Benjegerdes 2019-08-21 23:32 ` Troy Benjegerdes
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