From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Damien Le Moal <Damien.LeMoal@wdc.com>, Atish Patra <atish.patra@wdc.com> Subject: [PATCH 07/15] riscv: read the hart ID from mhartid on boot Date: Tue, 13 Aug 2019 17:47:39 +0200 [thread overview] Message-ID: <20190813154747.24256-8-hch@lst.de> (raw) In-Reply-To: <20190813154747.24256-1-hch@lst.de> From: Damien Le Moal <Damien.LeMoal@wdc.com> When in M-Mode, we can use the mhartid CSR to get the ID of the running HART. Doing so, direct M-Mode boot without firmware is possible. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/kernel/head.S | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 53d7ce74b447..64f8fe84b88f 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -81,6 +81,7 @@ #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) /* symbolic CSR names: */ +#define CSR_MHARTID 0xf14 #define CSR_MSTATUS 0x300 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index bb96bb7b95d2..275c2ab1e990 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -50,6 +50,14 @@ _start_kernel: csrw CSR_XIE, zero csrw CSR_XIP, zero +#ifdef CONFIG_M_MODE + /* + * The hartid in a0 is expected later on, and we have no firmware + * to hand it to us. + */ + csrr a0, CSR_MHARTID +#endif + /* Load the global pointer */ .option push .option norelax -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Atish Patra <atish.patra@wdc.com>, Damien Le Moal <Damien.LeMoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/15] riscv: read the hart ID from mhartid on boot Date: Tue, 13 Aug 2019 17:47:39 +0200 [thread overview] Message-ID: <20190813154747.24256-8-hch@lst.de> (raw) In-Reply-To: <20190813154747.24256-1-hch@lst.de> From: Damien Le Moal <Damien.LeMoal@wdc.com> When in M-Mode, we can use the mhartid CSR to get the ID of the running HART. Doing so, direct M-Mode boot without firmware is possible. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/kernel/head.S | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 53d7ce74b447..64f8fe84b88f 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -81,6 +81,7 @@ #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) /* symbolic CSR names: */ +#define CSR_MHARTID 0xf14 #define CSR_MSTATUS 0x300 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index bb96bb7b95d2..275c2ab1e990 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -50,6 +50,14 @@ _start_kernel: csrw CSR_XIE, zero csrw CSR_XIP, zero +#ifdef CONFIG_M_MODE + /* + * The hartid in a0 is expected later on, and we have no firmware + * to hand it to us. + */ + csrr a0, CSR_MHARTID +#endif + /* Load the global pointer */ .option push .option norelax -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-08-13 15:48 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 17:44 ` Paul Walmsley 2019-08-13 17:44 ` Paul Walmsley 2019-08-14 9:06 ` Marc Zyngier 2019-08-14 9:06 ` Marc Zyngier 2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 4:41 ` Paul Walmsley 2019-08-14 4:41 ` Paul Walmsley 2019-08-19 10:18 ` Christoph Hellwig 2019-08-19 10:18 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig [this message] 2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig 2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:29 ` Mark Rutland 2019-08-13 16:29 ` Mark Rutland 2019-08-19 10:16 ` Christoph Hellwig 2019-08-19 10:16 ` Christoph Hellwig 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-28 6:11 ` Christoph Hellwig 2019-08-28 6:11 ` Christoph Hellwig 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-04 2:05 ` Alan Kao 2019-09-04 2:05 ` Alan Kao 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:42 ` hch 2019-08-21 0:42 ` hch 2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:04 ` Atish Patra 2019-08-20 21:04 ` Atish Patra 2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:05 ` Atish Patra 2019-08-20 21:05 ` Atish Patra 2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 4:35 ` Christoph Hellwig 2019-08-14 4:35 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:07 ` Atish Patra 2019-08-20 21:07 ` Atish Patra 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:32 ` Troy Benjegerdes 2019-08-21 23:32 ` Troy Benjegerdes
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