From: Alan Kao <alankao@andestech.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: Christoph Hellwig <hch@lst.de>, <mark.rutland@arm.com>, Damien Le Moal <Damien.LeMoal@wdc.com>, <linux-kernel@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, <linux-riscv@lists.infradead.org> Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode Date: Wed, 4 Sep 2019 10:05:39 +0800 [thread overview] Message-ID: <20190904020539.GA18202@andestech.com> (raw) In-Reply-To: <mhng-e03fb9a6-73ee-437e-aee1-e30427f5d644@palmer-si-x1e> On Tue, Sep 03, 2019 at 11:48:52AM -0700, Palmer Dabbelt wrote: > On Tue, 27 Aug 2019 23:11:46 PDT (-0700), Christoph Hellwig wrote: > >On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote: > >>clint0 would be version 0 of the clint, with is the core-local interrupt > >>controller in rocket chip. It should be "sifive,clint-1.0.0", not > >>"riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of > >>legacy device trees floating around, but I'm only considering what's been > >>upstream to be actually part of the spec. > >> > >>In this case the code should match on a "sifive,clint-1.0.0", and the > >>device trees should be fixed up to match. We match on "riscv,plic0" for > >>legacy systems, and I guess it makes sense to do something similar here. > > > >IFF we decided to change it I'd rather separate DT noes for the ipi > >bank vs timecmp register vs timeval to support variable layouts. The > >downside is that we can't just boot on unmodified upstream qemu, which > >has used the "riscv,clint0" for years. > > Like I alluded to above, matching on "riscv,clint0" seems reasonable to me > as it's a defacto standard -- we'll just have to make sure that if we ever > end up with a RISC-V CLINT that the DT entry is something else. De facto, but not mandatory. > > As far as splitting the memory maps goes, I don't have a strong opinion but > it seems like that'll introduce more complexity than it's worth. > At least the splitting can keep reminding us and any new comers in the future that CLINT is not (yet) a must in RISC-V landscape. A previous discussion FYI: ( https://lkml.org/lkml/2019/8/20/1361 ) > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Alan Kao <alankao@andestech.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: mark.rutland@arm.com, Damien Le Moal <Damien.LeMoal@wdc.com>, linux-kernel@vger.kernel.org, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv@lists.infradead.org, Christoph Hellwig <hch@lst.de> Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode Date: Wed, 4 Sep 2019 10:05:39 +0800 [thread overview] Message-ID: <20190904020539.GA18202@andestech.com> (raw) In-Reply-To: <mhng-e03fb9a6-73ee-437e-aee1-e30427f5d644@palmer-si-x1e> On Tue, Sep 03, 2019 at 11:48:52AM -0700, Palmer Dabbelt wrote: > On Tue, 27 Aug 2019 23:11:46 PDT (-0700), Christoph Hellwig wrote: > >On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote: > >>clint0 would be version 0 of the clint, with is the core-local interrupt > >>controller in rocket chip. It should be "sifive,clint-1.0.0", not > >>"riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of > >>legacy device trees floating around, but I'm only considering what's been > >>upstream to be actually part of the spec. > >> > >>In this case the code should match on a "sifive,clint-1.0.0", and the > >>device trees should be fixed up to match. We match on "riscv,plic0" for > >>legacy systems, and I guess it makes sense to do something similar here. > > > >IFF we decided to change it I'd rather separate DT noes for the ipi > >bank vs timecmp register vs timeval to support variable layouts. The > >downside is that we can't just boot on unmodified upstream qemu, which > >has used the "riscv,clint0" for years. > > Like I alluded to above, matching on "riscv,clint0" seems reasonable to me > as it's a defacto standard -- we'll just have to make sure that if we ever > end up with a RISC-V CLINT that the DT entry is something else. De facto, but not mandatory. > > As far as splitting the memory maps goes, I don't have a strong opinion but > it seems like that'll introduce more complexity than it's worth. > At least the splitting can keep reminding us and any new comers in the future that CLINT is not (yet) a must in RISC-V landscape. A previous discussion FYI: ( https://lkml.org/lkml/2019/8/20/1361 ) > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-09-04 2:07 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 17:44 ` Paul Walmsley 2019-08-13 17:44 ` Paul Walmsley 2019-08-14 9:06 ` Marc Zyngier 2019-08-14 9:06 ` Marc Zyngier 2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:36 ` Paul Walmsley 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:42 ` Christoph Hellwig 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 16:51 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 19:44 ` Paul Walmsley 2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 4:41 ` Paul Walmsley 2019-08-14 4:41 ` Paul Walmsley 2019-08-19 10:18 ` Christoph Hellwig 2019-08-19 10:18 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-09-01 8:03 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 16:29 ` Mark Rutland 2019-08-13 16:29 ` Mark Rutland 2019-08-19 10:16 ` Christoph Hellwig 2019-08-19 10:16 ` Christoph Hellwig 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-27 23:37 ` Palmer Dabbelt 2019-08-28 6:11 ` Christoph Hellwig 2019-08-28 6:11 ` Christoph Hellwig 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-03 18:48 ` Palmer Dabbelt 2019-09-04 2:05 ` Alan Kao [this message] 2019-09-04 2:05 ` Alan Kao 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:24 ` Atish Patra 2019-08-21 0:42 ` hch 2019-08-21 0:42 ` hch 2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:04 ` Atish Patra 2019-08-20 21:04 ` Atish Patra 2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:05 ` Atish Patra 2019-08-20 21:05 ` Atish Patra 2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:00 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 1:07 ` Alan Kao 2019-08-14 4:35 ` Christoph Hellwig 2019-08-14 4:35 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig 2019-08-13 15:47 ` Christoph Hellwig 2019-08-20 21:07 ` Atish Patra 2019-08-20 21:07 ` Atish Patra 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 4:14 ` Troy Benjegerdes 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 7:12 ` Christoph Hellwig 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:31 ` Atish Patra 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 17:54 ` Troy Benjegerdes 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:02 ` Anup Patel 2019-08-21 23:32 ` Troy Benjegerdes 2019-08-21 23:32 ` Troy Benjegerdes
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