From: Christoph Hellwig <hch@lst.de>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Christoph Hellwig <hch@lst.de>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode
Date: Mon, 19 Aug 2019 12:16:48 +0200 [thread overview]
Message-ID: <20190819101648.GA29645@lst.de> (raw)
In-Reply-To: <20190813162958.GA27821@lakrids.cambridge.arm.com>
On Tue, Aug 13, 2019 at 05:29:58PM +0100, Mark Rutland wrote:
> > + np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
>
> Since the MMIO layout is that of the SiFive clint, the compatible string
> should be specific to that. e.g. "sifive,clint". That way it will be
> possible to distinguish it from other implementations.
>
> What exactly is the "0" suffix for? Is that a version number?
>
> If that's a CPU index, then I don't think that's the right way to encode
> this unless the programming interface actually differs across CPUs. It
> would be better to use an explicit phandle to express the affinity.
It isn't a cpu index, I suspect a version number. These show up
in a lot of the early RISC-V DTs coming from the UCB/SiFive sphere.
They've now spread everywhere unfortunately.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode
Date: Mon, 19 Aug 2019 12:16:48 +0200 [thread overview]
Message-ID: <20190819101648.GA29645@lst.de> (raw)
In-Reply-To: <20190813162958.GA27821@lakrids.cambridge.arm.com>
On Tue, Aug 13, 2019 at 05:29:58PM +0100, Mark Rutland wrote:
> > + np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
>
> Since the MMIO layout is that of the SiFive clint, the compatible string
> should be specific to that. e.g. "sifive,clint". That way it will be
> possible to distinguish it from other implementations.
>
> What exactly is the "0" suffix for? Is that a version number?
>
> If that's a CPU index, then I don't think that's the right way to encode
> this unless the programming interface actually differs across CPUs. It
> would be better to use an explicit phandle to express the affinity.
It isn't a cpu index, I suspect a version number. These show up
in a lot of the early RISC-V DTs coming from the UCB/SiFive sphere.
They've now spread everywhere unfortunately.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-08-19 10:16 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 17:44 ` Paul Walmsley
2019-08-13 17:44 ` Paul Walmsley
2019-08-14 9:06 ` Marc Zyngier
2019-08-14 9:06 ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 16:36 ` Paul Walmsley
2019-08-13 16:36 ` Paul Walmsley
2019-08-13 16:42 ` Christoph Hellwig
2019-08-13 16:42 ` Christoph Hellwig
2019-08-13 16:51 ` Paul Walmsley
2019-08-13 16:51 ` Paul Walmsley
2019-08-13 19:44 ` Paul Walmsley
2019-08-13 19:44 ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-14 4:41 ` Paul Walmsley
2019-08-14 4:41 ` Paul Walmsley
2019-08-19 10:18 ` Christoph Hellwig
2019-08-19 10:18 ` Christoph Hellwig
2019-09-01 8:03 ` Christoph Hellwig
2019-09-01 8:03 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 16:29 ` Mark Rutland
2019-08-13 16:29 ` Mark Rutland
2019-08-19 10:16 ` Christoph Hellwig [this message]
2019-08-19 10:16 ` Christoph Hellwig
2019-08-27 23:37 ` Palmer Dabbelt
2019-08-27 23:37 ` Palmer Dabbelt
2019-08-28 6:11 ` Christoph Hellwig
2019-08-28 6:11 ` Christoph Hellwig
2019-09-03 18:48 ` Palmer Dabbelt
2019-09-03 18:48 ` Palmer Dabbelt
2019-09-04 2:05 ` Alan Kao
2019-09-04 2:05 ` Alan Kao
2019-08-21 0:24 ` Atish Patra
2019-08-21 0:24 ` Atish Patra
2019-08-21 0:42 ` hch
2019-08-21 0:42 ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-20 21:04 ` Atish Patra
2019-08-20 21:04 ` Atish Patra
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-20 21:05 ` Atish Patra
2019-08-20 21:05 ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-14 1:00 ` Alan Kao
2019-08-14 1:00 ` Alan Kao
2019-08-14 1:07 ` Alan Kao
2019-08-14 1:07 ` Alan Kao
2019-08-14 4:35 ` Christoph Hellwig
2019-08-14 4:35 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-20 21:07 ` Atish Patra
2019-08-20 21:07 ` Atish Patra
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:32 ` Troy Benjegerdes
2019-08-21 23:32 ` Troy Benjegerdes
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190819101648.GA29645@lst.de \
--to=hch@lst.de \
--cc=damien.lemoal@wdc.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.