[PATCH 00/12] drm/i915: Gamma cleanups

[PATCH 00/12] drm/i915: Gamma cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some polishings and at least one minor fix for the gamma stuff.

Ville Syrjälä (12):
  drm: Inline drm_color_lut_extract()
  drm/i915: Polish CHV .load_luts() a bit
  drm/i915: Polish CHV CGM CSC loading
  drm/i915: Add i9xx_lut_8()
  drm/i915: Clean up i9xx_load_luts_internal()
  drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  drm/i915: s/blob_data/lut/
  drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  drm/i915: Clean up integer types in color code
  drm/i915: Refactor LUT read functions
  drm/i915: Fix readout of PIPEGCMAX
  drm/i915: Pass the crtc to the low level read_lut() funcs

 drivers/gpu/drm/drm_color_mgmt.c           |  24 --
 drivers/gpu/drm/i915/display/intel_color.c | 435 +++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h            |   1 -
 include/drm/drm_color_mgmt.h               |  23 +-
 4 files changed, 258 insertions(+), 225 deletions(-)

-- 
2.23.0

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[Intel-gfx] [PATCH 00/12] drm/i915: Gamma cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some polishings and at least one minor fix for the gamma stuff.

Ville Syrjälä (12):
  drm: Inline drm_color_lut_extract()
  drm/i915: Polish CHV .load_luts() a bit
  drm/i915: Polish CHV CGM CSC loading
  drm/i915: Add i9xx_lut_8()
  drm/i915: Clean up i9xx_load_luts_internal()
  drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  drm/i915: s/blob_data/lut/
  drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  drm/i915: Clean up integer types in color code
  drm/i915: Refactor LUT read functions
  drm/i915: Fix readout of PIPEGCMAX
  drm/i915: Pass the crtc to the low level read_lut() funcs

 drivers/gpu/drm/drm_color_mgmt.c           |  24 --
 drivers/gpu/drm/i915/display/intel_color.c | 435 +++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h            |   1 -
 include/drm/drm_color_mgmt.h               |  23 +-
 4 files changed, 258 insertions(+), 225 deletions(-)

-- 
2.23.0

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[PATCH 00/12] drm/i915: Gamma cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some polishings and at least one minor fix for the gamma stuff.

Ville Syrjälä (12):
  drm: Inline drm_color_lut_extract()
  drm/i915: Polish CHV .load_luts() a bit
  drm/i915: Polish CHV CGM CSC loading
  drm/i915: Add i9xx_lut_8()
  drm/i915: Clean up i9xx_load_luts_internal()
  drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  drm/i915: s/blob_data/lut/
  drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  drm/i915: Clean up integer types in color code
  drm/i915: Refactor LUT read functions
  drm/i915: Fix readout of PIPEGCMAX
  drm/i915: Pass the crtc to the low level read_lut() funcs

 drivers/gpu/drm/drm_color_mgmt.c           |  24 --
 drivers/gpu/drm/i915/display/intel_color.c | 435 +++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h            |   1 -
 include/drm/drm_color_mgmt.h               |  23 +-
 4 files changed, 258 insertions(+), 225 deletions(-)

-- 
2.23.0

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[PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This thing can get called several thousand times per LUT
so seems like we want to inline it to:
- avoid the function call overhead
- allow constant folding

A quick synthetic test (w/o any hardware interaction) with
a ridiculously large LUT size shows about 50% reduction in
runtime on my HSW and BSW boxes. Slightly less with more
reasonable LUT size but still easily measurable in tens
of microseconds.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
 include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 4ce5c6d8de99..19c5f635992a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -108,30 +108,6 @@
  * 	standard enum values supported by the DRM plane.
  */
 
-/**
- * drm_color_lut_extract - clamp and round LUT entries
- * @user_input: input value
- * @bit_precision: number of bits the hw LUT supports
- *
- * Extract a degamma/gamma LUT value provided by user (in the form of
- * &drm_color_lut entries) and round it to the precision supported by the
- * hardware.
- */
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
-{
-	uint32_t val = user_input;
-	uint32_t max = 0xffff >> (16 - bit_precision);
-
-	/* Round only if we're not using full precision. */
-	if (bit_precision < 16) {
-		val += 1UL << (16 - bit_precision - 1);
-		val >>= 16 - bit_precision;
-	}
-
-	return clamp_val(val, 0, max);
-}
-EXPORT_SYMBOL(drm_color_lut_extract);
-
 /**
  * drm_crtc_enable_color_mgmt - enable color management properties
  * @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d92ab7..069b21d61871 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -29,7 +29,28 @@
 struct drm_crtc;
 struct drm_plane;
 
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+/**
+ * drm_color_lut_extract - clamp and round LUT entries
+ * @user_input: input value
+ * @bit_precision: number of bits the hw LUT supports
+ *
+ * Extract a degamma/gamma LUT value provided by user (in the form of
+ * &drm_color_lut entries) and round it to the precision supported by the
+ * hardware.
+ */
+static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
+{
+	u32 val = user_input;
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	/* Round only if we're not using full precision. */
+	if (bit_precision < 16) {
+		val += 1UL << (16 - bit_precision - 1);
+		val >>= 16 - bit_precision;
+	}
+
+	return clamp_val(val, 0, max);
+}
 
 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 				uint degamma_lut_size,
-- 
2.23.0

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[Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This thing can get called several thousand times per LUT
so seems like we want to inline it to:
- avoid the function call overhead
- allow constant folding

A quick synthetic test (w/o any hardware interaction) with
a ridiculously large LUT size shows about 50% reduction in
runtime on my HSW and BSW boxes. Slightly less with more
reasonable LUT size but still easily measurable in tens
of microseconds.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
 include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 4ce5c6d8de99..19c5f635992a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -108,30 +108,6 @@
  * 	standard enum values supported by the DRM plane.
  */
 
-/**
- * drm_color_lut_extract - clamp and round LUT entries
- * @user_input: input value
- * @bit_precision: number of bits the hw LUT supports
- *
- * Extract a degamma/gamma LUT value provided by user (in the form of
- * &drm_color_lut entries) and round it to the precision supported by the
- * hardware.
- */
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
-{
-	uint32_t val = user_input;
-	uint32_t max = 0xffff >> (16 - bit_precision);
-
-	/* Round only if we're not using full precision. */
-	if (bit_precision < 16) {
-		val += 1UL << (16 - bit_precision - 1);
-		val >>= 16 - bit_precision;
-	}
-
-	return clamp_val(val, 0, max);
-}
-EXPORT_SYMBOL(drm_color_lut_extract);
-
 /**
  * drm_crtc_enable_color_mgmt - enable color management properties
  * @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d92ab7..069b21d61871 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -29,7 +29,28 @@
 struct drm_crtc;
 struct drm_plane;
 
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+/**
+ * drm_color_lut_extract - clamp and round LUT entries
+ * @user_input: input value
+ * @bit_precision: number of bits the hw LUT supports
+ *
+ * Extract a degamma/gamma LUT value provided by user (in the form of
+ * &drm_color_lut entries) and round it to the precision supported by the
+ * hardware.
+ */
+static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
+{
+	u32 val = user_input;
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	/* Round only if we're not using full precision. */
+	if (bit_precision < 16) {
+		val += 1UL << (16 - bit_precision - 1);
+		val >>= 16 - bit_precision;
+	}
+
+	return clamp_val(val, 0, max);
+}
 
 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 				uint degamma_lut_size,
-- 
2.23.0

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[PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This thing can get called several thousand times per LUT
so seems like we want to inline it to:
- avoid the function call overhead
- allow constant folding

A quick synthetic test (w/o any hardware interaction) with
a ridiculously large LUT size shows about 50% reduction in
runtime on my HSW and BSW boxes. Slightly less with more
reasonable LUT size but still easily measurable in tens
of microseconds.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
 include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 4ce5c6d8de99..19c5f635992a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -108,30 +108,6 @@
  * 	standard enum values supported by the DRM plane.
  */
 
-/**
- * drm_color_lut_extract - clamp and round LUT entries
- * @user_input: input value
- * @bit_precision: number of bits the hw LUT supports
- *
- * Extract a degamma/gamma LUT value provided by user (in the form of
- * &drm_color_lut entries) and round it to the precision supported by the
- * hardware.
- */
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
-{
-	uint32_t val = user_input;
-	uint32_t max = 0xffff >> (16 - bit_precision);
-
-	/* Round only if we're not using full precision. */
-	if (bit_precision < 16) {
-		val += 1UL << (16 - bit_precision - 1);
-		val >>= 16 - bit_precision;
-	}
-
-	return clamp_val(val, 0, max);
-}
-EXPORT_SYMBOL(drm_color_lut_extract);
-
 /**
  * drm_crtc_enable_color_mgmt - enable color management properties
  * @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d92ab7..069b21d61871 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -29,7 +29,28 @@
 struct drm_crtc;
 struct drm_plane;
 
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+/**
+ * drm_color_lut_extract - clamp and round LUT entries
+ * @user_input: input value
+ * @bit_precision: number of bits the hw LUT supports
+ *
+ * Extract a degamma/gamma LUT value provided by user (in the form of
+ * &drm_color_lut entries) and round it to the precision supported by the
+ * hardware.
+ */
+static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
+{
+	u32 val = user_input;
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	/* Round only if we're not using full precision. */
+	if (bit_precision < 16) {
+		val += 1UL << (16 - bit_precision - 1);
+		val >>= 16 - bit_precision;
+	}
+
+	return clamp_val(val, 0, max);
+}
 
 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 				uint degamma_lut_size,
-- 
2.23.0

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Re: [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Kazlauskas, Nicholas]

On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This thing can get called several thousand times per LUT
> so seems like we want to inline it to:
> - avoid the function call overhead
> - allow constant folding
> 
> A quick synthetic test (w/o any hardware interaction) with
> a ridiculously large LUT size shows about 50% reduction in
> runtime on my HSW and BSW boxes. Slightly less with more
> reasonable LUT size but still easily measurable in tens
> of microseconds.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Seems reasonable to me. It would probably make sense to even split this 
further into two functions, one for high precision and one for low 
precision so it's purely a calculation and not hitting any branches.

Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>   include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
>   2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> index 4ce5c6d8de99..19c5f635992a 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -108,30 +108,6 @@
>    * 	standard enum values supported by the DRM plane.
>    */
>   
> -/**
> - * drm_color_lut_extract - clamp and round LUT entries
> - * @user_input: input value
> - * @bit_precision: number of bits the hw LUT supports
> - *
> - * Extract a degamma/gamma LUT value provided by user (in the form of
> - * &drm_color_lut entries) and round it to the precision supported by the
> - * hardware.
> - */
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> -{
> -	uint32_t val = user_input;
> -	uint32_t max = 0xffff >> (16 - bit_precision);
> -
> -	/* Round only if we're not using full precision. */
> -	if (bit_precision < 16) {
> -		val += 1UL << (16 - bit_precision - 1);
> -		val >>= 16 - bit_precision;
> -	}
> -
> -	return clamp_val(val, 0, max);
> -}
> -EXPORT_SYMBOL(drm_color_lut_extract);
> -
>   /**
>    * drm_crtc_enable_color_mgmt - enable color management properties
>    * @crtc: DRM CRTC
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index d1c662d92ab7..069b21d61871 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -29,7 +29,28 @@
>   struct drm_crtc;
>   struct drm_plane;
>   
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> +/**
> + * drm_color_lut_extract - clamp and round LUT entries
> + * @user_input: input value
> + * @bit_precision: number of bits the hw LUT supports
> + *
> + * Extract a degamma/gamma LUT value provided by user (in the form of
> + * &drm_color_lut entries) and round it to the precision supported by the
> + * hardware.
> + */
> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> +{
> +	u32 val = user_input;
> +	u32 max = 0xffff >> (16 - bit_precision);
> +
> +	/* Round only if we're not using full precision. */
> +	if (bit_precision < 16) {
> +		val += 1UL << (16 - bit_precision - 1);
> +		val >>= 16 - bit_precision;
> +	}
> +
> +	return clamp_val(val, 0, max);
> +}
>   
>   void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>   				uint degamma_lut_size,
> 

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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Kazlauskas, Nicholas]

On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This thing can get called several thousand times per LUT
> so seems like we want to inline it to:
> - avoid the function call overhead
> - allow constant folding
> 
> A quick synthetic test (w/o any hardware interaction) with
> a ridiculously large LUT size shows about 50% reduction in
> runtime on my HSW and BSW boxes. Slightly less with more
> reasonable LUT size but still easily measurable in tens
> of microseconds.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Seems reasonable to me. It would probably make sense to even split this 
further into two functions, one for high precision and one for low 
precision so it's purely a calculation and not hitting any branches.

Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>   include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
>   2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> index 4ce5c6d8de99..19c5f635992a 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -108,30 +108,6 @@
>    * 	standard enum values supported by the DRM plane.
>    */
>   
> -/**
> - * drm_color_lut_extract - clamp and round LUT entries
> - * @user_input: input value
> - * @bit_precision: number of bits the hw LUT supports
> - *
> - * Extract a degamma/gamma LUT value provided by user (in the form of
> - * &drm_color_lut entries) and round it to the precision supported by the
> - * hardware.
> - */
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> -{
> -	uint32_t val = user_input;
> -	uint32_t max = 0xffff >> (16 - bit_precision);
> -
> -	/* Round only if we're not using full precision. */
> -	if (bit_precision < 16) {
> -		val += 1UL << (16 - bit_precision - 1);
> -		val >>= 16 - bit_precision;
> -	}
> -
> -	return clamp_val(val, 0, max);
> -}
> -EXPORT_SYMBOL(drm_color_lut_extract);
> -
>   /**
>    * drm_crtc_enable_color_mgmt - enable color management properties
>    * @crtc: DRM CRTC
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index d1c662d92ab7..069b21d61871 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -29,7 +29,28 @@
>   struct drm_crtc;
>   struct drm_plane;
>   
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> +/**
> + * drm_color_lut_extract - clamp and round LUT entries
> + * @user_input: input value
> + * @bit_precision: number of bits the hw LUT supports
> + *
> + * Extract a degamma/gamma LUT value provided by user (in the form of
> + * &drm_color_lut entries) and round it to the precision supported by the
> + * hardware.
> + */
> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> +{
> +	u32 val = user_input;
> +	u32 max = 0xffff >> (16 - bit_precision);
> +
> +	/* Round only if we're not using full precision. */
> +	if (bit_precision < 16) {
> +		val += 1UL << (16 - bit_precision - 1);
> +		val >>= 16 - bit_precision;
> +	}
> +
> +	return clamp_val(val, 0, max);
> +}
>   
>   void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>   				uint degamma_lut_size,
> 

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Re: [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 03:31:28PM +0000, Kazlauskas, Nicholas wrote:
> On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This thing can get called several thousand times per LUT
> > so seems like we want to inline it to:
> > - avoid the function call overhead
> > - allow constant folding
> > 
> > A quick synthetic test (w/o any hardware interaction) with
> > a ridiculously large LUT size shows about 50% reduction in
> > runtime on my HSW and BSW boxes. Slightly less with more
> > reasonable LUT size but still easily measurable in tens
> > of microseconds.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> 
> Seems reasonable to me. It would probably make sense to even split this 
> further into two functions, one for high precision and one for low 
> precision so it's purely a calculation and not hitting any branches.

Constant folding gets rid of it.

> 
> Nicholas Kazlauskas
> 
> > ---
> >   drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> >   include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> >   2 files changed, 22 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > index 4ce5c6d8de99..19c5f635992a 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -108,30 +108,6 @@
> >    * 	standard enum values supported by the DRM plane.
> >    */
> >   
> > -/**
> > - * drm_color_lut_extract - clamp and round LUT entries
> > - * @user_input: input value
> > - * @bit_precision: number of bits the hw LUT supports
> > - *
> > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > - * &drm_color_lut entries) and round it to the precision supported by the
> > - * hardware.
> > - */
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > -{
> > -	uint32_t val = user_input;
> > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > -
> > -	/* Round only if we're not using full precision. */
> > -	if (bit_precision < 16) {
> > -		val += 1UL << (16 - bit_precision - 1);
> > -		val >>= 16 - bit_precision;
> > -	}
> > -
> > -	return clamp_val(val, 0, max);
> > -}
> > -EXPORT_SYMBOL(drm_color_lut_extract);
> > -
> >   /**
> >    * drm_crtc_enable_color_mgmt - enable color management properties
> >    * @crtc: DRM CRTC
> > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > index d1c662d92ab7..069b21d61871 100644
> > --- a/include/drm/drm_color_mgmt.h
> > +++ b/include/drm/drm_color_mgmt.h
> > @@ -29,7 +29,28 @@
> >   struct drm_crtc;
> >   struct drm_plane;
> >   
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > +/**
> > + * drm_color_lut_extract - clamp and round LUT entries
> > + * @user_input: input value
> > + * @bit_precision: number of bits the hw LUT supports
> > + *
> > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > + * &drm_color_lut entries) and round it to the precision supported by the
> > + * hardware.
> > + */
> > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > +{
> > +	u32 val = user_input;
> > +	u32 max = 0xffff >> (16 - bit_precision);
> > +
> > +	/* Round only if we're not using full precision. */
> > +	if (bit_precision < 16) {
> > +		val += 1UL << (16 - bit_precision - 1);
> > +		val >>= 16 - bit_precision;
> > +	}
> > +
> > +	return clamp_val(val, 0, max);
> > +}
> >   
> >   void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> >   				uint degamma_lut_size,
> > 
> 

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 03:31:28PM +0000, Kazlauskas, Nicholas wrote:
> On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This thing can get called several thousand times per LUT
> > so seems like we want to inline it to:
> > - avoid the function call overhead
> > - allow constant folding
> > 
> > A quick synthetic test (w/o any hardware interaction) with
> > a ridiculously large LUT size shows about 50% reduction in
> > runtime on my HSW and BSW boxes. Slightly less with more
> > reasonable LUT size but still easily measurable in tens
> > of microseconds.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> 
> Seems reasonable to me. It would probably make sense to even split this 
> further into two functions, one for high precision and one for low 
> precision so it's purely a calculation and not hitting any branches.

Constant folding gets rid of it.

> 
> Nicholas Kazlauskas
> 
> > ---
> >   drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> >   include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> >   2 files changed, 22 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > index 4ce5c6d8de99..19c5f635992a 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -108,30 +108,6 @@
> >    * 	standard enum values supported by the DRM plane.
> >    */
> >   
> > -/**
> > - * drm_color_lut_extract - clamp and round LUT entries
> > - * @user_input: input value
> > - * @bit_precision: number of bits the hw LUT supports
> > - *
> > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > - * &drm_color_lut entries) and round it to the precision supported by the
> > - * hardware.
> > - */
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > -{
> > -	uint32_t val = user_input;
> > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > -
> > -	/* Round only if we're not using full precision. */
> > -	if (bit_precision < 16) {
> > -		val += 1UL << (16 - bit_precision - 1);
> > -		val >>= 16 - bit_precision;
> > -	}
> > -
> > -	return clamp_val(val, 0, max);
> > -}
> > -EXPORT_SYMBOL(drm_color_lut_extract);
> > -
> >   /**
> >    * drm_crtc_enable_color_mgmt - enable color management properties
> >    * @crtc: DRM CRTC
> > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > index d1c662d92ab7..069b21d61871 100644
> > --- a/include/drm/drm_color_mgmt.h
> > +++ b/include/drm/drm_color_mgmt.h
> > @@ -29,7 +29,28 @@
> >   struct drm_crtc;
> >   struct drm_plane;
> >   
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > +/**
> > + * drm_color_lut_extract - clamp and round LUT entries
> > + * @user_input: input value
> > + * @bit_precision: number of bits the hw LUT supports
> > + *
> > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > + * &drm_color_lut entries) and round it to the precision supported by the
> > + * hardware.
> > + */
> > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > +{
> > +	u32 val = user_input;
> > +	u32 max = 0xffff >> (16 - bit_precision);
> > +
> > +	/* Round only if we're not using full precision. */
> > +	if (bit_precision < 16) {
> > +		val += 1UL << (16 - bit_precision - 1);
> > +		val >>= 16 - bit_precision;
> > +	}
> > +
> > +	return clamp_val(val, 0, max);
> > +}
> >   
> >   void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> >   				uint degamma_lut_size,
> > 
> 

-- 
Ville Syrjälä
Intel
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Re: [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Kazlauskas, Nicholas]

On 2019-11-07 10:43 a.m., Ville Syrjälä wrote:
> On Thu, Nov 07, 2019 at 03:31:28PM +0000, Kazlauskas, Nicholas wrote:
>> On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> This thing can get called several thousand times per LUT
>>> so seems like we want to inline it to:
>>> - avoid the function call overhead
>>> - allow constant folding
>>>
>>> A quick synthetic test (w/o any hardware interaction) with
>>> a ridiculously large LUT size shows about 50% reduction in
>>> runtime on my HSW and BSW boxes. Slightly less with more
>>> reasonable LUT size but still easily measurable in tens
>>> of microseconds.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>
>> Seems reasonable to me. It would probably make sense to even split this
>> further into two functions, one for high precision and one for low
>> precision so it's purely a calculation and not hitting any branches.
> 
> Constant folding gets rid of it.

I realized after sending that email that moving this to inline is 
probably allowing the compiler to optimize this out and give you that 
large speedup in the first place. Though branch prediction probably 
helped cut down on the cost even when it wasn't inline.

This is fine as is then, thanks.

Nicholas Kazlauskas

> 
>>
>> Nicholas Kazlauskas
>>
>>> ---
>>>    drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>>>    include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
>>>    2 files changed, 22 insertions(+), 25 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
>>> index 4ce5c6d8de99..19c5f635992a 100644
>>> --- a/drivers/gpu/drm/drm_color_mgmt.c
>>> +++ b/drivers/gpu/drm/drm_color_mgmt.c
>>> @@ -108,30 +108,6 @@
>>>     * 	standard enum values supported by the DRM plane.
>>>     */
>>>    
>>> -/**
>>> - * drm_color_lut_extract - clamp and round LUT entries
>>> - * @user_input: input value
>>> - * @bit_precision: number of bits the hw LUT supports
>>> - *
>>> - * Extract a degamma/gamma LUT value provided by user (in the form of
>>> - * &drm_color_lut entries) and round it to the precision supported by the
>>> - * hardware.
>>> - */
>>> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
>>> -{
>>> -	uint32_t val = user_input;
>>> -	uint32_t max = 0xffff >> (16 - bit_precision);
>>> -
>>> -	/* Round only if we're not using full precision. */
>>> -	if (bit_precision < 16) {
>>> -		val += 1UL << (16 - bit_precision - 1);
>>> -		val >>= 16 - bit_precision;
>>> -	}
>>> -
>>> -	return clamp_val(val, 0, max);
>>> -}
>>> -EXPORT_SYMBOL(drm_color_lut_extract);
>>> -
>>>    /**
>>>     * drm_crtc_enable_color_mgmt - enable color management properties
>>>     * @crtc: DRM CRTC
>>> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
>>> index d1c662d92ab7..069b21d61871 100644
>>> --- a/include/drm/drm_color_mgmt.h
>>> +++ b/include/drm/drm_color_mgmt.h
>>> @@ -29,7 +29,28 @@
>>>    struct drm_crtc;
>>>    struct drm_plane;
>>>    
>>> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
>>> +/**
>>> + * drm_color_lut_extract - clamp and round LUT entries
>>> + * @user_input: input value
>>> + * @bit_precision: number of bits the hw LUT supports
>>> + *
>>> + * Extract a degamma/gamma LUT value provided by user (in the form of
>>> + * &drm_color_lut entries) and round it to the precision supported by the
>>> + * hardware.
>>> + */
>>> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
>>> +{
>>> +	u32 val = user_input;
>>> +	u32 max = 0xffff >> (16 - bit_precision);
>>> +
>>> +	/* Round only if we're not using full precision. */
>>> +	if (bit_precision < 16) {
>>> +		val += 1UL << (16 - bit_precision - 1);
>>> +		val >>= 16 - bit_precision;
>>> +	}
>>> +
>>> +	return clamp_val(val, 0, max);
>>> +}
>>>    
>>>    void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>>>    				uint degamma_lut_size,
>>>
>>
> 

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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Kazlauskas, Nicholas]

On 2019-11-07 10:43 a.m., Ville Syrjälä wrote:
> On Thu, Nov 07, 2019 at 03:31:28PM +0000, Kazlauskas, Nicholas wrote:
>> On 2019-11-07 10:17 a.m., Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> This thing can get called several thousand times per LUT
>>> so seems like we want to inline it to:
>>> - avoid the function call overhead
>>> - allow constant folding
>>>
>>> A quick synthetic test (w/o any hardware interaction) with
>>> a ridiculously large LUT size shows about 50% reduction in
>>> runtime on my HSW and BSW boxes. Slightly less with more
>>> reasonable LUT size but still easily measurable in tens
>>> of microseconds.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>
>> Seems reasonable to me. It would probably make sense to even split this
>> further into two functions, one for high precision and one for low
>> precision so it's purely a calculation and not hitting any branches.
> 
> Constant folding gets rid of it.

I realized after sending that email that moving this to inline is 
probably allowing the compiler to optimize this out and give you that 
large speedup in the first place. Though branch prediction probably 
helped cut down on the cost even when it wasn't inline.

This is fine as is then, thanks.

Nicholas Kazlauskas

> 
>>
>> Nicholas Kazlauskas
>>
>>> ---
>>>    drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>>>    include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
>>>    2 files changed, 22 insertions(+), 25 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
>>> index 4ce5c6d8de99..19c5f635992a 100644
>>> --- a/drivers/gpu/drm/drm_color_mgmt.c
>>> +++ b/drivers/gpu/drm/drm_color_mgmt.c
>>> @@ -108,30 +108,6 @@
>>>     * 	standard enum values supported by the DRM plane.
>>>     */
>>>    
>>> -/**
>>> - * drm_color_lut_extract - clamp and round LUT entries
>>> - * @user_input: input value
>>> - * @bit_precision: number of bits the hw LUT supports
>>> - *
>>> - * Extract a degamma/gamma LUT value provided by user (in the form of
>>> - * &drm_color_lut entries) and round it to the precision supported by the
>>> - * hardware.
>>> - */
>>> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
>>> -{
>>> -	uint32_t val = user_input;
>>> -	uint32_t max = 0xffff >> (16 - bit_precision);
>>> -
>>> -	/* Round only if we're not using full precision. */
>>> -	if (bit_precision < 16) {
>>> -		val += 1UL << (16 - bit_precision - 1);
>>> -		val >>= 16 - bit_precision;
>>> -	}
>>> -
>>> -	return clamp_val(val, 0, max);
>>> -}
>>> -EXPORT_SYMBOL(drm_color_lut_extract);
>>> -
>>>    /**
>>>     * drm_crtc_enable_color_mgmt - enable color management properties
>>>     * @crtc: DRM CRTC
>>> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
>>> index d1c662d92ab7..069b21d61871 100644
>>> --- a/include/drm/drm_color_mgmt.h
>>> +++ b/include/drm/drm_color_mgmt.h
>>> @@ -29,7 +29,28 @@
>>>    struct drm_crtc;
>>>    struct drm_plane;
>>>    
>>> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
>>> +/**
>>> + * drm_color_lut_extract - clamp and round LUT entries
>>> + * @user_input: input value
>>> + * @bit_precision: number of bits the hw LUT supports
>>> + *
>>> + * Extract a degamma/gamma LUT value provided by user (in the form of
>>> + * &drm_color_lut entries) and round it to the precision supported by the
>>> + * hardware.
>>> + */
>>> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
>>> +{
>>> +	u32 val = user_input;
>>> +	u32 max = 0xffff >> (16 - bit_precision);
>>> +
>>> +	/* Round only if we're not using full precision. */
>>> +	if (bit_precision < 16) {
>>> +		val += 1UL << (16 - bit_precision - 1);
>>> +		val >>= 16 - bit_precision;
>>> +	}
>>> +
>>> +	return clamp_val(val, 0, max);
>>> +}
>>>    
>>>    void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>>>    				uint degamma_lut_size,
>>>
>>
> 

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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This thing can get called several thousand times per LUT
> so seems like we want to inline it to:
> - avoid the function call overhead
> - allow constant folding
> 
> A quick synthetic test (w/o any hardware interaction) with
> a ridiculously large LUT size shows about 50% reduction in
> runtime on my HSW and BSW boxes. Slightly less with more
> reasonable LUT size but still easily measurable in tens
> of microseconds.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-

You forgot to add the include stanza in the kerneldoc .rst files, which
means this is now lost from the output. Please fix.
-Daniel

>  2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> index 4ce5c6d8de99..19c5f635992a 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -108,30 +108,6 @@
>   * 	standard enum values supported by the DRM plane.
>   */
>  
> -/**
> - * drm_color_lut_extract - clamp and round LUT entries
> - * @user_input: input value
> - * @bit_precision: number of bits the hw LUT supports
> - *
> - * Extract a degamma/gamma LUT value provided by user (in the form of
> - * &drm_color_lut entries) and round it to the precision supported by the
> - * hardware.
> - */
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> -{
> -	uint32_t val = user_input;
> -	uint32_t max = 0xffff >> (16 - bit_precision);
> -
> -	/* Round only if we're not using full precision. */
> -	if (bit_precision < 16) {
> -		val += 1UL << (16 - bit_precision - 1);
> -		val >>= 16 - bit_precision;
> -	}
> -
> -	return clamp_val(val, 0, max);
> -}
> -EXPORT_SYMBOL(drm_color_lut_extract);
> -
>  /**
>   * drm_crtc_enable_color_mgmt - enable color management properties
>   * @crtc: DRM CRTC
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index d1c662d92ab7..069b21d61871 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -29,7 +29,28 @@
>  struct drm_crtc;
>  struct drm_plane;
>  
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> +/**
> + * drm_color_lut_extract - clamp and round LUT entries
> + * @user_input: input value
> + * @bit_precision: number of bits the hw LUT supports
> + *
> + * Extract a degamma/gamma LUT value provided by user (in the form of
> + * &drm_color_lut entries) and round it to the precision supported by the
> + * hardware.
> + */
> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> +{
> +	u32 val = user_input;
> +	u32 max = 0xffff >> (16 - bit_precision);
> +
> +	/* Round only if we're not using full precision. */
> +	if (bit_precision < 16) {
> +		val += 1UL << (16 - bit_precision - 1);
> +		val >>= 16 - bit_precision;
> +	}
> +
> +	return clamp_val(val, 0, max);
> +}
>  
>  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>  				uint degamma_lut_size,
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This thing can get called several thousand times per LUT
> so seems like we want to inline it to:
> - avoid the function call overhead
> - allow constant folding
> 
> A quick synthetic test (w/o any hardware interaction) with
> a ridiculously large LUT size shows about 50% reduction in
> runtime on my HSW and BSW boxes. Slightly less with more
> reasonable LUT size but still easily measurable in tens
> of microseconds.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
>  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-

You forgot to add the include stanza in the kerneldoc .rst files, which
means this is now lost from the output. Please fix.
-Daniel

>  2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> index 4ce5c6d8de99..19c5f635992a 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -108,30 +108,6 @@
>   * 	standard enum values supported by the DRM plane.
>   */
>  
> -/**
> - * drm_color_lut_extract - clamp and round LUT entries
> - * @user_input: input value
> - * @bit_precision: number of bits the hw LUT supports
> - *
> - * Extract a degamma/gamma LUT value provided by user (in the form of
> - * &drm_color_lut entries) and round it to the precision supported by the
> - * hardware.
> - */
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> -{
> -	uint32_t val = user_input;
> -	uint32_t max = 0xffff >> (16 - bit_precision);
> -
> -	/* Round only if we're not using full precision. */
> -	if (bit_precision < 16) {
> -		val += 1UL << (16 - bit_precision - 1);
> -		val >>= 16 - bit_precision;
> -	}
> -
> -	return clamp_val(val, 0, max);
> -}
> -EXPORT_SYMBOL(drm_color_lut_extract);
> -
>  /**
>   * drm_crtc_enable_color_mgmt - enable color management properties
>   * @crtc: DRM CRTC
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index d1c662d92ab7..069b21d61871 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -29,7 +29,28 @@
>  struct drm_crtc;
>  struct drm_plane;
>  
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> +/**
> + * drm_color_lut_extract - clamp and round LUT entries
> + * @user_input: input value
> + * @bit_precision: number of bits the hw LUT supports
> + *
> + * Extract a degamma/gamma LUT value provided by user (in the form of
> + * &drm_color_lut entries) and round it to the precision supported by the
> + * hardware.
> + */
> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> +{
> +	u32 val = user_input;
> +	u32 max = 0xffff >> (16 - bit_precision);
> +
> +	/* Round only if we're not using full precision. */
> +	if (bit_precision < 16) {
> +		val += 1UL << (16 - bit_precision - 1);
> +		val >>= 16 - bit_precision;
> +	}
> +
> +	return clamp_val(val, 0, max);
> +}
>  
>  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>  				uint degamma_lut_size,
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This thing can get called several thousand times per LUT
> > so seems like we want to inline it to:
> > - avoid the function call overhead
> > - allow constant folding
> > 
> > A quick synthetic test (w/o any hardware interaction) with
> > a ridiculously large LUT size shows about 50% reduction in
> > runtime on my HSW and BSW boxes. Slightly less with more
> > reasonable LUT size but still easily measurable in tens
> > of microseconds.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> 
> You forgot to add the include stanza in the kerneldoc .rst files, which
> means this is now lost from the output. Please fix.

Aye. A bit funny that we already have a bunch of other kerneldocs
in that header but it's not included in the .rst.

> -Daniel
> 
> >  2 files changed, 22 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > index 4ce5c6d8de99..19c5f635992a 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -108,30 +108,6 @@
> >   * 	standard enum values supported by the DRM plane.
> >   */
> >  
> > -/**
> > - * drm_color_lut_extract - clamp and round LUT entries
> > - * @user_input: input value
> > - * @bit_precision: number of bits the hw LUT supports
> > - *
> > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > - * &drm_color_lut entries) and round it to the precision supported by the
> > - * hardware.
> > - */
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > -{
> > -	uint32_t val = user_input;
> > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > -
> > -	/* Round only if we're not using full precision. */
> > -	if (bit_precision < 16) {
> > -		val += 1UL << (16 - bit_precision - 1);
> > -		val >>= 16 - bit_precision;
> > -	}
> > -
> > -	return clamp_val(val, 0, max);
> > -}
> > -EXPORT_SYMBOL(drm_color_lut_extract);
> > -
> >  /**
> >   * drm_crtc_enable_color_mgmt - enable color management properties
> >   * @crtc: DRM CRTC
> > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > index d1c662d92ab7..069b21d61871 100644
> > --- a/include/drm/drm_color_mgmt.h
> > +++ b/include/drm/drm_color_mgmt.h
> > @@ -29,7 +29,28 @@
> >  struct drm_crtc;
> >  struct drm_plane;
> >  
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > +/**
> > + * drm_color_lut_extract - clamp and round LUT entries
> > + * @user_input: input value
> > + * @bit_precision: number of bits the hw LUT supports
> > + *
> > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > + * &drm_color_lut entries) and round it to the precision supported by the
> > + * hardware.
> > + */
> > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > +{
> > +	u32 val = user_input;
> > +	u32 max = 0xffff >> (16 - bit_precision);
> > +
> > +	/* Round only if we're not using full precision. */
> > +	if (bit_precision < 16) {
> > +		val += 1UL << (16 - bit_precision - 1);
> > +		val >>= 16 - bit_precision;
> > +	}
> > +
> > +	return clamp_val(val, 0, max);
> > +}
> >  
> >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> >  				uint degamma_lut_size,
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This thing can get called several thousand times per LUT
> > so seems like we want to inline it to:
> > - avoid the function call overhead
> > - allow constant folding
> > 
> > A quick synthetic test (w/o any hardware interaction) with
> > a ridiculously large LUT size shows about 50% reduction in
> > runtime on my HSW and BSW boxes. Slightly less with more
> > reasonable LUT size but still easily measurable in tens
> > of microseconds.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> 
> You forgot to add the include stanza in the kerneldoc .rst files, which
> means this is now lost from the output. Please fix.

Aye. A bit funny that we already have a bunch of other kerneldocs
in that header but it's not included in the .rst.

> -Daniel
> 
> >  2 files changed, 22 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > index 4ce5c6d8de99..19c5f635992a 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -108,30 +108,6 @@
> >   * 	standard enum values supported by the DRM plane.
> >   */
> >  
> > -/**
> > - * drm_color_lut_extract - clamp and round LUT entries
> > - * @user_input: input value
> > - * @bit_precision: number of bits the hw LUT supports
> > - *
> > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > - * &drm_color_lut entries) and round it to the precision supported by the
> > - * hardware.
> > - */
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > -{
> > -	uint32_t val = user_input;
> > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > -
> > -	/* Round only if we're not using full precision. */
> > -	if (bit_precision < 16) {
> > -		val += 1UL << (16 - bit_precision - 1);
> > -		val >>= 16 - bit_precision;
> > -	}
> > -
> > -	return clamp_val(val, 0, max);
> > -}
> > -EXPORT_SYMBOL(drm_color_lut_extract);
> > -
> >  /**
> >   * drm_crtc_enable_color_mgmt - enable color management properties
> >   * @crtc: DRM CRTC
> > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > index d1c662d92ab7..069b21d61871 100644
> > --- a/include/drm/drm_color_mgmt.h
> > +++ b/include/drm/drm_color_mgmt.h
> > @@ -29,7 +29,28 @@
> >  struct drm_crtc;
> >  struct drm_plane;
> >  
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > +/**
> > + * drm_color_lut_extract - clamp and round LUT entries
> > + * @user_input: input value
> > + * @bit_precision: number of bits the hw LUT supports
> > + *
> > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > + * &drm_color_lut entries) and round it to the precision supported by the
> > + * hardware.
> > + */
> > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > +{
> > +	u32 val = user_input;
> > +	u32 max = 0xffff >> (16 - bit_precision);
> > +
> > +	/* Round only if we're not using full precision. */
> > +	if (bit_precision < 16) {
> > +		val += 1UL << (16 - bit_precision - 1);
> > +		val >>= 16 - bit_precision;
> > +	}
> > +
> > +	return clamp_val(val, 0, max);
> > +}
> >  
> >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> >  				uint degamma_lut_size,
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This thing can get called several thousand times per LUT
> > so seems like we want to inline it to:
> > - avoid the function call overhead
> > - allow constant folding
> > 
> > A quick synthetic test (w/o any hardware interaction) with
> > a ridiculously large LUT size shows about 50% reduction in
> > runtime on my HSW and BSW boxes. Slightly less with more
> > reasonable LUT size but still easily measurable in tens
> > of microseconds.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> 
> You forgot to add the include stanza in the kerneldoc .rst files, which
> means this is now lost from the output. Please fix.

Aye. A bit funny that we already have a bunch of other kerneldocs
in that header but it's not included in the .rst.

> -Daniel
> 
> >  2 files changed, 22 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > index 4ce5c6d8de99..19c5f635992a 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -108,30 +108,6 @@
> >   * 	standard enum values supported by the DRM plane.
> >   */
> >  
> > -/**
> > - * drm_color_lut_extract - clamp and round LUT entries
> > - * @user_input: input value
> > - * @bit_precision: number of bits the hw LUT supports
> > - *
> > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > - * &drm_color_lut entries) and round it to the precision supported by the
> > - * hardware.
> > - */
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > -{
> > -	uint32_t val = user_input;
> > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > -
> > -	/* Round only if we're not using full precision. */
> > -	if (bit_precision < 16) {
> > -		val += 1UL << (16 - bit_precision - 1);
> > -		val >>= 16 - bit_precision;
> > -	}
> > -
> > -	return clamp_val(val, 0, max);
> > -}
> > -EXPORT_SYMBOL(drm_color_lut_extract);
> > -
> >  /**
> >   * drm_crtc_enable_color_mgmt - enable color management properties
> >   * @crtc: DRM CRTC
> > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > index d1c662d92ab7..069b21d61871 100644
> > --- a/include/drm/drm_color_mgmt.h
> > +++ b/include/drm/drm_color_mgmt.h
> > @@ -29,7 +29,28 @@
> >  struct drm_crtc;
> >  struct drm_plane;
> >  
> > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > +/**
> > + * drm_color_lut_extract - clamp and round LUT entries
> > + * @user_input: input value
> > + * @bit_precision: number of bits the hw LUT supports
> > + *
> > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > + * &drm_color_lut entries) and round it to the precision supported by the
> > + * hardware.
> > + */
> > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > +{
> > +	u32 val = user_input;
> > +	u32 max = 0xffff >> (16 - bit_precision);
> > +
> > +	/* Round only if we're not using full precision. */
> > +	if (bit_precision < 16) {
> > +		val += 1UL << (16 - bit_precision - 1);
> > +		val >>= 16 - bit_precision;
> > +	}
> > +
> > +	return clamp_val(val, 0, max);
> > +}
> >  
> >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> >  				uint degamma_lut_size,
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Fri, Nov 08, 2019 at 03:36:57PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> > On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > This thing can get called several thousand times per LUT
> > > so seems like we want to inline it to:
> > > - avoid the function call overhead
> > > - allow constant folding
> > > 
> > > A quick synthetic test (w/o any hardware interaction) with
> > > a ridiculously large LUT size shows about 50% reduction in
> > > runtime on my HSW and BSW boxes. Slightly less with more
> > > reasonable LUT size but still easily measurable in tens
> > > of microseconds.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> > >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> > 
> > You forgot to add the include stanza in the kerneldoc .rst files, which
> > means this is now lost from the output. Please fix.
> 
> Aye. A bit funny that we already have a bunch of other kerneldocs
> in that header but it's not included in the .rst.

kerneldoc complains if there's no kerneldoc, which is often the case for
headers. So we start out without the header included, and then someone
misses that when adding the first/second/... kerneldoc.

It's rather annoying unfortunately :-/
-Daniel

> 
> > -Daniel
> > 
> > >  2 files changed, 22 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > > index 4ce5c6d8de99..19c5f635992a 100644
> > > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > > @@ -108,30 +108,6 @@
> > >   * 	standard enum values supported by the DRM plane.
> > >   */
> > >  
> > > -/**
> > > - * drm_color_lut_extract - clamp and round LUT entries
> > > - * @user_input: input value
> > > - * @bit_precision: number of bits the hw LUT supports
> > > - *
> > > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > > - * &drm_color_lut entries) and round it to the precision supported by the
> > > - * hardware.
> > > - */
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > > -{
> > > -	uint32_t val = user_input;
> > > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > > -
> > > -	/* Round only if we're not using full precision. */
> > > -	if (bit_precision < 16) {
> > > -		val += 1UL << (16 - bit_precision - 1);
> > > -		val >>= 16 - bit_precision;
> > > -	}
> > > -
> > > -	return clamp_val(val, 0, max);
> > > -}
> > > -EXPORT_SYMBOL(drm_color_lut_extract);
> > > -
> > >  /**
> > >   * drm_crtc_enable_color_mgmt - enable color management properties
> > >   * @crtc: DRM CRTC
> > > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > > index d1c662d92ab7..069b21d61871 100644
> > > --- a/include/drm/drm_color_mgmt.h
> > > +++ b/include/drm/drm_color_mgmt.h
> > > @@ -29,7 +29,28 @@
> > >  struct drm_crtc;
> > >  struct drm_plane;
> > >  
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > > +/**
> > > + * drm_color_lut_extract - clamp and round LUT entries
> > > + * @user_input: input value
> > > + * @bit_precision: number of bits the hw LUT supports
> > > + *
> > > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > > + * &drm_color_lut entries) and round it to the precision supported by the
> > > + * hardware.
> > > + */
> > > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > > +{
> > > +	u32 val = user_input;
> > > +	u32 max = 0xffff >> (16 - bit_precision);
> > > +
> > > +	/* Round only if we're not using full precision. */
> > > +	if (bit_precision < 16) {
> > > +		val += 1UL << (16 - bit_precision - 1);
> > > +		val >>= 16 - bit_precision;
> > > +	}
> > > +
> > > +	return clamp_val(val, 0, max);
> > > +}
> > >  
> > >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> > >  				uint degamma_lut_size,
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Fri, Nov 08, 2019 at 03:36:57PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> > On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > This thing can get called several thousand times per LUT
> > > so seems like we want to inline it to:
> > > - avoid the function call overhead
> > > - allow constant folding
> > > 
> > > A quick synthetic test (w/o any hardware interaction) with
> > > a ridiculously large LUT size shows about 50% reduction in
> > > runtime on my HSW and BSW boxes. Slightly less with more
> > > reasonable LUT size but still easily measurable in tens
> > > of microseconds.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> > >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> > 
> > You forgot to add the include stanza in the kerneldoc .rst files, which
> > means this is now lost from the output. Please fix.
> 
> Aye. A bit funny that we already have a bunch of other kerneldocs
> in that header but it's not included in the .rst.

kerneldoc complains if there's no kerneldoc, which is often the case for
headers. So we start out without the header included, and then someone
misses that when adding the first/second/... kerneldoc.

It's rather annoying unfortunately :-/
-Daniel

> 
> > -Daniel
> > 
> > >  2 files changed, 22 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > > index 4ce5c6d8de99..19c5f635992a 100644
> > > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > > @@ -108,30 +108,6 @@
> > >   * 	standard enum values supported by the DRM plane.
> > >   */
> > >  
> > > -/**
> > > - * drm_color_lut_extract - clamp and round LUT entries
> > > - * @user_input: input value
> > > - * @bit_precision: number of bits the hw LUT supports
> > > - *
> > > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > > - * &drm_color_lut entries) and round it to the precision supported by the
> > > - * hardware.
> > > - */
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > > -{
> > > -	uint32_t val = user_input;
> > > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > > -
> > > -	/* Round only if we're not using full precision. */
> > > -	if (bit_precision < 16) {
> > > -		val += 1UL << (16 - bit_precision - 1);
> > > -		val >>= 16 - bit_precision;
> > > -	}
> > > -
> > > -	return clamp_val(val, 0, max);
> > > -}
> > > -EXPORT_SYMBOL(drm_color_lut_extract);
> > > -
> > >  /**
> > >   * drm_crtc_enable_color_mgmt - enable color management properties
> > >   * @crtc: DRM CRTC
> > > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > > index d1c662d92ab7..069b21d61871 100644
> > > --- a/include/drm/drm_color_mgmt.h
> > > +++ b/include/drm/drm_color_mgmt.h
> > > @@ -29,7 +29,28 @@
> > >  struct drm_crtc;
> > >  struct drm_plane;
> > >  
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > > +/**
> > > + * drm_color_lut_extract - clamp and round LUT entries
> > > + * @user_input: input value
> > > + * @bit_precision: number of bits the hw LUT supports
> > > + *
> > > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > > + * &drm_color_lut entries) and round it to the precision supported by the
> > > + * hardware.
> > > + */
> > > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > > +{
> > > +	u32 val = user_input;
> > > +	u32 max = 0xffff >> (16 - bit_precision);
> > > +
> > > +	/* Round only if we're not using full precision. */
> > > +	if (bit_precision < 16) {
> > > +		val += 1UL << (16 - bit_precision - 1);
> > > +		val >>= 16 - bit_precision;
> > > +	}
> > > +
> > > +	return clamp_val(val, 0, max);
> > > +}
> > >  
> > >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> > >  				uint degamma_lut_size,
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Fri, Nov 08, 2019 at 03:36:57PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 07, 2019 at 06:40:14PM +0100, Daniel Vetter wrote:
> > On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > This thing can get called several thousand times per LUT
> > > so seems like we want to inline it to:
> > > - avoid the function call overhead
> > > - allow constant folding
> > > 
> > > A quick synthetic test (w/o any hardware interaction) with
> > > a ridiculously large LUT size shows about 50% reduction in
> > > runtime on my HSW and BSW boxes. Slightly less with more
> > > reasonable LUT size but still easily measurable in tens
> > > of microseconds.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
> > >  include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
> > 
> > You forgot to add the include stanza in the kerneldoc .rst files, which
> > means this is now lost from the output. Please fix.
> 
> Aye. A bit funny that we already have a bunch of other kerneldocs
> in that header but it's not included in the .rst.

kerneldoc complains if there's no kerneldoc, which is often the case for
headers. So we start out without the header included, and then someone
misses that when adding the first/second/... kerneldoc.

It's rather annoying unfortunately :-/
-Daniel

> 
> > -Daniel
> > 
> > >  2 files changed, 22 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
> > > index 4ce5c6d8de99..19c5f635992a 100644
> > > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > > @@ -108,30 +108,6 @@
> > >   * 	standard enum values supported by the DRM plane.
> > >   */
> > >  
> > > -/**
> > > - * drm_color_lut_extract - clamp and round LUT entries
> > > - * @user_input: input value
> > > - * @bit_precision: number of bits the hw LUT supports
> > > - *
> > > - * Extract a degamma/gamma LUT value provided by user (in the form of
> > > - * &drm_color_lut entries) and round it to the precision supported by the
> > > - * hardware.
> > > - */
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> > > -{
> > > -	uint32_t val = user_input;
> > > -	uint32_t max = 0xffff >> (16 - bit_precision);
> > > -
> > > -	/* Round only if we're not using full precision. */
> > > -	if (bit_precision < 16) {
> > > -		val += 1UL << (16 - bit_precision - 1);
> > > -		val >>= 16 - bit_precision;
> > > -	}
> > > -
> > > -	return clamp_val(val, 0, max);
> > > -}
> > > -EXPORT_SYMBOL(drm_color_lut_extract);
> > > -
> > >  /**
> > >   * drm_crtc_enable_color_mgmt - enable color management properties
> > >   * @crtc: DRM CRTC
> > > diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> > > index d1c662d92ab7..069b21d61871 100644
> > > --- a/include/drm/drm_color_mgmt.h
> > > +++ b/include/drm/drm_color_mgmt.h
> > > @@ -29,7 +29,28 @@
> > >  struct drm_crtc;
> > >  struct drm_plane;
> > >  
> > > -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> > > +/**
> > > + * drm_color_lut_extract - clamp and round LUT entries
> > > + * @user_input: input value
> > > + * @bit_precision: number of bits the hw LUT supports
> > > + *
> > > + * Extract a degamma/gamma LUT value provided by user (in the form of
> > > + * &drm_color_lut entries) and round it to the precision supported by the
> > > + * hardware.
> > > + */
> > > +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> > > +{
> > > +	u32 val = user_input;
> > > +	u32 max = 0xffff >> (16 - bit_precision);
> > > +
> > > +	/* Round only if we're not using full precision. */
> > > +	if (bit_precision < 16) {
> > > +		val += 1UL << (16 - bit_precision - 1);
> > > +		val >>= 16 - bit_precision;
> > > +	}
> > > +
> > > +	return clamp_val(val, 0, max);
> > > +}
> > >  
> > >  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
> > >  				uint degamma_lut_size,
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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[PATCH v2 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This thing can get called several thousand times per LUT
so seems like we want to inline it to:
- avoid the function call overhead
- allow constant folding

A quick synthetic test (w/o any hardware interaction) with
a ridiculously large LUT size shows about 50% reduction in
runtime on my HSW and BSW boxes. Slightly less with more
reasonable LUT size but still easily measurable in tens
of microseconds.

v2: Include drm_color_mgmt.h in the .rst (Daniel)

Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 Documentation/gpu/drm-kms.rst    |  3 +++
 drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
 include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 23a3c986ef6d..c68588ce4090 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -479,6 +479,9 @@ Color Management Properties
 .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
    :export:
 
+.. kernel-doc:: include/drm/drm_color_mgmt.h
+   :internal:
+
 Tile Group Property
 -------------------
 
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 4ce5c6d8de99..19c5f635992a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -108,30 +108,6 @@
  * 	standard enum values supported by the DRM plane.
  */
 
-/**
- * drm_color_lut_extract - clamp and round LUT entries
- * @user_input: input value
- * @bit_precision: number of bits the hw LUT supports
- *
- * Extract a degamma/gamma LUT value provided by user (in the form of
- * &drm_color_lut entries) and round it to the precision supported by the
- * hardware.
- */
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
-{
-	uint32_t val = user_input;
-	uint32_t max = 0xffff >> (16 - bit_precision);
-
-	/* Round only if we're not using full precision. */
-	if (bit_precision < 16) {
-		val += 1UL << (16 - bit_precision - 1);
-		val >>= 16 - bit_precision;
-	}
-
-	return clamp_val(val, 0, max);
-}
-EXPORT_SYMBOL(drm_color_lut_extract);
-
 /**
  * drm_crtc_enable_color_mgmt - enable color management properties
  * @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d92ab7..069b21d61871 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -29,7 +29,28 @@
 struct drm_crtc;
 struct drm_plane;
 
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+/**
+ * drm_color_lut_extract - clamp and round LUT entries
+ * @user_input: input value
+ * @bit_precision: number of bits the hw LUT supports
+ *
+ * Extract a degamma/gamma LUT value provided by user (in the form of
+ * &drm_color_lut entries) and round it to the precision supported by the
+ * hardware.
+ */
+static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
+{
+	u32 val = user_input;
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	/* Round only if we're not using full precision. */
+	if (bit_precision < 16) {
+		val += 1UL << (16 - bit_precision - 1);
+		val >>= 16 - bit_precision;
+	}
+
+	return clamp_val(val, 0, max);
+}
 
 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 				uint degamma_lut_size,
-- 
2.23.0

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[Intel-gfx] [PATCH v2 01/12] drm: Inline drm_color_lut_extract()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This thing can get called several thousand times per LUT
so seems like we want to inline it to:
- avoid the function call overhead
- allow constant folding

A quick synthetic test (w/o any hardware interaction) with
a ridiculously large LUT size shows about 50% reduction in
runtime on my HSW and BSW boxes. Slightly less with more
reasonable LUT size but still easily measurable in tens
of microseconds.

v2: Include drm_color_mgmt.h in the .rst (Daniel)

Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 Documentation/gpu/drm-kms.rst    |  3 +++
 drivers/gpu/drm/drm_color_mgmt.c | 24 ------------------------
 include/drm/drm_color_mgmt.h     | 23 ++++++++++++++++++++++-
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 23a3c986ef6d..c68588ce4090 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -479,6 +479,9 @@ Color Management Properties
 .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
    :export:
 
+.. kernel-doc:: include/drm/drm_color_mgmt.h
+   :internal:
+
 Tile Group Property
 -------------------
 
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 4ce5c6d8de99..19c5f635992a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -108,30 +108,6 @@
  * 	standard enum values supported by the DRM plane.
  */
 
-/**
- * drm_color_lut_extract - clamp and round LUT entries
- * @user_input: input value
- * @bit_precision: number of bits the hw LUT supports
- *
- * Extract a degamma/gamma LUT value provided by user (in the form of
- * &drm_color_lut entries) and round it to the precision supported by the
- * hardware.
- */
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
-{
-	uint32_t val = user_input;
-	uint32_t max = 0xffff >> (16 - bit_precision);
-
-	/* Round only if we're not using full precision. */
-	if (bit_precision < 16) {
-		val += 1UL << (16 - bit_precision - 1);
-		val >>= 16 - bit_precision;
-	}
-
-	return clamp_val(val, 0, max);
-}
-EXPORT_SYMBOL(drm_color_lut_extract);
-
 /**
  * drm_crtc_enable_color_mgmt - enable color management properties
  * @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d92ab7..069b21d61871 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -29,7 +29,28 @@
 struct drm_crtc;
 struct drm_plane;
 
-uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+/**
+ * drm_color_lut_extract - clamp and round LUT entries
+ * @user_input: input value
+ * @bit_precision: number of bits the hw LUT supports
+ *
+ * Extract a degamma/gamma LUT value provided by user (in the form of
+ * &drm_color_lut entries) and round it to the precision supported by the
+ * hardware.
+ */
+static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
+{
+	u32 val = user_input;
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	/* Round only if we're not using full precision. */
+	if (bit_precision < 16) {
+		val += 1UL << (16 - bit_precision - 1);
+		val >>= 16 - bit_precision;
+	}
+
+	return clamp_val(val, 0, max);
+}
 
 void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 				uint degamma_lut_size,
-- 
2.23.0

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[PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It irks me to use crtc_state_is_legacy_gamma() inside the guts
of the CHV color management code. Let's get rid of it and instead
just consult cgm_mode to figure out if we want to enable the pipe
gamma or the CGM gamma.

Also CHV display engine is based on i965/g4x so we should fall back
to the i965 path when the CGM gamma is not used.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3980e8b50c28..d8ee90b7774a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -996,16 +996,13 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 
 	cherryview_load_csc_matrix(crtc_state);
 
-	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		i9xx_load_luts(crtc_state);
-		return;
-	}
-
-	if (degamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
 
-	if (gamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
 		chv_load_cgm_gamma(crtc, gamma_lut);
+	else
+		i965_load_luts(crtc_state);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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[Intel-gfx] [PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It irks me to use crtc_state_is_legacy_gamma() inside the guts
of the CHV color management code. Let's get rid of it and instead
just consult cgm_mode to figure out if we want to enable the pipe
gamma or the CGM gamma.

Also CHV display engine is based on i965/g4x so we should fall back
to the i965 path when the CGM gamma is not used.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3980e8b50c28..d8ee90b7774a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -996,16 +996,13 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 
 	cherryview_load_csc_matrix(crtc_state);
 
-	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		i9xx_load_luts(crtc_state);
-		return;
-	}
-
-	if (degamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
 
-	if (gamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
 		chv_load_cgm_gamma(crtc, gamma_lut);
+	else
+		i965_load_luts(crtc_state);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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[PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It irks me to use crtc_state_is_legacy_gamma() inside the guts
of the CHV color management code. Let's get rid of it and instead
just consult cgm_mode to figure out if we want to enable the pipe
gamma or the CGM gamma.

Also CHV display engine is based on i965/g4x so we should fall back
to the i965 path when the CGM gamma is not used.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3980e8b50c28..d8ee90b7774a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -996,16 +996,13 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 
 	cherryview_load_csc_matrix(crtc_state);
 
-	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		i9xx_load_luts(crtc_state);
-		return;
-	}
-
-	if (degamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
 
-	if (gamma_lut)
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
 		chv_load_cgm_gamma(crtc, gamma_lut);
+	else
+		i965_load_luts(crtc_state);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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Re: [PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit

[Sharma, Swati2]

Hi Ville,
Can you please rebase the series? There are intel_de_write()
changes in existing code.

On 07-Nov-19 8:47 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It irks me to use crtc_state_is_legacy_gamma() inside the guts
> of the CHV color management code. Let's get rid of it and instead
> just consult cgm_mode to figure out if we want to enable the pipe
> gamma or the CGM gamma.
> 
> Also CHV display engine is based on i965/g4x so we should fall back
> to the i965 path when the CGM gamma is not used.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 11 ++++-------
>   1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 3980e8b50c28..d8ee90b7774a 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -996,16 +996,13 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   
>   	cherryview_load_csc_matrix(crtc_state);
>   
> -	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		i9xx_load_luts(crtc_state);
> -		return;
> -	}
> -
> -	if (degamma_lut)
> +	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
>   		chv_load_cgm_degamma(crtc, degamma_lut);
>   
> -	if (gamma_lut)
> +	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>   		chv_load_cgm_gamma(crtc, gamma_lut);
> +	else
> +		i965_load_luts(crtc_state);
>   }
>   
>   void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> 
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

-- 
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Re: [Intel-gfx] [PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit

[Sharma, Swati2]

Hi Ville,
Can you please rebase the series? There are intel_de_write()
changes in existing code.

On 07-Nov-19 8:47 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It irks me to use crtc_state_is_legacy_gamma() inside the guts
> of the CHV color management code. Let's get rid of it and instead
> just consult cgm_mode to figure out if we want to enable the pipe
> gamma or the CGM gamma.
> 
> Also CHV display engine is based on i965/g4x so we should fall back
> to the i965 path when the CGM gamma is not used.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 11 ++++-------
>   1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 3980e8b50c28..d8ee90b7774a 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -996,16 +996,13 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   
>   	cherryview_load_csc_matrix(crtc_state);
>   
> -	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		i9xx_load_luts(crtc_state);
> -		return;
> -	}
> -
> -	if (degamma_lut)
> +	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
>   		chv_load_cgm_degamma(crtc, degamma_lut);
>   
> -	if (gamma_lut)
> +	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>   		chv_load_cgm_gamma(crtc, gamma_lut);
> +	else
> +		i965_load_luts(crtc_state);
>   }
>   
>   void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> 
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

-- 
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[PATCH 03/12] drm/i915: Polish CHV CGM CSC loading

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only load the CGM CSC based on the cgm_mode bit like we
do with the gamma/degamma LUTs. And make the function
naming and arguments consistent as well.

TODO: the code to convert the coefficients look totally
bogus. IIRC CHV uses two's complement format but the code
certainly doesn't generate that, so probably negative
coefficients are totally busted.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 69 ++++++++++------------
 1 file changed, 32 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d8ee90b7774a..f20809d91f85 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -333,48 +333,38 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 }
 
-/*
- * Set up the pipe CSC unit on CherryView.
- */
-static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
+static void chv_load_cgm_csc(struct intel_crtc *crtc,
+			     const struct drm_property_blob *blob)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_color_ctm *ctm = blob->data;
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
+	u16 coeffs[9];
+	int i;
 
-	if (crtc_state->hw.ctm) {
-		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
-		u16 coeffs[9] = {};
-		int i;
-
-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
-			u64 abs_coeff =
-				((1ULL << 63) - 1) & ctm->matrix[i];
-
-			/* Round coefficient. */
-			abs_coeff += 1 << (32 - 13);
-			/* Clamp to hardware limits. */
-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
-			/* Write coefficients in S3.12 format. */
-			if (ctm->matrix[i] & (1ULL << 63))
-				coeffs[i] = 1 << 15;
-			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
-			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
-		}
+	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+		u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 
-		I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
-			   coeffs[1] << 16 | coeffs[0]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
-			   coeffs[3] << 16 | coeffs[2]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
-			   coeffs[5] << 16 | coeffs[4]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
-			   coeffs[7] << 16 | coeffs[6]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
+		/* Round coefficient. */
+		abs_coeff += 1 << (32 - 13);
+		/* Clamp to hardware limits. */
+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
+
+		coeffs[i] = 0;
+
+		/* Write coefficients in S3.12 format. */
+		if (ctm->matrix[i] & (1ULL << 63))
+			coeffs[i] |= 1 << 15;
+
+		coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
+		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 	}
 
-	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
+	I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), coeffs[1] << 16 | coeffs[0]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), coeffs[3] << 16 | coeffs[2]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), coeffs[5] << 16 | coeffs[4]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), coeffs[7] << 16 | coeffs[6]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
@@ -991,10 +981,13 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
 
-	cherryview_load_csc_matrix(crtc_state);
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+		chv_load_cgm_csc(crtc, ctm);
 
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
@@ -1003,6 +996,8 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 		chv_load_cgm_gamma(crtc, gamma_lut);
 	else
 		i965_load_luts(crtc_state);
+
+	I915_WRITE(CGM_PIPE_MODE(crtc->pipe), crtc_state->cgm_mode);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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[Intel-gfx] [PATCH 03/12] drm/i915: Polish CHV CGM CSC loading

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only load the CGM CSC based on the cgm_mode bit like we
do with the gamma/degamma LUTs. And make the function
naming and arguments consistent as well.

TODO: the code to convert the coefficients look totally
bogus. IIRC CHV uses two's complement format but the code
certainly doesn't generate that, so probably negative
coefficients are totally busted.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 69 ++++++++++------------
 1 file changed, 32 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d8ee90b7774a..f20809d91f85 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -333,48 +333,38 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 }
 
-/*
- * Set up the pipe CSC unit on CherryView.
- */
-static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
+static void chv_load_cgm_csc(struct intel_crtc *crtc,
+			     const struct drm_property_blob *blob)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_color_ctm *ctm = blob->data;
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
+	u16 coeffs[9];
+	int i;
 
-	if (crtc_state->hw.ctm) {
-		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
-		u16 coeffs[9] = {};
-		int i;
-
-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
-			u64 abs_coeff =
-				((1ULL << 63) - 1) & ctm->matrix[i];
-
-			/* Round coefficient. */
-			abs_coeff += 1 << (32 - 13);
-			/* Clamp to hardware limits. */
-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
-			/* Write coefficients in S3.12 format. */
-			if (ctm->matrix[i] & (1ULL << 63))
-				coeffs[i] = 1 << 15;
-			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
-			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
-		}
+	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+		u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 
-		I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
-			   coeffs[1] << 16 | coeffs[0]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
-			   coeffs[3] << 16 | coeffs[2]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
-			   coeffs[5] << 16 | coeffs[4]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
-			   coeffs[7] << 16 | coeffs[6]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
+		/* Round coefficient. */
+		abs_coeff += 1 << (32 - 13);
+		/* Clamp to hardware limits. */
+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
+
+		coeffs[i] = 0;
+
+		/* Write coefficients in S3.12 format. */
+		if (ctm->matrix[i] & (1ULL << 63))
+			coeffs[i] |= 1 << 15;
+
+		coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
+		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 	}
 
-	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
+	I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), coeffs[1] << 16 | coeffs[0]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), coeffs[3] << 16 | coeffs[2]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), coeffs[5] << 16 | coeffs[4]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), coeffs[7] << 16 | coeffs[6]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
@@ -991,10 +981,13 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
 
-	cherryview_load_csc_matrix(crtc_state);
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+		chv_load_cgm_csc(crtc, ctm);
 
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
@@ -1003,6 +996,8 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 		chv_load_cgm_gamma(crtc, gamma_lut);
 	else
 		i965_load_luts(crtc_state);
+
+	I915_WRITE(CGM_PIPE_MODE(crtc->pipe), crtc_state->cgm_mode);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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[PATCH 03/12] drm/i915: Polish CHV CGM CSC loading

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only load the CGM CSC based on the cgm_mode bit like we
do with the gamma/degamma LUTs. And make the function
naming and arguments consistent as well.

TODO: the code to convert the coefficients look totally
bogus. IIRC CHV uses two's complement format but the code
certainly doesn't generate that, so probably negative
coefficients are totally busted.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 69 ++++++++++------------
 1 file changed, 32 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d8ee90b7774a..f20809d91f85 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -333,48 +333,38 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 }
 
-/*
- * Set up the pipe CSC unit on CherryView.
- */
-static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
+static void chv_load_cgm_csc(struct intel_crtc *crtc,
+			     const struct drm_property_blob *blob)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_color_ctm *ctm = blob->data;
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
+	u16 coeffs[9];
+	int i;
 
-	if (crtc_state->hw.ctm) {
-		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
-		u16 coeffs[9] = {};
-		int i;
-
-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
-			u64 abs_coeff =
-				((1ULL << 63) - 1) & ctm->matrix[i];
-
-			/* Round coefficient. */
-			abs_coeff += 1 << (32 - 13);
-			/* Clamp to hardware limits. */
-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
-			/* Write coefficients in S3.12 format. */
-			if (ctm->matrix[i] & (1ULL << 63))
-				coeffs[i] = 1 << 15;
-			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
-			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
-		}
+	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+		u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 
-		I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
-			   coeffs[1] << 16 | coeffs[0]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
-			   coeffs[3] << 16 | coeffs[2]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
-			   coeffs[5] << 16 | coeffs[4]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
-			   coeffs[7] << 16 | coeffs[6]);
-		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
+		/* Round coefficient. */
+		abs_coeff += 1 << (32 - 13);
+		/* Clamp to hardware limits. */
+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
+
+		coeffs[i] = 0;
+
+		/* Write coefficients in S3.12 format. */
+		if (ctm->matrix[i] & (1ULL << 63))
+			coeffs[i] |= 1 << 15;
+
+		coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
+		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 	}
 
-	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
+	I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), coeffs[1] << 16 | coeffs[0]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), coeffs[3] << 16 | coeffs[2]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), coeffs[5] << 16 | coeffs[4]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), coeffs[7] << 16 | coeffs[6]);
+	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
@@ -991,10 +981,13 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
 
-	cherryview_load_csc_matrix(crtc_state);
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+		chv_load_cgm_csc(crtc, ctm);
 
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
@@ -1003,6 +996,8 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 		chv_load_cgm_gamma(crtc, gamma_lut);
 	else
 		i965_load_luts(crtc_state);
+
+	I915_WRITE(CGM_PIPE_MODE(crtc->pipe), crtc_state->cgm_mode);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.23.0

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[PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have a nice little helper to compute a single LUT entry
for everything except the 8bpc legacy gamma mode. Let's
complete the set.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index f20809d91f85..5443b8ec0a4c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,13 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
+static u32 i9xx_lut_8(const struct drm_color_lut *color)
+{
+	return drm_color_lut_extract(color->red, 8) << 16 |
+		drm_color_lut_extract(color->green, 8) << 8 |
+		drm_color_lut_extract(color->blue, 8);
+}
+
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 {
@@ -410,10 +417,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 		const struct drm_color_lut *lut = blob->data;
 
 		for (i = 0; i < 256; i++) {
-			u32 word =
-				(drm_color_lut_extract(lut[i].red, 8) << 16) |
-				(drm_color_lut_extract(lut[i].green, 8) << 8) |
-				drm_color_lut_extract(lut[i].blue, 8);
+			u32 word = i9xx_lut_8(&lut[i]);
 
 			if (HAS_GMCH(dev_priv))
 				I915_WRITE(PALETTE(pipe, i), word);
-- 
2.23.0

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[Intel-gfx] [PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have a nice little helper to compute a single LUT entry
for everything except the 8bpc legacy gamma mode. Let's
complete the set.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index f20809d91f85..5443b8ec0a4c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,13 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
+static u32 i9xx_lut_8(const struct drm_color_lut *color)
+{
+	return drm_color_lut_extract(color->red, 8) << 16 |
+		drm_color_lut_extract(color->green, 8) << 8 |
+		drm_color_lut_extract(color->blue, 8);
+}
+
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 {
@@ -410,10 +417,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 		const struct drm_color_lut *lut = blob->data;
 
 		for (i = 0; i < 256; i++) {
-			u32 word =
-				(drm_color_lut_extract(lut[i].red, 8) << 16) |
-				(drm_color_lut_extract(lut[i].green, 8) << 8) |
-				drm_color_lut_extract(lut[i].blue, 8);
+			u32 word = i9xx_lut_8(&lut[i]);
 
 			if (HAS_GMCH(dev_priv))
 				I915_WRITE(PALETTE(pipe, i), word);
-- 
2.23.0

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Re: [Intel-gfx] [PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Emil Velikov]

On Thu, 7 Nov 2019 at 15:17, Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have a nice little helper to compute a single LUT entry
> for everything except the 8bpc legacy gamma mode. Let's
> complete the set.
>
At a later stage one could rename this & the 10bit one, moving them to
include/drm/.
There are other drivers doing the same thing... not sure if that's
worth it though.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

-Emil
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Re: [Intel-gfx] [PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Emil Velikov]

On Thu, 7 Nov 2019 at 15:17, Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have a nice little helper to compute a single LUT entry
> for everything except the 8bpc legacy gamma mode. Let's
> complete the set.
>
At a later stage one could rename this & the 10bit one, moving them to
include/drm/.
There are other drivers doing the same thing... not sure if that's
worth it though.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

-Emil
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Re: [Intel-gfx] [PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Ville Syrjälä]

On Thu, Feb 20, 2020 at 11:20:05AM +0000, Emil Velikov wrote:
> On Thu, 7 Nov 2019 at 15:17, Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We have a nice little helper to compute a single LUT entry
> > for everything except the 8bpc legacy gamma mode. Let's
> > complete the set.
> >
> At a later stage one could rename this & the 10bit one, moving them to
> include/drm/.
> There are other drivers doing the same thing... not sure if that's
> worth it though.

I'd say no. These are specifically about formatting the LUT entry for
the hw register. I don't really see much benefit from sharing code to
compute hw register values across totally different hardware, even if
the bits happen to match by accident.

The only good exception I can think of are cases where said 
register value comes more or less straight from some cross
vendor spec.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 04/12] drm/i915: Add i9xx_lut_8()

[Ville Syrjälä]

On Thu, Feb 20, 2020 at 11:20:05AM +0000, Emil Velikov wrote:
> On Thu, 7 Nov 2019 at 15:17, Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We have a nice little helper to compute a single LUT entry
> > for everything except the 8bpc legacy gamma mode. Let's
> > complete the set.
> >
> At a later stage one could rename this & the 10bit one, moving them to
> include/drm/.
> There are other drivers doing the same thing... not sure if that's
> worth it though.

I'd say no. These are specifically about formatting the LUT entry for
the hw register. I don't really see much benefit from sharing code to
compute hw register values across totally different hardware, even if
the bits happen to match by accident.

The only good exception I can think of are cases where said 
register value comes more or less straight from some cross
vendor spec.

-- 
Ville Syrjälä
Intel
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[PATCH 05/12] drm/i915: Clean up i9xx_load_luts_internal()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split i9xx_load_luts_internal() into neat gmch vs. ilk+ chunks.
Avoids at least one branch in the inner loop, and makes life
a bit less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 98 +++++++++++++---------
 1 file changed, 57 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5443b8ec0a4c..992290a07086 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -397,41 +397,6 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
-/* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
-				    const struct drm_property_blob *blob)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	int i;
-
-	if (HAS_GMCH(dev_priv)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
-			assert_dsi_pll_enabled(dev_priv);
-		else
-			assert_pll_enabled(dev_priv, pipe);
-	}
-
-	if (blob) {
-		const struct drm_color_lut *lut = blob->data;
-
-		for (i = 0; i < 256; i++) {
-			u32 word = i9xx_lut_8(&lut[i]);
-
-			if (HAS_GMCH(dev_priv))
-				I915_WRITE(PALETTE(pipe, i), word);
-			else
-				I915_WRITE(LGC_PALETTE(pipe, i), word);
-		}
-	}
-}
-
-static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
-{
-	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
-}
-
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -496,6 +461,34 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 		ilk_load_csc_matrix(crtc_state);
 }
 
+static void i9xx_load_lut_8(struct intel_crtc *crtc,
+			    const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
+static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+
+	assert_pll_enabled(dev_priv, crtc->pipe);
+
+	i9xx_load_lut_8(crtc, gamma_lut);
+}
+
 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
@@ -519,14 +512,37 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		assert_dsi_pll_enabled(dev_priv);
+	else
+		assert_pll_enabled(dev_priv, crtc->pipe);
+
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		i9xx_load_lut_8(crtc, gamma_lut);
 	else
 		i965_load_lut_10p6(crtc, gamma_lut);
 }
 
+static void ilk_load_lut_8(struct intel_crtc *crtc,
+			   const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
 static void ilk_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
@@ -545,7 +561,7 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	else
 		ilk_load_lut_10(crtc, gamma_lut);
 }
@@ -653,7 +669,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -676,7 +692,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -777,7 +793,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 		glk_load_degamma_lut_linear(crtc_state);
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else {
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);
@@ -913,7 +929,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 	case GAMMA_MODE_MODE_8BIT:
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
-- 
2.23.0

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[Intel-gfx] [PATCH 05/12] drm/i915: Clean up i9xx_load_luts_internal()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split i9xx_load_luts_internal() into neat gmch vs. ilk+ chunks.
Avoids at least one branch in the inner loop, and makes life
a bit less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 98 +++++++++++++---------
 1 file changed, 57 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5443b8ec0a4c..992290a07086 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -397,41 +397,6 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
-/* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
-				    const struct drm_property_blob *blob)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	int i;
-
-	if (HAS_GMCH(dev_priv)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
-			assert_dsi_pll_enabled(dev_priv);
-		else
-			assert_pll_enabled(dev_priv, pipe);
-	}
-
-	if (blob) {
-		const struct drm_color_lut *lut = blob->data;
-
-		for (i = 0; i < 256; i++) {
-			u32 word = i9xx_lut_8(&lut[i]);
-
-			if (HAS_GMCH(dev_priv))
-				I915_WRITE(PALETTE(pipe, i), word);
-			else
-				I915_WRITE(LGC_PALETTE(pipe, i), word);
-		}
-	}
-}
-
-static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
-{
-	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
-}
-
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -496,6 +461,34 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 		ilk_load_csc_matrix(crtc_state);
 }
 
+static void i9xx_load_lut_8(struct intel_crtc *crtc,
+			    const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
+static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+
+	assert_pll_enabled(dev_priv, crtc->pipe);
+
+	i9xx_load_lut_8(crtc, gamma_lut);
+}
+
 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
@@ -519,14 +512,37 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		assert_dsi_pll_enabled(dev_priv);
+	else
+		assert_pll_enabled(dev_priv, crtc->pipe);
+
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		i9xx_load_lut_8(crtc, gamma_lut);
 	else
 		i965_load_lut_10p6(crtc, gamma_lut);
 }
 
+static void ilk_load_lut_8(struct intel_crtc *crtc,
+			   const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
 static void ilk_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
@@ -545,7 +561,7 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	else
 		ilk_load_lut_10(crtc, gamma_lut);
 }
@@ -653,7 +669,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -676,7 +692,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -777,7 +793,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 		glk_load_degamma_lut_linear(crtc_state);
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else {
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);
@@ -913,7 +929,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 	case GAMMA_MODE_MODE_8BIT:
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
-- 
2.23.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 05/12] drm/i915: Clean up i9xx_load_luts_internal()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split i9xx_load_luts_internal() into neat gmch vs. ilk+ chunks.
Avoids at least one branch in the inner loop, and makes life
a bit less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 98 +++++++++++++---------
 1 file changed, 57 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5443b8ec0a4c..992290a07086 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -397,41 +397,6 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
-/* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
-				    const struct drm_property_blob *blob)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	int i;
-
-	if (HAS_GMCH(dev_priv)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
-			assert_dsi_pll_enabled(dev_priv);
-		else
-			assert_pll_enabled(dev_priv, pipe);
-	}
-
-	if (blob) {
-		const struct drm_color_lut *lut = blob->data;
-
-		for (i = 0; i < 256; i++) {
-			u32 word = i9xx_lut_8(&lut[i]);
-
-			if (HAS_GMCH(dev_priv))
-				I915_WRITE(PALETTE(pipe, i), word);
-			else
-				I915_WRITE(LGC_PALETTE(pipe, i), word);
-		}
-	}
-}
-
-static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
-{
-	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
-}
-
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -496,6 +461,34 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 		ilk_load_csc_matrix(crtc_state);
 }
 
+static void i9xx_load_lut_8(struct intel_crtc *crtc,
+			    const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
+static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+
+	assert_pll_enabled(dev_priv, crtc->pipe);
+
+	i9xx_load_lut_8(crtc, gamma_lut);
+}
+
 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
@@ -519,14 +512,37 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		assert_dsi_pll_enabled(dev_priv);
+	else
+		assert_pll_enabled(dev_priv, crtc->pipe);
+
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		i9xx_load_lut_8(crtc, gamma_lut);
 	else
 		i965_load_lut_10p6(crtc, gamma_lut);
 }
 
+static void ilk_load_lut_8(struct intel_crtc *crtc,
+			   const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		I915_WRITE(LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i]));
+}
+
 static void ilk_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
@@ -545,7 +561,7 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	else
 		ilk_load_lut_10(crtc, gamma_lut);
 }
@@ -653,7 +669,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -676,7 +692,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -777,7 +793,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 		glk_load_degamma_lut_linear(crtc_state);
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else {
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);
@@ -913,7 +929,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 	case GAMMA_MODE_MODE_8BIT:
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
-- 
2.23.0

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https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 06/12] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To mirror the load_luts path let's clone an ilk+ version
from i9xx_read_lut_8(). I guess the extra branch isn't a huge
issue but feels better to make a clean split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++----
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 992290a07086..5890e3896f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1674,10 +1674,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	blob_data = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		if (HAS_GMCH(dev_priv))
-			val = I915_READ(PALETTE(pipe, i));
-		else
-			val = I915_READ(LGC_PALETTE(pipe, i));
+		val = I915_READ(PALETTE(pipe, i));
 
 		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1792,6 +1789,38 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 		i965_read_luts(crtc_state);
 }
 
+static struct drm_property_blob *
+ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
+		val = I915_READ(LGC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							LGC_PALETTE_RED_MASK, val), 8);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  LGC_PALETTE_GREEN_MASK, val), 8);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 LGC_PALETTE_BLUE_MASK, val), 8);
+	}
+
+	return blob;
+}
+
 static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
@@ -1834,7 +1863,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
 }
@@ -1883,7 +1912,7 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 06/12] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To mirror the load_luts path let's clone an ilk+ version
from i9xx_read_lut_8(). I guess the extra branch isn't a huge
issue but feels better to make a clean split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++----
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 992290a07086..5890e3896f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1674,10 +1674,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	blob_data = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		if (HAS_GMCH(dev_priv))
-			val = I915_READ(PALETTE(pipe, i));
-		else
-			val = I915_READ(LGC_PALETTE(pipe, i));
+		val = I915_READ(PALETTE(pipe, i));
 
 		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1792,6 +1789,38 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 		i965_read_luts(crtc_state);
 }
 
+static struct drm_property_blob *
+ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
+		val = I915_READ(LGC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							LGC_PALETTE_RED_MASK, val), 8);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  LGC_PALETTE_GREEN_MASK, val), 8);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 LGC_PALETTE_BLUE_MASK, val), 8);
+	}
+
+	return blob;
+}
+
 static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
@@ -1834,7 +1863,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
 }
@@ -1883,7 +1912,7 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 06/12] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To mirror the load_luts path let's clone an ilk+ version
from i9xx_read_lut_8(). I guess the extra branch isn't a huge
issue but feels better to make a clean split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++----
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 992290a07086..5890e3896f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1674,10 +1674,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	blob_data = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		if (HAS_GMCH(dev_priv))
-			val = I915_READ(PALETTE(pipe, i));
-		else
-			val = I915_READ(LGC_PALETTE(pipe, i));
+		val = I915_READ(PALETTE(pipe, i));
 
 		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1792,6 +1789,38 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 		i965_read_luts(crtc_state);
 }
 
+static struct drm_property_blob *
+ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
+		val = I915_READ(LGC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							LGC_PALETTE_RED_MASK, val), 8);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  LGC_PALETTE_GREEN_MASK, val), 8);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 LGC_PALETTE_BLUE_MASK, val), 8);
+	}
+
+	return blob;
+}
+
 static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
@@ -1834,7 +1863,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
 }
@@ -1883,7 +1912,7 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
-- 
2.23.0

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[PATCH 07/12] drm/i915: s/blob_data/lut/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're talking about LUT contents here so let's call the thing
'lut' rather than 'blob_data'. This is the name the load_lut()
code used before already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5890e3896f8d..43435ed343f2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1662,7 +1662,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1671,16 +1671,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1703,7 +1703,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1712,25 +1712,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
 		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
 		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
-		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
 						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
 						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
 	}
 
-	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));
-	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));
-	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));
 
 	return blob;
@@ -1755,7 +1755,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1764,17 +1764,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
 
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							CGM_PIPE_GAMMA_RED_MASK, val), 10);
 	}
 
@@ -1796,7 +1796,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1805,16 +1805,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(LGC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1829,7 +1829,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1838,16 +1838,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(PREC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  PREC_PALETTE_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 PREC_PALETTE_BLUE_MASK, val), 10);
 	}
 
@@ -1876,7 +1876,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1885,7 +1885,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 		   PAL_PREC_AUTO_INCREMENT);
@@ -1893,11 +1893,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	for (i = 0; i < hw_lut_size; i++) {
 		val = I915_READ(PREC_PAL_DATA(pipe));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_BLUE_MASK, val), 10);
 	}
 
-- 
2.23.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 07/12] drm/i915: s/blob_data/lut/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're talking about LUT contents here so let's call the thing
'lut' rather than 'blob_data'. This is the name the load_lut()
code used before already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5890e3896f8d..43435ed343f2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1662,7 +1662,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1671,16 +1671,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1703,7 +1703,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1712,25 +1712,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
 		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
 		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
-		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
 						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
 						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
 	}
 
-	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));
-	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));
-	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));
 
 	return blob;
@@ -1755,7 +1755,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1764,17 +1764,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
 
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							CGM_PIPE_GAMMA_RED_MASK, val), 10);
 	}
 
@@ -1796,7 +1796,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1805,16 +1805,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(LGC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1829,7 +1829,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1838,16 +1838,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(PREC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  PREC_PALETTE_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 PREC_PALETTE_BLUE_MASK, val), 10);
 	}
 
@@ -1876,7 +1876,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1885,7 +1885,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 		   PAL_PREC_AUTO_INCREMENT);
@@ -1893,11 +1893,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	for (i = 0; i < hw_lut_size; i++) {
 		val = I915_READ(PREC_PAL_DATA(pipe));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_BLUE_MASK, val), 10);
 	}
 
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 07/12] drm/i915: s/blob_data/lut/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're talking about LUT contents here so let's call the thing
'lut' rather than 'blob_data'. This is the name the load_lut()
code used before already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5890e3896f8d..43435ed343f2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1662,7 +1662,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1671,16 +1671,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1703,7 +1703,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1712,25 +1712,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
 		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
 		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
-		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
 						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
 						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
 	}
 
-	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));
-	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));
-	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));
 
 	return blob;
@@ -1755,7 +1755,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1764,17 +1764,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
 
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							CGM_PIPE_GAMMA_RED_MASK, val), 10);
 	}
 
@@ -1796,7 +1796,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1805,16 +1805,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = I915_READ(LGC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1829,7 +1829,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1838,16 +1838,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = I915_READ(PREC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  PREC_PALETTE_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 PREC_PALETTE_BLUE_MASK, val), 10);
 	}
 
@@ -1876,7 +1876,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1885,7 +1885,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 		   PAL_PREC_AUTO_INCREMENT);
@@ -1893,11 +1893,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	for (i = 0; i < hw_lut_size; i++) {
 		val = I915_READ(PREC_PAL_DATA(pipe));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_BLUE_MASK, val), 10);
 	}
 
-- 
2.23.0

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[PATCH 08/12] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
let's rename it to reflect that fact. This also mirrors
the other direction's chv_load_cgm_gamma().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 43435ed343f2..30c0b939620c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1748,7 +1748,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
-chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
+chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1784,7 +1784,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
 	else
 		i965_read_luts(crtc_state);
 }
-- 
2.23.0

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[Intel-gfx] [PATCH 08/12] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
let's rename it to reflect that fact. This also mirrors
the other direction's chv_load_cgm_gamma().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 43435ed343f2..30c0b939620c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1748,7 +1748,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
-chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
+chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1784,7 +1784,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
 	else
 		i965_read_luts(crtc_state);
 }
-- 
2.23.0

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[PATCH 08/12] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
let's rename it to reflect that fact. This also mirrors
the other direction's chv_load_cgm_gamma().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 43435ed343f2..30c0b939620c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1748,7 +1748,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
-chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
+chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1784,7 +1784,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
 	else
 		i965_read_luts(crtc_state);
 }
-- 
2.23.0

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[PATCH 09/12] drm/i915: Clean up integer types in color code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A variable called 'i' having an unsigned type is just looking for
trouble, and using a sized type generally makes no sense either.
Change all of them to just plain old int. And do the same for some
'lut_size' variables which generally provide the loop end codition
for 'i'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 42 ++++++++++------------
 1 file changed, 19 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 30c0b939620c..d6a20d7522a9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -713,9 +713,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
-	u32 i;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -752,8 +751,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	u32 i;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -837,7 +835,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Super Fine segment (let's call it seg1)...
@@ -870,7 +868,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *entry;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Fine segment (let's call it seg2)...
@@ -1643,7 +1641,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 }
 
 /* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
 {
 	u32 max = 0xffff >> (16 - bit_precision);
 
@@ -1663,7 +1661,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1674,7 +1672,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(PALETTE(pipe, i));
+		u32 val = I915_READ(PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1700,11 +1698,10 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1715,8 +1712,8 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
-		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+		u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+		u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
 		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
@@ -1752,11 +1749,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1767,6 +1763,8 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
+		u32 val;
+
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
 		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
@@ -1797,7 +1795,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1808,7 +1806,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(LGC_PALETTE(pipe, i));
+		u32 val = I915_READ(LGC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1826,11 +1824,10 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1841,7 +1838,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		val = I915_READ(PREC_PALETTE(pipe, i));
+		u32 val = I915_READ(PREC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
@@ -1873,11 +1870,10 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
+	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * hw_lut_size,
@@ -1891,7 +1887,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 		   PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
-		val = I915_READ(PREC_PAL_DATA(pipe));
+		u32 val = I915_READ(PREC_PAL_DATA(pipe));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 09/12] drm/i915: Clean up integer types in color code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A variable called 'i' having an unsigned type is just looking for
trouble, and using a sized type generally makes no sense either.
Change all of them to just plain old int. And do the same for some
'lut_size' variables which generally provide the loop end codition
for 'i'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 42 ++++++++++------------
 1 file changed, 19 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 30c0b939620c..d6a20d7522a9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -713,9 +713,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
-	u32 i;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -752,8 +751,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	u32 i;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -837,7 +835,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Super Fine segment (let's call it seg1)...
@@ -870,7 +868,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *entry;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Fine segment (let's call it seg2)...
@@ -1643,7 +1641,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 }
 
 /* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
 {
 	u32 max = 0xffff >> (16 - bit_precision);
 
@@ -1663,7 +1661,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1674,7 +1672,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(PALETTE(pipe, i));
+		u32 val = I915_READ(PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1700,11 +1698,10 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1715,8 +1712,8 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
-		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+		u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+		u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
 		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
@@ -1752,11 +1749,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1767,6 +1763,8 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
+		u32 val;
+
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
 		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
@@ -1797,7 +1795,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1808,7 +1806,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(LGC_PALETTE(pipe, i));
+		u32 val = I915_READ(LGC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1826,11 +1824,10 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1841,7 +1838,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		val = I915_READ(PREC_PALETTE(pipe, i));
+		u32 val = I915_READ(PREC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
@@ -1873,11 +1870,10 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
+	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * hw_lut_size,
@@ -1891,7 +1887,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 		   PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
-		val = I915_READ(PREC_PAL_DATA(pipe));
+		u32 val = I915_READ(PREC_PAL_DATA(pipe));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 09/12] drm/i915: Clean up integer types in color code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A variable called 'i' having an unsigned type is just looking for
trouble, and using a sized type generally makes no sense either.
Change all of them to just plain old int. And do the same for some
'lut_size' variables which generally provide the loop end codition
for 'i'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 42 ++++++++++------------
 1 file changed, 19 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 30c0b939620c..d6a20d7522a9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -713,9 +713,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
-	u32 i;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -752,8 +751,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	u32 i;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -837,7 +835,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Super Fine segment (let's call it seg1)...
@@ -870,7 +868,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *entry;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Fine segment (let's call it seg2)...
@@ -1643,7 +1641,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 }
 
 /* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
 {
 	u32 max = 0xffff >> (16 - bit_precision);
 
@@ -1663,7 +1661,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1674,7 +1672,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(PALETTE(pipe, i));
+		u32 val = I915_READ(PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1700,11 +1698,10 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1715,8 +1712,8 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
-		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+		u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+		u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
 
 		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
@@ -1752,11 +1749,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1767,6 +1763,8 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
+		u32 val;
+
 		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
 		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
@@ -1797,7 +1795,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1808,7 +1806,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = I915_READ(LGC_PALETTE(pipe, i));
+		u32 val = I915_READ(LGC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1826,11 +1824,10 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1841,7 +1838,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		val = I915_READ(PREC_PALETTE(pipe, i));
+		u32 val = I915_READ(PREC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
@@ -1873,11 +1870,10 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
+	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * hw_lut_size,
@@ -1891,7 +1887,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 		   PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
-		val = I915_READ(PREC_PAL_DATA(pipe));
+		u32 val = I915_READ(PREC_PAL_DATA(pipe));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-- 
2.23.0

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[PATCH 10/12] drm/i915: Refactor LUT read functions

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract all the 'hw value -> LUT entry' stuff into small helpers
to make the main 'read out the entire LUT' loop less bogged down
by such mundane details.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 128 ++++++++++-----------
 1 file changed, 64 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d6a20d7522a9..4b2bd5ac0e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
+{
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	val = clamp_val(val, 0, max);
+
+	if (bit_precision < 16)
+		val <<= 16 - bit_precision;
+
+	return val;
+}
+
 static u32 i9xx_lut_8(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 8) << 16 |
@@ -374,6 +387,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 8);
 }
 
+static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+}
+
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 {
@@ -390,6 +410,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 		(color->blue >> 8);
 }
 
+static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_RED_MASK, ldw);
+	entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
+	entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
+}
+
+static u16 i965_lut_11p6_max_pack(u32 val)
+{
+	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+}
+
 static u32 ilk_lut_10(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 10) << 20 |
@@ -397,6 +432,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
+static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+}
+
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -953,6 +995,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 	return drm_color_lut_extract(color->red, 14);
 }
 
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 				 const struct drm_property_blob *blob)
 {
@@ -1640,19 +1689,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-/* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, int bit_precision)
-{
-	u32 max = 0xffff >> (16 - bit_precision);
-
-	val = clamp_val(val, 0, max);
-
-	if (bit_precision < 16)
-		val <<= 16 - bit_precision;
-
-	return val;
-}
-
 static struct drm_property_blob *
 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 {
@@ -1674,12 +1710,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = I915_READ(PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1712,23 +1743,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
-		u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
-
-		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
-						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
-						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
-						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+		u32 ldw = I915_READ(PALETTE(pipe, 2 * i + 0));
+		u32 udw = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+		i965_lut_10p6_pack(&lut[i], ldw, udw);
 	}
 
-	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					 I915_READ(PIPEGCMAX(pipe, 0)));
-	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					   I915_READ(PIPEGCMAX(pipe, 1)));
-	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					  I915_READ(PIPEGCMAX(pipe, 2)));
+	lut[i].red = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 0)));
+	lut[i].green = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 1)));
+	lut[i].blue = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 2)));
 
 	return blob;
 }
@@ -1763,17 +1786,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		u32 val;
-
-		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+		u32 ldw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 udw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
 
-		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							CGM_PIPE_GAMMA_RED_MASK, val), 10);
+		chv_cgm_gamma_pack(&lut[i], ldw, udw);
 	}
 
 	return blob;
@@ -1808,12 +1824,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = I915_READ(LGC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1840,12 +1851,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < lut_size; i++) {
 		u32 val = I915_READ(PREC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PALETTE_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  PREC_PALETTE_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 PREC_PALETTE_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1883,18 +1889,12 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 	lut = blob->data;
 
-	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
-		   PAL_PREC_AUTO_INCREMENT);
+	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
 		u32 val = I915_READ(PREC_PAL_DATA(pipe));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
-- 
2.23.0

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[Intel-gfx] [PATCH 10/12] drm/i915: Refactor LUT read functions

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract all the 'hw value -> LUT entry' stuff into small helpers
to make the main 'read out the entire LUT' loop less bogged down
by such mundane details.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 128 ++++++++++-----------
 1 file changed, 64 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d6a20d7522a9..4b2bd5ac0e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 }
 
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
+{
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	val = clamp_val(val, 0, max);
+
+	if (bit_precision < 16)
+		val <<= 16 - bit_precision;
+
+	return val;
+}
+
 static u32 i9xx_lut_8(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 8) << 16 |
@@ -374,6 +387,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 8);
 }
 
+static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+}
+
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 {
@@ -390,6 +410,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 		(color->blue >> 8);
 }
 
+static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_RED_MASK, ldw);
+	entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
+	entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
+}
+
+static u16 i965_lut_11p6_max_pack(u32 val)
+{
+	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+}
+
 static u32 ilk_lut_10(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 10) << 20 |
@@ -397,6 +432,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
+static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+}
+
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -953,6 +995,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 	return drm_color_lut_extract(color->red, 14);
 }
 
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 				 const struct drm_property_blob *blob)
 {
@@ -1640,19 +1689,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-/* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, int bit_precision)
-{
-	u32 max = 0xffff >> (16 - bit_precision);
-
-	val = clamp_val(val, 0, max);
-
-	if (bit_precision < 16)
-		val <<= 16 - bit_precision;
-
-	return val;
-}
-
 static struct drm_property_blob *
 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 {
@@ -1674,12 +1710,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = I915_READ(PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1712,23 +1743,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
-		u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
-
-		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
-						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
-						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
-						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+		u32 ldw = I915_READ(PALETTE(pipe, 2 * i + 0));
+		u32 udw = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+		i965_lut_10p6_pack(&lut[i], ldw, udw);
 	}
 
-	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					 I915_READ(PIPEGCMAX(pipe, 0)));
-	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					   I915_READ(PIPEGCMAX(pipe, 1)));
-	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					  I915_READ(PIPEGCMAX(pipe, 2)));
+	lut[i].red = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 0)));
+	lut[i].green = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 1)));
+	lut[i].blue = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 2)));
 
 	return blob;
 }
@@ -1763,17 +1786,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		u32 val;
-
-		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+		u32 ldw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 udw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
 
-		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							CGM_PIPE_GAMMA_RED_MASK, val), 10);
+		chv_cgm_gamma_pack(&lut[i], ldw, udw);
 	}
 
 	return blob;
@@ -1808,12 +1824,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = I915_READ(LGC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1840,12 +1851,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < lut_size; i++) {
 		u32 val = I915_READ(PREC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PALETTE_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  PREC_PALETTE_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 PREC_PALETTE_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1883,18 +1889,12 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 	lut = blob->data;
 
-	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
-		   PAL_PREC_AUTO_INCREMENT);
+	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
 		u32 val = I915_READ(PREC_PAL_DATA(pipe));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
-- 
2.23.0

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[PATCH 11/12] drm/i915: Fix readout of PIPEGCMAX

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can
represent a value of 1.0 when the maximum we can store in the
software LUT is 0.ffff. Clamp the value so that it gets
saturated to the max the uapi supports.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h            | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4b2bd5ac0e8d..3fd517fa1de5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -422,7 +422,8 @@ static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 
 static u16 i965_lut_11p6_max_pack(u32 val)
 {
-	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+	/* PIPEGCMAX is 11.6, clamp to 10.6 */
+	return clamp_val(val, 0, 0xffff);
 }
 
 static u32 ilk_lut_10(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..4a8021a33b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5871,7 +5871,6 @@ enum {
 
 #define  _PIPEAGCMAX           0x70010
 #define  _PIPEBGCMAX           0x71010
-#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
 #define _PIPE_MISC_A			0x70030
-- 
2.23.0

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[Intel-gfx] [PATCH 11/12] drm/i915: Fix readout of PIPEGCMAX

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can
represent a value of 1.0 when the maximum we can store in the
software LUT is 0.ffff. Clamp the value so that it gets
saturated to the max the uapi supports.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h            | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4b2bd5ac0e8d..3fd517fa1de5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -422,7 +422,8 @@ static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 
 static u16 i965_lut_11p6_max_pack(u32 val)
 {
-	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+	/* PIPEGCMAX is 11.6, clamp to 10.6 */
+	return clamp_val(val, 0, 0xffff);
 }
 
 static u32 ilk_lut_10(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..4a8021a33b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5871,7 +5871,6 @@ enum {
 
 #define  _PIPEAGCMAX           0x70010
 #define  _PIPEBGCMAX           0x71010
-#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
 #define _PIPE_MISC_A			0x70030
-- 
2.23.0

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[PATCH 12/12] drm/i915: Pass the crtc to the low level read_lut() funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The low level read_lut() functions don't need the entire crtc state
as they know exactly what they're reading. Just need to pass in the
crtc to get at the pipe. This now neatly mirrors the load_lut()
direction.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 51 +++++++++++-----------
 1 file changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3fd517fa1de5..f0f372b9b3bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1690,10 +1690,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-static struct drm_property_blob *
-i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1719,16 +1717,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
-	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 }
 
-static struct drm_property_blob *
-i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1759,19 +1757,19 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 
 static void i965_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
+		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
 }
 
-static struct drm_property_blob *
-chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1798,16 +1796,16 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
 	else
 		i965_read_luts(crtc_state);
 }
 
-static struct drm_property_blob *
-ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1831,10 +1829,8 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	return blob;
 }
 
-static struct drm_property_blob *
-ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1860,6 +1856,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 
 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
@@ -1867,15 +1865,14 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
 }
 
-static struct drm_property_blob *
-glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
+static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
+						 u32 prec_index)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
@@ -1905,13 +1902,15 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 static void glk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
 }
 
 void intel_color_init(struct intel_crtc *crtc)
-- 
2.23.0

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[Intel-gfx] [PATCH 12/12] drm/i915: Pass the crtc to the low level read_lut() funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The low level read_lut() functions don't need the entire crtc state
as they know exactly what they're reading. Just need to pass in the
crtc to get at the pipe. This now neatly mirrors the load_lut()
direction.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 51 +++++++++++-----------
 1 file changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3fd517fa1de5..f0f372b9b3bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1690,10 +1690,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-static struct drm_property_blob *
-i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1719,16 +1717,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
-	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 }
 
-static struct drm_property_blob *
-i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1759,19 +1757,19 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 
 static void i965_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
+		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
 }
 
-static struct drm_property_blob *
-chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1798,16 +1796,16 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
 	else
 		i965_read_luts(crtc_state);
 }
 
-static struct drm_property_blob *
-ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1831,10 +1829,8 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	return blob;
 }
 
-static struct drm_property_blob *
-ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1860,6 +1856,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 
 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
@@ -1867,15 +1865,14 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
 }
 
-static struct drm_property_blob *
-glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
+static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
+						 u32 prec_index)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
@@ -1905,13 +1902,15 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 static void glk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
 }
 
 void intel_color_init(struct intel_crtc *crtc)
-- 
2.23.0

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[PATCH 12/12] drm/i915: Pass the crtc to the low level read_lut() funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The low level read_lut() functions don't need the entire crtc state
as they know exactly what they're reading. Just need to pass in the
crtc to get at the pipe. This now neatly mirrors the load_lut()
direction.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 51 +++++++++++-----------
 1 file changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 3fd517fa1de5..f0f372b9b3bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1690,10 +1690,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-static struct drm_property_blob *
-i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1719,16 +1717,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
-	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 }
 
-static struct drm_property_blob *
-i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1759,19 +1757,19 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 
 static void i965_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
+		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
 }
 
-static struct drm_property_blob *
-chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1798,16 +1796,16 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
 	else
 		i965_read_luts(crtc_state);
 }
 
-static struct drm_property_blob *
-ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1831,10 +1829,8 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	return blob;
 }
 
-static struct drm_property_blob *
-ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1860,6 +1856,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 
 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
@@ -1867,15 +1865,14 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
 }
 
-static struct drm_property_blob *
-glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
+static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
+						 u32 prec_index)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
@@ -1905,13 +1902,15 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 static void glk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
 }
 
 void intel_color_init(struct intel_crtc *crtc)
-- 
2.23.0

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aab7b7b6ba2e drm: Inline drm_color_lut_extract()
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
ce81f95570f1 drm/i915: Add i9xx_lut_8()
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
f7394645c856 drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1679:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1681:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1683:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1730:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1732:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1734:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1771:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1773:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1777:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1846:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1848:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1850:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1896:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1898:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1900:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
1d66b7bd3630 drm/i915: Clean up integer types in color code
7cef77b47c3f drm/i915: Refactor LUT read functions
631db3ed62b9 drm/i915: Fix readout of PIPEGCMAX
4888c33ef45e drm/i915: Pass the crtc to the low level read_lut() funcs

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aab7b7b6ba2e drm: Inline drm_color_lut_extract()
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
ce81f95570f1 drm/i915: Add i9xx_lut_8()
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
f7394645c856 drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1679:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1681:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1683:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1730:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1732:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1734:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1771:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1773:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1777:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1846:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1848:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1850:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1896:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1898:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1900:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
1d66b7bd3630 drm/i915: Clean up integer types in color code
7cef77b47c3f drm/i915: Refactor LUT read functions
631db3ed62b9 drm/i915: Fix readout of PIPEGCMAX
4888c33ef45e drm/i915: Pass the crtc to the low level read_lut() funcs

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✗ Fi.CI.SPARSE: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm: Inline drm_color_lut_extract()
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)

Commit: drm/i915: Polish CHV .load_luts() a bit
Okay!

Commit: drm/i915: Polish CHV CGM CSC loading
Okay!

Commit: drm/i915: Add i9xx_lut_8()
Okay!

Commit: drm/i915: Clean up i9xx_load_luts_internal()
Okay!

Commit: drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
Okay!

Commit: drm/i915: s/blob_data/lut/
Okay!

Commit: drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
Okay!

Commit: drm/i915: Clean up integer types in color code
Okay!

Commit: drm/i915: Refactor LUT read functions
Okay!

Commit: drm/i915: Fix readout of PIPEGCMAX
Okay!

Commit: drm/i915: Pass the crtc to the low level read_lut() funcs
Okay!

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm: Inline drm_color_lut_extract()
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)

Commit: drm/i915: Polish CHV .load_luts() a bit
Okay!

Commit: drm/i915: Polish CHV CGM CSC loading
Okay!

Commit: drm/i915: Add i9xx_lut_8()
Okay!

Commit: drm/i915: Clean up i9xx_load_luts_internal()
Okay!

Commit: drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
Okay!

Commit: drm/i915: s/blob_data/lut/
Okay!

Commit: drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
Okay!

Commit: drm/i915: Clean up integer types in color code
Okay!

Commit: drm/i915: Refactor LUT read functions
Okay!

Commit: drm/i915: Fix readout of PIPEGCMAX
Okay!

Commit: drm/i915: Pass the crtc to the low level read_lut() funcs
Okay!

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✗ Fi.CI.BAT: failure for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15177
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15177 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15177, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15177:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_execlists:
    - fi-icl-dsi:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-dsi/igt@i915_selftest@live_execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-icl-dsi/igt@i915_selftest@live_execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_15177 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-nick:        [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - {fi-tgl-u}:         [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_create@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-tgl-u/igt@gem_exec_create@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6700k2:      [INCOMPLETE][9] ([fdo#104108]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15177

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15177: 4888c33ef45e557085500f6d3196da5c1ee23270 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4888c33ef45e drm/i915: Pass the crtc to the low level read_lut() funcs
631db3ed62b9 drm/i915: Fix readout of PIPEGCMAX
7cef77b47c3f drm/i915: Refactor LUT read functions
1d66b7bd3630 drm/i915: Clean up integer types in color code
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
f7394645c856 drm/i915: s/blob_data/lut/
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
ce81f95570f1 drm/i915: Add i9xx_lut_8()
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
aab7b7b6ba2e drm: Inline drm_color_lut_extract()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15177
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15177 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15177, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15177:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_execlists:
    - fi-icl-dsi:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-dsi/igt@i915_selftest@live_execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-icl-dsi/igt@i915_selftest@live_execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_15177 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-nick:        [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - {fi-tgl-u}:         [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_create@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-tgl-u/igt@gem_exec_create@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6700k2:      [INCOMPLETE][9] ([fdo#104108]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15177

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15177: 4888c33ef45e557085500f6d3196da5c1ee23270 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4888c33ef45e drm/i915: Pass the crtc to the low level read_lut() funcs
631db3ed62b9 drm/i915: Fix readout of PIPEGCMAX
7cef77b47c3f drm/i915: Refactor LUT read functions
1d66b7bd3630 drm/i915: Clean up integer types in color code
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
f7394645c856 drm/i915: s/blob_data/lut/
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
ce81f95570f1 drm/i915: Add i9xx_lut_8()
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
aab7b7b6ba2e drm: Inline drm_color_lut_extract()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
21be37521e2e drm: Inline drm_color_lut_extract()
54271b0bb942 drm/i915: Polish CHV .load_luts() a bit
08381a7f1283 drm/i915: Polish CHV CGM CSC loading
f0e0d4e9637c drm/i915: Add i9xx_lut_8()
30d9559d9b79 drm/i915: Clean up i9xx_load_luts_internal()
7169040bcf48 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
79c86338cbac drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1679:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1681:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1683:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1730:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1732:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1734:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1771:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1773:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1777:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1846:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1848:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1850:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1896:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1898:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1900:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
417c9d10ff93 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
6c7f36dc0f92 drm/i915: Clean up integer types in color code
86a3d4e57744 drm/i915: Refactor LUT read functions
3e2378de6c00 drm/i915: Fix readout of PIPEGCMAX
0f7e8b3f77aa drm/i915: Pass the crtc to the low level read_lut() funcs

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
21be37521e2e drm: Inline drm_color_lut_extract()
54271b0bb942 drm/i915: Polish CHV .load_luts() a bit
08381a7f1283 drm/i915: Polish CHV CGM CSC loading
f0e0d4e9637c drm/i915: Add i9xx_lut_8()
30d9559d9b79 drm/i915: Clean up i9xx_load_luts_internal()
7169040bcf48 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
79c86338cbac drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1679:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1681:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1683:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1730:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 I915_READ(PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1732:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   I915_READ(PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1734:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  I915_READ(PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1771:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1773:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1777:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1846:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1848:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1850:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1896:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1898:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1900:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
417c9d10ff93 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
6c7f36dc0f92 drm/i915: Clean up integer types in color code
86a3d4e57744 drm/i915: Refactor LUT read functions
3e2378de6c00 drm/i915: Fix readout of PIPEGCMAX
0f7e8b3f77aa drm/i915: Pass the crtc to the low level read_lut() funcs

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm: Inline drm_color_lut_extract()
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)

Commit: drm/i915: Polish CHV .load_luts() a bit
Okay!

Commit: drm/i915: Polish CHV CGM CSC loading
Okay!

Commit: drm/i915: Add i9xx_lut_8()
Okay!

Commit: drm/i915: Clean up i9xx_load_luts_internal()
Okay!

Commit: drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
Okay!

Commit: drm/i915: s/blob_data/lut/
Okay!

Commit: drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
Okay!

Commit: drm/i915: Clean up integer types in color code
Okay!

Commit: drm/i915: Refactor LUT read functions
Okay!

Commit: drm/i915: Fix readout of PIPEGCMAX
Okay!

Commit: drm/i915: Pass the crtc to the low level read_lut() funcs
Okay!

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm: Inline drm_color_lut_extract()
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)

Commit: drm/i915: Polish CHV .load_luts() a bit
Okay!

Commit: drm/i915: Polish CHV CGM CSC loading
Okay!

Commit: drm/i915: Add i9xx_lut_8()
Okay!

Commit: drm/i915: Clean up i9xx_load_luts_internal()
Okay!

Commit: drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
Okay!

Commit: drm/i915: s/blob_data/lut/
Okay!

Commit: drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
Okay!

Commit: drm/i915: Clean up integer types in color code
Okay!

Commit: drm/i915: Refactor LUT read functions
Okay!

Commit: drm/i915: Fix readout of PIPEGCMAX
Okay!

Commit: drm/i915: Pass the crtc to the low level read_lut() funcs
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7299 -> Patchwork_15196
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html

Known issues
------------

  Here are the changes found in Patchwork_15196 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-cml-s:           [PASS][1] -> [DMESG-WARN][2] ([fdo#111764])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-cml-s/igt@gem_exec_suspend@basic-s3.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][3] ([fdo#112147]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#111045] / [fdo#111096])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7299 -> Patchwork_15196

  CI-20190529: 20190529
  CI_DRM_7299: e7de48a8b1161a99f4b8e4483bc1bb85f5d31039 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5268: c94958b8f7caefcda72392417ae6f3a98e36a48b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15196: 0f7e8b3f77aa61491647790b3096196051ebf9df @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0f7e8b3f77aa drm/i915: Pass the crtc to the low level read_lut() funcs
3e2378de6c00 drm/i915: Fix readout of PIPEGCMAX
86a3d4e57744 drm/i915: Refactor LUT read functions
6c7f36dc0f92 drm/i915: Clean up integer types in color code
417c9d10ff93 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
79c86338cbac drm/i915: s/blob_data/lut/
7169040bcf48 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
30d9559d9b79 drm/i915: Clean up i9xx_load_luts_internal()
f0e0d4e9637c drm/i915: Add i9xx_lut_8()
08381a7f1283 drm/i915: Polish CHV CGM CSC loading
54271b0bb942 drm/i915: Polish CHV .load_luts() a bit
21be37521e2e drm: Inline drm_color_lut_extract()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7299 -> Patchwork_15196
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html

Known issues
------------

  Here are the changes found in Patchwork_15196 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-cml-s:           [PASS][1] -> [DMESG-WARN][2] ([fdo#111764])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-cml-s/igt@gem_exec_suspend@basic-s3.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][3] ([fdo#112147]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#111045] / [fdo#111096])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7299 -> Patchwork_15196

  CI-20190529: 20190529
  CI_DRM_7299: e7de48a8b1161a99f4b8e4483bc1bb85f5d31039 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5268: c94958b8f7caefcda72392417ae6f3a98e36a48b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15196: 0f7e8b3f77aa61491647790b3096196051ebf9df @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0f7e8b3f77aa drm/i915: Pass the crtc to the low level read_lut() funcs
3e2378de6c00 drm/i915: Fix readout of PIPEGCMAX
86a3d4e57744 drm/i915: Refactor LUT read functions
6c7f36dc0f92 drm/i915: Clean up integer types in color code
417c9d10ff93 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
79c86338cbac drm/i915: s/blob_data/lut/
7169040bcf48 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
30d9559d9b79 drm/i915: Clean up i9xx_load_luts_internal()
f0e0d4e9637c drm/i915: Add i9xx_lut_8()
08381a7f1283 drm/i915: Polish CHV CGM CSC loading
54271b0bb942 drm/i915: Polish CHV .load_luts() a bit
21be37521e2e drm: Inline drm_color_lut_extract()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15196_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_15196_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15196_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15196_full:

### IGT changes ###

#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][1] ([fdo#111865]) -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@i915_pm_dc@dc6-psr.html

  
Known issues
------------

  Here are the changes found in Patchwork_15196_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl2/igt@gem_ctx_isolation@vecs0-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl1/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_exec_create@basic:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111736])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb4/igt@gem_exec_create@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb6/igt@gem_exec_create@basic.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@gem_exec_schedule@in-order-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +16 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb3/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-vebox:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111677])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111832])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb3/igt@gem_exec_suspend@basic-s0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb8/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_request_retire@retire-vma-not-inactive:
    - shard-glk:          [PASS][19] -> [INCOMPLETE][20] ([fdo#103359] / [k.org#198133])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-glk3/igt@gem_request_retire@retire-vma-not-inactive.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-glk8/igt@gem_request_retire@retire-vma-not-inactive.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [PASS][23] -> [INCOMPLETE][24] ([fdo#104108])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rps@waitboost:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#102250])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl7/igt@i915_pm_rps@waitboost.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl7/igt@i915_pm_rps@waitboost.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][27] -> [DMESG-FAIL][28] ([fdo#111991])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw2/igt@i915_selftest@live_hangcheck.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw5/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +5 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [PASS][31] -> [FAIL][32] ([fdo#103167]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([fdo#108566]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [PASS][35] -> [INCOMPLETE][36] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109642] / [fdo#111068])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][41] ([fdo#109276] / [fdo#112080]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@gem_ctx_persistence@vcs1-queued.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [INCOMPLETE][43] ([fdo#111735]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@gem_ctx_shared@q-smoketest-vebox.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [SKIP][45] ([fdo#112080]) -> [PASS][46] +8 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb5/igt@gem_ctx_switch@vcs1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_ctx_switch@vcs1.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][47] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb3/igt@gem_eio@in-flight-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#112146]) -> [PASS][50] +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb7/igt@gem_userptr_blits@dmabuf-sync.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [DMESG-WARN][53] ([fdo#110789] / [fdo#111870]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111832] / [fdo#111850]) -> [PASS][56] +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb1/igt@gem_workarounds@suspend-resume.html

  * igt@i915_selftest@live_requests:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb2/igt@i915_selftest@live_requests.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@i915_selftest@live_requests.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][59] ([fdo#106107]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl4/igt@kms_color@pipe-b-ctm-0-5.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][61] ([fdo#103355]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
    - shard-tglb:         [INCOMPLETE][63] ([fdo#112035 ]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb1/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb3/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][65] ([fdo#102670]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
    - shard-apl:          [DMESG-WARN][67] -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][71] ([fdo#103167]) -> [PASS][72] +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-tglb:         [FAIL][73] ([fdo#103167]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76] +9 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-tglb:         [TIMEOUT][77] ([fdo#112168]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][79] ([fdo#108145] / [fdo#110403]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][81] ([fdo#109441]) -> [PASS][82] +3 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-hsw:          [INCOMPLETE][83] ([fdo#103540]) -> [PASS][84] +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][85] ([fdo#109276]) -> [PASS][86] +14 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][87] ([fdo#111329]) -> [SKIP][88] ([fdo#109276] / [fdo#112080])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_exec_schedule@deep-bsd2:
    - shard-tglb:         [FAIL][89] ([fdo#111646]) -> [INCOMPLETE][90] ([fdo#111671])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb4/igt@gem_exec_schedule@deep-bsd2.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb4/igt@gem_exec_schedule@deep-bsd2.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [FAIL][91] ([fdo#111330]) -> [SKIP][92] ([fdo#109276]) +2 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-skl:          [SKIP][93] ([fdo#109271]) -> [FAIL][94] ([fdo#108686])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl4/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [DMESG-WARN][95] ([fdo#111870]) -> [DMESG-WARN][96] ([fdo#110789] / [fdo#111870])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [DMESG-WARN][97] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][98] ([fdo#111870])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][99] ([fdo#111832] / [fdo#111850]) -> [FAIL][100] ([fdo#111703])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freed

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Gamma cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7299_full -> Patchwork_15196_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_15196_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15196_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15196_full:

### IGT changes ###

#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][1] ([fdo#111865]) -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@i915_pm_dc@dc6-psr.html

  
Known issues
------------

  Here are the changes found in Patchwork_15196_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl2/igt@gem_ctx_isolation@vecs0-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl1/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_exec_create@basic:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111736])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb4/igt@gem_exec_create@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb6/igt@gem_exec_create@basic.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@gem_exec_schedule@in-order-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +16 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb3/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-vebox:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111677])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111832])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb3/igt@gem_exec_suspend@basic-s0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb8/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_request_retire@retire-vma-not-inactive:
    - shard-glk:          [PASS][19] -> [INCOMPLETE][20] ([fdo#103359] / [k.org#198133])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-glk3/igt@gem_request_retire@retire-vma-not-inactive.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-glk8/igt@gem_request_retire@retire-vma-not-inactive.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [PASS][23] -> [INCOMPLETE][24] ([fdo#104108])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rps@waitboost:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#102250])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl7/igt@i915_pm_rps@waitboost.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl7/igt@i915_pm_rps@waitboost.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][27] -> [DMESG-FAIL][28] ([fdo#111991])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw2/igt@i915_selftest@live_hangcheck.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw5/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +5 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [PASS][31] -> [FAIL][32] ([fdo#103167]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([fdo#108566]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [PASS][35] -> [INCOMPLETE][36] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109642] / [fdo#111068])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][41] ([fdo#109276] / [fdo#112080]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@gem_ctx_persistence@vcs1-queued.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [INCOMPLETE][43] ([fdo#111735]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@gem_ctx_shared@q-smoketest-vebox.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [SKIP][45] ([fdo#112080]) -> [PASS][46] +8 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb5/igt@gem_ctx_switch@vcs1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@gem_ctx_switch@vcs1.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][47] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb3/igt@gem_eio@in-flight-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#112146]) -> [PASS][50] +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb7/igt@gem_userptr_blits@dmabuf-sync.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [DMESG-WARN][53] ([fdo#110789] / [fdo#111870]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111832] / [fdo#111850]) -> [PASS][56] +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb1/igt@gem_workarounds@suspend-resume.html

  * igt@i915_selftest@live_requests:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb2/igt@i915_selftest@live_requests.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb7/igt@i915_selftest@live_requests.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][59] ([fdo#106107]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl4/igt@kms_color@pipe-b-ctm-0-5.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][61] ([fdo#103355]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
    - shard-tglb:         [INCOMPLETE][63] ([fdo#112035 ]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb1/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb3/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][65] ([fdo#102670]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
    - shard-apl:          [DMESG-WARN][67] -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][71] ([fdo#103167]) -> [PASS][72] +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-tglb:         [FAIL][73] ([fdo#103167]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76] +9 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-tglb:         [TIMEOUT][77] ([fdo#112168]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][79] ([fdo#108145] / [fdo#110403]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][81] ([fdo#109441]) -> [PASS][82] +3 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-hsw:          [INCOMPLETE][83] ([fdo#103540]) -> [PASS][84] +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-hsw5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-hsw2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][85] ([fdo#109276]) -> [PASS][86] +14 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][87] ([fdo#111329]) -> [SKIP][88] ([fdo#109276] / [fdo#112080])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_exec_schedule@deep-bsd2:
    - shard-tglb:         [FAIL][89] ([fdo#111646]) -> [INCOMPLETE][90] ([fdo#111671])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb4/igt@gem_exec_schedule@deep-bsd2.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb4/igt@gem_exec_schedule@deep-bsd2.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [FAIL][91] ([fdo#111330]) -> [SKIP][92] ([fdo#109276]) +2 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-skl:          [SKIP][93] ([fdo#109271]) -> [FAIL][94] ([fdo#108686])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-skl4/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [DMESG-WARN][95] ([fdo#111870]) -> [DMESG-WARN][96] ([fdo#110789] / [fdo#111870])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [DMESG-WARN][97] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][98] ([fdo#111870])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][99] ([fdo#111832] / [fdo#111850]) -> [FAIL][100] ([fdo#111703])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7299/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freed

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15196/index.html
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