From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> To: intel-gfx@lists.freedesktop.org Cc: Matthew Auld <matthew.auld@intel.com> Subject: [PATCH 3/4] drm/i915: cpu-map based dumb buffers Date: Fri, 15 Nov 2019 13:45:48 +0200 [thread overview] Message-ID: <20191115114549.23716-3-abdiel.janulgue@linux.intel.com> (raw) In-Reply-To: <20191115114549.23716-1-abdiel.janulgue@linux.intel.com> Prefer CPU WC mmaps via our new mmap offset plumbing otherwise fall- back to GTT mmaps when hw doesn't support PAT Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 ++ drivers/gpu/drm/i915/i915_drv.c | 1 + 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index d2ed8a463672..c1756e4f46b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -540,6 +540,24 @@ __assign_gem_object_mmap_data(struct drm_file *file, return ret; } +int +i915_gem_mmap_dumb(struct drm_file *file, + struct drm_device *dev, + u32 handle, + u64 *offset) +{ + enum i915_mmap_type mmap_type; + + if (boot_cpu_has(X86_FEATURE_PAT)) + mmap_type = I915_MMAP_TYPE_WC; + else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt)) + return -ENODEV; + else + mmap_type = I915_MMAP_TYPE_GTT; + + return __assign_gem_object_mmap_data(file, handle, mmap_type, offset); +} + /** * i915_gem_mmap_offset_ioctl - prepare an object for GTT mmap'ing * @dev: DRM device diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h index 4d3b493e853a..6e70b91dabc4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h @@ -24,6 +24,8 @@ void i915_mmap_offset_destroy(struct i915_mmap_offset *mmo, struct mutex *mutex) void __i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj); void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj); +int i915_gem_mmap_dumb(struct drm_file *file_priv, struct drm_device *dev, + u32 handle, u64 *offset); int i915_gem_mmap_gtt_version(void); #endif diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ac6d4470ce75..f7db0bbbe302 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2767,6 +2767,7 @@ static struct drm_driver driver = { .get_scanout_position = i915_get_crtc_scanoutpos, .dumb_create = i915_gem_dumb_create, + .dumb_map_offset = i915_gem_mmap_dumb, .ioctls = i915_ioctls, .num_ioctls = ARRAY_SIZE(i915_ioctls), .fops = &i915_driver_fops, -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> To: intel-gfx@lists.freedesktop.org Cc: Matthew Auld <matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 3/4] drm/i915: cpu-map based dumb buffers Date: Fri, 15 Nov 2019 13:45:48 +0200 [thread overview] Message-ID: <20191115114549.23716-3-abdiel.janulgue@linux.intel.com> (raw) Message-ID: <20191115114548.JVVjO1EP1354P5DHL4ZrJzS36q-yvOkx4nbYofWX5eI@z> (raw) In-Reply-To: <20191115114549.23716-1-abdiel.janulgue@linux.intel.com> Prefer CPU WC mmaps via our new mmap offset plumbing otherwise fall- back to GTT mmaps when hw doesn't support PAT Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 ++ drivers/gpu/drm/i915/i915_drv.c | 1 + 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index d2ed8a463672..c1756e4f46b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -540,6 +540,24 @@ __assign_gem_object_mmap_data(struct drm_file *file, return ret; } +int +i915_gem_mmap_dumb(struct drm_file *file, + struct drm_device *dev, + u32 handle, + u64 *offset) +{ + enum i915_mmap_type mmap_type; + + if (boot_cpu_has(X86_FEATURE_PAT)) + mmap_type = I915_MMAP_TYPE_WC; + else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt)) + return -ENODEV; + else + mmap_type = I915_MMAP_TYPE_GTT; + + return __assign_gem_object_mmap_data(file, handle, mmap_type, offset); +} + /** * i915_gem_mmap_offset_ioctl - prepare an object for GTT mmap'ing * @dev: DRM device diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h index 4d3b493e853a..6e70b91dabc4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h @@ -24,6 +24,8 @@ void i915_mmap_offset_destroy(struct i915_mmap_offset *mmo, struct mutex *mutex) void __i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj); void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj); +int i915_gem_mmap_dumb(struct drm_file *file_priv, struct drm_device *dev, + u32 handle, u64 *offset); int i915_gem_mmap_gtt_version(void); #endif diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ac6d4470ce75..f7db0bbbe302 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2767,6 +2767,7 @@ static struct drm_driver driver = { .get_scanout_position = i915_get_crtc_scanoutpos, .dumb_create = i915_gem_dumb_create, + .dumb_map_offset = i915_gem_mmap_dumb, .ioctls = i915_ioctls, .num_ioctls = ARRAY_SIZE(i915_ioctls), .fops = &i915_driver_fops, -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-15 11:45 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-15 11:45 [PATCH 1/4] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core Abdiel Janulgue 2019-11-15 11:45 ` [Intel-gfx] " Abdiel Janulgue 2019-11-15 11:45 ` [PATCH 2/4] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET Abdiel Janulgue 2019-11-15 11:45 ` [Intel-gfx] " Abdiel Janulgue 2019-11-15 13:51 ` Chris Wilson 2019-11-15 13:51 ` [Intel-gfx] " Chris Wilson 2019-11-15 14:31 ` Chris Wilson 2019-11-15 14:31 ` [Intel-gfx] " Chris Wilson 2019-11-15 11:45 ` Abdiel Janulgue [this message] 2019-11-15 11:45 ` [Intel-gfx] [PATCH 3/4] drm/i915: cpu-map based dumb buffers Abdiel Janulgue 2019-11-15 13:54 ` Chris Wilson 2019-11-15 13:54 ` [Intel-gfx] " Chris Wilson 2019-11-15 14:26 ` Chris Wilson 2019-11-15 14:26 ` [Intel-gfx] " Chris Wilson 2019-11-15 11:45 ` [PATCH 4/4] drm/i915: Add cpu fault handler for mmap_offset Abdiel Janulgue 2019-11-15 11:45 ` [Intel-gfx] " Abdiel Janulgue 2019-11-15 13:58 ` Chris Wilson 2019-11-15 13:58 ` [Intel-gfx] " Chris Wilson 2019-11-15 13:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core Patchwork 2019-11-15 13:56 ` [Intel-gfx] " Patchwork 2019-11-15 13:57 ` ✗ Fi.CI.SPARSE: " Patchwork 2019-11-15 13:57 ` [Intel-gfx] " Patchwork 2019-11-15 14:17 ` [PATCH 1/4] " Chris Wilson 2019-11-15 14:17 ` [Intel-gfx] " Chris Wilson 2019-11-15 14:23 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] " Patchwork 2019-11-15 14:23 ` [Intel-gfx] " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2019-11-19 11:37 [PATCH 1/4] " Abdiel Janulgue 2019-11-19 11:37 ` [PATCH 3/4] drm/i915: cpu-map based dumb buffers Abdiel Janulgue 2019-11-14 19:09 [PATCH 1/4] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core Abdiel Janulgue 2019-11-14 19:09 ` [PATCH 3/4] drm/i915: cpu-map based dumb buffers Abdiel Janulgue
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