* [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework
@ 2020-01-20 17:47 Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
` (23 more replies)
0 siblings, 24 replies; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Here's an attempt at making the ad-hoc global state handling more
standardized like the private obj stuff. As the first excercise we
convert the bandwidth and cdclk states to use this. Another future
target for this is probably ddb/fifo allocation for the pipes.
Entire series available here:
git://github.com/vsyrjala/linux.git global_state_rework_2
Ville Syrjälä (17):
drm/i915: Polish WM_LINETIME register stuff
drm/i915: Move linetime wms into the crtc state
drm/i915: Nuke skl wm.dirty_pipes bitmask
drm/i915: Move more cdclk state handling into the cdclk code
drm/i915: Collect more cdclk state under the same roof
drm/i915: s/need_cd2x_updare/can_cd2x_update/
drm/i915: s/cdclk_state/cdclk_config/
drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling
convention
drm/i915: Extract intel_cdclk_state
drm/i915: swap() the entire cdclk state
drm/i915: s/init_cdclk/init_cdclk_hw/
drm/i915: Move intel_atomic_state_free() into intel_atomic.c
drm/i915: Intrduce better global state handling
drm/i915: Convert bandwidth state to global state
drm/i915: Introduce intel_calc_active_pipes()
drm/i915: Convert cdclk to global state
drm/i915: Store active_pipes bitmask in cdclk state
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 26 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 5 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 66 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
drivers/gpu/drm/i915/display/intel_audio.c | 39 +-
drivers/gpu/drm/i915/display/intel_bw.c | 31 +-
drivers/gpu/drm/i915/display/intel_bw.h | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 748 ++++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 71 +-
drivers/gpu/drm/i915/display/intel_display.c | 297 +++++--
drivers/gpu/drm/i915/display/intel_display.h | 3 +
.../drm/i915/display/intel_display_power.c | 24 +-
.../drm/i915/display/intel_display_types.h | 35 +-
.../gpu/drm/i915/display/intel_global_state.c | 223 ++++++
.../gpu/drm/i915/display/intel_global_state.h | 87 ++
drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 48 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 147 +---
20 files changed, 1147 insertions(+), 733 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
` (22 subsequent siblings)
23 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's store the normal and IPS linetime watermarks individually,
and while at it we'll pimp the register definitions as well.
v2: Deal with gvt
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 14 ++--
drivers/gpu/drm/i915/intel_pm.c | 67 ++++++++++---------
4 files changed, 49 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 155ce49ae764..bfe85e180e16 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -662,7 +662,8 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- u32 linetime;
+ u16 linetime;
+ u16 ips_linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6d28d72e6c7e..18475dd377ed 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2415,9 +2415,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
MMIO_D(SPLL_CTL, D_ALL);
MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..ba023bbf545b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10538,13 +10538,13 @@ enum skl_power_gate {
#define D_COMP_COMP_DISABLE (1 << 0)
/* Pipe WM_LINETIME - watermark line time */
-#define _PIPE_WM_LINETIME_A 0x45270
-#define _PIPE_WM_LINETIME_B 0x45274
-#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
-#define PIPE_WM_LINETIME_MASK (0x1ff)
-#define PIPE_WM_LINETIME_TIME(x) ((x))
-#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
-#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
+#define _WM_LINETIME_A 0x45270
+#define _WM_LINETIME_B 0x45274
+#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
+#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
+#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
+#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
+#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
/* SFUSE_STRAP */
#define SFUSE_STRAP _MMIO(0xc2014)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 81e5a3278fda..a4b66ee1e3d8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2811,31 +2811,31 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
}
static u32
-hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
+hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
- const struct intel_atomic_state *intel_state =
- to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- u32 linetime, ips_linetime;
if (!crtc_state->hw.active)
return 0;
- if (WARN_ON(adjusted_mode->crtc_clock == 0))
- return 0;
- if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
- return 0;
- /* The WM are computed with base on how long it takes to fill a single
- * row at the given clock rate, multiplied by 8.
- * */
- linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
- ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- intel_state->cdclk.logical.cdclk);
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ adjusted_mode->crtc_clock);
+}
+
+static u32
+hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.active)
+ return 0;
- return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
- PIPE_WM_LINETIME_TIME(linetime);
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ state->cdclk.logical.cdclk);
}
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
@@ -3178,8 +3178,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ pipe_wm->linetime = hsw_linetime_wm(crtc_state);
+ pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state);
+ }
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3426,13 +3428,14 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
/* LP0 register values */
for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
enum pipe pipe = intel_crtc->pipe;
- const struct intel_wm_level *r =
- &intel_crtc->wm.active.ilk.wm[0];
+ const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
+ const struct intel_wm_level *r = &pipe_wm->wm[0];
if (WARN_ON(!r->enable))
continue;
-
- results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
+ results->wm_linetime[pipe] =
+ HSW_LINETIME(pipe_wm->linetime) |
+ HSW_IPS_LINETIME(pipe_wm->ips_linetime);
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
@@ -3585,11 +3588,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
if (dirty & WM_DIRTY_LINETIME(PIPE_A))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
+ I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]);
if (dirty & WM_DIRTY_LINETIME(PIPE_B))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
+ I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]);
if (dirty & WM_DIRTY_LINETIME(PIPE_C))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
+ I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]);
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -5568,7 +5571,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
return;
- I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
+ I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
}
static void skl_initial_wm(struct intel_atomic_state *state,
@@ -5713,7 +5716,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
if (!crtc->active)
return;
- out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
+ val = I915_READ(WM_LINETIME(pipe));
+ out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
}
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
@@ -5755,7 +5759,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
+ hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -5774,7 +5778,10 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
- active->linetime = hw->wm_linetime[pipe];
+ active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
+ hw->wm_linetime[pipe]);
+ active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
+ hw->wm_linetime[pipe]);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-29 14:05 ` Lisovskiy, Stanislav
2020-01-31 15:07 ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
` (21 subsequent siblings)
23 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The linetime watermarks really have very little in common with the
plane watermarks. It looks to be cleaner to simply track them in
the crtc_state and program them from the normal modeset/fastset
paths.
The only dark cloud comes from the fact that the register is
still supposedly single buffered. So in theory it might still
need some form of two stage programming. Note that even though
HSW/BDWhave two stage programming we never computed any special
intermediate values for the linetime watermarks, and on SKL+
we don't even have the two stage stuff plugged in since everything
else is double buffered. So let's assume it's all fine and
continue doing what we've been doing.
Actually on HSW/BDW the value should not even change without
a full modeset since it doesn't account for pfit downscaling.
Thus only fastboot might be affected. But on SKL+ the pfit
scaling factor is take into consideration so the value may
change during any fastset.
As a bonus we'll plug this thing into the state
checker/dump now.
v2: Rebase due to bigjoiner prep
v2: Only compute ips linetime for IPS capable pipes.
Bspec says the register values is ignored for other
pipes, but in fact it can't even be written so the
state checker becomes unhappy if we don't compute
it as zero.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 95 +++++++++++++-
.../drm/i915/display/intel_display_types.h | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 117 +-----------------
4 files changed, 98 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 76c17341df2b..8dcb86c51aaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6885,6 +6885,16 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ I915_WRITE(WM_LINETIME(crtc->pipe),
+ HSW_LINETIME(crtc_state->linetime) |
+ HSW_IPS_LINETIME(crtc_state->ips_linetime));
+}
+
static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -6969,6 +6979,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) < 9)
intel_disable_primary_plane(new_crtc_state);
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
@@ -10947,6 +10959,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
enum intel_display_power_domain power_domain;
u64 power_domain_mask;
bool active;
+ u32 tmp;
pipe_config->master_transcoder = INVALID_TRANSCODER;
@@ -11010,7 +11023,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
if (INTEL_GEN(dev_priv) >= 9) {
- u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
+ tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
pipe_config->gamma_enable = true;
@@ -11023,6 +11036,12 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_color_get_config(pipe_config);
+ tmp = I915_READ(WM_LINETIME(crtc->pipe));
+ pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ pipe_config->ips_linetime =
+ REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
+
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
WARN_ON(power_domain_mask & BIT_ULL(power_domain));
@@ -12508,6 +12527,53 @@ static int icl_compute_port_sync_crtc_state(struct drm_connector *connector,
return 0;
}
+static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ adjusted_mode->crtc_clock);
+}
+
+static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ state->cdclk.logical.cdclk);
+}
+
+static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ u16 linetime_wm;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
+ crtc_state->pixel_rate);
+
+ /* Display WA #1135: BXT:ALL GLK:ALL */
+ if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
+ linetime_wm /= 2;
+
+ return linetime_wm;
+}
+
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -12579,6 +12645,14 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (HAS_IPS(dev_priv))
crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
+ if (INTEL_GEN(dev_priv) >= 9) {
+ crtc_state->linetime = skl_linetime_wm(crtc_state);
+ } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ crtc_state->linetime = hsw_linetime_wm(crtc_state);
+ if (hsw_crtc_supports_ips(crtc))
+ crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
+ }
+
return ret;
}
@@ -12868,6 +12942,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
pipe_config->pixel_rate);
+ DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n",
+ pipe_config->linetime, pipe_config->ips_linetime);
+
if (INTEL_GEN(dev_priv) >= 9)
DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
crtc->num_scalers,
@@ -13638,10 +13715,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+ PIPE_CONF_CHECK_I(linetime);
+ PIPE_CONF_CHECK_I(ips_linetime);
+
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
-
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -14798,6 +14877,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
ilk_pfit_disable(old_crtc_state);
}
+ /*
+ * The register is supposedly single buffered so perhaps
+ * not 100% correct to do this here. But SKL+ calculate
+ * this based on the adjust pixel rate so pfit changes do
+ * affect it and so it must be updated for fastsets.
+ * HSW/BDW only really need this here for fastboot, after
+ * that the value should not change without a full modeset.
+ */
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bfe85e180e16..2d8491590501 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -662,8 +662,6 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- u16 linetime;
- u16 ips_linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
@@ -679,7 +677,6 @@ struct skl_plane_wm {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
- u32 linetime;
};
enum vlv_wm_level {
@@ -1050,6 +1047,10 @@ struct intel_crtc_state {
struct drm_dsc_config config;
} dsc;
+ /* HSW+ linetime watermarks */
+ u16 linetime;
+ u16 ips_linetime;
+
/* Forward Error correction State */
bool fec_enable;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 077af22b8340..5bd40184ddee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -744,7 +744,6 @@ struct ilk_wm_values {
u32 wm_pipe[3];
u32 wm_lp[3];
u32 wm_lp_spr[3];
- u32 wm_linetime[3];
bool enable_fbc_wm;
enum intel_ddb_partitioning partitioning;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a4b66ee1e3d8..edd62367006d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2810,34 +2810,6 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
-static u32
-hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
-}
-
-static u32
-hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- state->cdclk.logical.cdclk);
-}
-
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[8])
{
@@ -3178,11 +3150,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- pipe_wm->linetime = hsw_linetime_wm(crtc_state);
- pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state);
- }
-
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3433,9 +3400,6 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] =
- HSW_LINETIME(pipe_wm->linetime) |
- HSW_IPS_LINETIME(pipe_wm->ips_linetime);
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
@@ -3475,7 +3439,6 @@ ilk_find_best_result(struct drm_i915_private *dev_priv,
/* dirty bits used to track which watermarks need changes */
#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
-#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
#define WM_DIRTY_FBC (1 << 24)
@@ -3490,12 +3453,6 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
int wm_lp;
for_each_pipe(dev_priv, pipe) {
- if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
- dirty |= WM_DIRTY_LINETIME(pipe);
- /* Must disable LP1+ watermarks too */
- dirty |= WM_DIRTY_LP_ALL;
- }
-
if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
dirty |= WM_DIRTY_PIPE(pipe);
/* Must disable LP1+ watermarks too */
@@ -3587,13 +3544,6 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_PIPE(PIPE_C))
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_A))
- I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_B))
- I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_C))
- I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]);
-
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = I915_READ(WM_MISC);
@@ -4847,24 +4797,6 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
-static u32
-skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct drm_i915_private *dev_priv = to_i915(state->dev);
- uint_fixed_16_16_t linetime_us;
- u32 linetime_wm;
-
- linetime_us = intel_get_linetime_us(crtc_state);
- linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
-
- /* Display WA #1135: BXT:ALL GLK:ALL */
- if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
- linetime_wm /= 2;
-
- return linetime_wm;
-}
-
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5052,8 +4984,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
return ret;
}
- pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
-
return 0;
}
@@ -5178,7 +5108,7 @@ static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
return false;
}
- return wm1->linetime == wm2->linetime;
+ return true;
}
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
@@ -5559,40 +5489,6 @@ skl_compute_wm(struct intel_atomic_state *state)
return 0;
}
-static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- enum pipe pipe = crtc->pipe;
-
- if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
-}
-
-static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_ddb_values *results = &state->wm_results;
-
- if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- mutex_lock(&dev_priv->wm.wm_mutex);
-
- if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc);
-
- mutex_unlock(&dev_priv->wm.wm_mutex);
-}
-
static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
struct intel_wm_config *config)
{
@@ -5715,9 +5611,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
if (!crtc->active)
return;
-
- val = I915_READ(WM_LINETIME(pipe));
- out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
}
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
@@ -5758,8 +5651,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
};
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -5778,10 +5669,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
- active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
- hw->wm_linetime[pipe]);
- active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
- hw->wm_linetime[pipe]);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -7264,8 +7151,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.initial_watermarks = skl_initial_wm;
- dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
--
2.24.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
` (20 subsequent siblings)
23 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The dirty_pipes bitmask is now unused. Get rid of it.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 35 +--------------------------------
2 files changed, 1 insertion(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bd40184ddee..a7f6275a79e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -803,7 +803,6 @@ struct skl_ddb_allocation {
};
struct skl_ddb_values {
- unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index edd62367006d..811e55e53b39 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5094,23 +5094,6 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
}
-static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
- const struct skl_pipe_wm *wm1,
- const struct skl_pipe_wm *wm2)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum plane_id plane_id;
-
- for_each_plane_id_on_crtc(crtc, plane_id) {
- if (!skl_plane_wm_equals(dev_priv,
- &wm1->planes[plane_id],
- &wm2->planes[plane_id]))
- return false;
- }
-
- return true;
-}
-
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
const struct skl_ddb_entry *b)
{
@@ -5372,8 +5355,6 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
* to grab the lock on *all* CRTC's.
*/
if (state->active_pipe_changes || state->modeset) {
- state->wm_results.dirty_pipes = INTEL_INFO(dev_priv)->pipe_mask;
-
ret = intel_add_all_pipes(state);
if (ret)
return ret;
@@ -5448,12 +5429,8 @@ skl_compute_wm(struct intel_atomic_state *state)
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc_state *old_crtc_state;
- struct skl_ddb_values *results = &state->wm_results;
int ret, i;
- /* Clear all dirty flags */
- results->dirty_pipes = 0;
-
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
@@ -5461,8 +5438,7 @@ skl_compute_wm(struct intel_atomic_state *state)
/*
* Calculate WM's for all pipes that are part of this transaction.
* Note that skl_ddb_add_affected_pipes may have added more CRTC's that
- * weren't otherwise being modified (and set bits in dirty_pipes) if
- * pipe allocations had to change.
+ * weren't otherwise being modified if pipe allocations had to change.
*/
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -5473,11 +5449,6 @@ skl_compute_wm(struct intel_atomic_state *state)
ret = skl_wm_add_affected_planes(state, crtc);
if (ret)
return ret;
-
- if (!skl_pipe_wm_equals(crtc,
- &old_crtc_state->wm.skl.optimal,
- &new_crtc_state->wm.skl.optimal))
- results->dirty_pipes |= BIT(crtc->pipe);
}
ret = skl_compute_ddb(state);
@@ -5615,7 +5586,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
@@ -5625,9 +5595,6 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
crtc_state = to_intel_crtc_state(crtc->base.state);
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
-
- if (crtc->active)
- hw->dirty_pipes |= BIT(crtc->pipe);
}
if (dev_priv->active_pipes) {
--
2.24.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (2 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 18:39 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
` (19 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the initial setup of state->{cdclk,min_cdclk[],min_voltage_level[]}
into intel_modeset_calc_cdclk(), and we'll move the counterparts into
intel_cdclk_swap_state(). This encapsulates the cdclk state much better.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 +++++++++++++++-----
drivers/gpu/drm/i915/display/intel_display.c | 11 ---------
2 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0ce5926006ca..05f6c6456ddf 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1819,6 +1819,14 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ /* FIXME maybe swap() these too */
+ memcpy(dev_priv->min_cdclk, state->min_cdclk,
+ sizeof(state->min_cdclk));
+ memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
+ sizeof(state->min_voltage_level));
+
+ dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
+
swap(state->cdclk.logical, dev_priv->cdclk.logical);
swap(state->cdclk.actual, dev_priv->cdclk.actual);
}
@@ -2033,9 +2041,6 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
int min_cdclk, i;
enum pipe pipe;
- memcpy(state->min_cdclk, dev_priv->min_cdclk,
- sizeof(state->min_cdclk));
-
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2082,9 +2087,6 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
int i;
enum pipe pipe;
- memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
- sizeof(state->min_voltage_level));
-
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2339,6 +2341,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
enum pipe pipe;
int ret;
+ memcpy(state->min_cdclk, dev_priv->min_cdclk,
+ sizeof(state->min_cdclk));
+ memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
+ sizeof(state->min_voltage_level));
+
+ /* keep the current setting */
+ if (!state->cdclk.force_min_cdclk_changed)
+ state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
+ state->cdclk.logical = dev_priv->cdclk.logical;
+ state->cdclk.actual = dev_priv->cdclk.actual;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8dcb86c51aaa..930e9256596c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14360,14 +14360,8 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
- /* keep the current setting */
- if (!state->cdclk.force_min_cdclk_changed)
- state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
-
state->modeset = true;
state->active_pipes = dev_priv->active_pipes;
- state->cdclk.logical = dev_priv->cdclk.logical;
- state->cdclk.actual = dev_priv->cdclk.actual;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -15673,12 +15667,7 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
- memcpy(dev_priv->min_cdclk, state->min_cdclk,
- sizeof(state->min_cdclk));
- memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
- sizeof(state->min_voltage_level));
dev_priv->active_pipes = state->active_pipes;
- dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
intel_cdclk_swap_state(state);
}
--
2.24.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (3 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 18:43 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
` (18 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the min_cdclk[] and min_voltage_level[] arrays under the
rest of the cdclk state. And while at it provide a simple
helper (intel_cdclk_clear_state()) to clear the state during
the ww_mutex backoff dance.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 ++---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++-------
drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
.../drm/i915/display/intel_display_types.h | 10 +++--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
6 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index c362eecdd414..1269f63ea006 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -35,6 +35,7 @@
#include <drm/drm_plane_helper.h>
#include "intel_atomic.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
@@ -497,15 +498,13 @@ intel_atomic_state_alloc(struct drm_device *dev)
void intel_atomic_state_clear(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
+
drm_atomic_state_default_clear(&state->base);
+
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
- memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
- memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level));
- memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
- memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
- state->cdclk.pipe = INVALID_PIPE;
+ intel_cdclk_clear_state(state);
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 05f6c6456ddf..f7f886dcd6ae 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1803,6 +1803,18 @@ static bool intel_cdclk_changed(const struct intel_cdclk_state *a,
a->voltage_level != b->voltage_level;
}
+/**
+ * intel_cdclk_clear_state - clear the cdclk state
+ * @state: atomic state
+ *
+ * Clear the cdclk state for ww_mutex backoff.
+ */
+void intel_cdclk_clear_state(struct intel_atomic_state *state)
+{
+ memset(&state->cdclk, 0, sizeof(state->cdclk));
+ state->cdclk.pipe = INVALID_PIPE;
+}
+
/**
* intel_cdclk_swap_state - make atomic CDCLK configuration effective
* @state: atomic state
@@ -1820,10 +1832,10 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
/* FIXME maybe swap() these too */
- memcpy(dev_priv->min_cdclk, state->min_cdclk,
- sizeof(state->min_cdclk));
- memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
- sizeof(state->min_voltage_level));
+ memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk,
+ sizeof(state->cdclk.min_cdclk));
+ memcpy(dev_priv->cdclk.min_voltage_level, state->cdclk.min_voltage_level,
+ sizeof(state->cdclk.min_voltage_level));
dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
@@ -2048,10 +2060,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
if (min_cdclk < 0)
return min_cdclk;
- if (state->min_cdclk[i] == min_cdclk)
+ if (state->cdclk.min_cdclk[i] == min_cdclk)
continue;
- state->min_cdclk[i] = min_cdclk;
+ state->cdclk.min_cdclk[i] = min_cdclk;
ret = intel_atomic_lock_global_state(state);
if (ret)
@@ -2060,7 +2072,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
min_cdclk = state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
- min_cdclk = max(state->min_cdclk[pipe], min_cdclk);
+ min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk);
return min_cdclk;
}
@@ -2095,10 +2107,10 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
else
min_voltage_level = 0;
- if (state->min_voltage_level[i] == min_voltage_level)
+ if (state->cdclk.min_voltage_level[i] == min_voltage_level)
continue;
- state->min_voltage_level[i] = min_voltage_level;
+ state->cdclk.min_voltage_level[i] = min_voltage_level;
ret = intel_atomic_lock_global_state(state);
if (ret)
@@ -2107,7 +2119,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
min_voltage_level = 0;
for_each_pipe(dev_priv, pipe)
- min_voltage_level = max(state->min_voltage_level[pipe],
+ min_voltage_level = max(state->cdclk.min_voltage_level[pipe],
min_voltage_level);
return min_voltage_level;
@@ -2341,10 +2353,10 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
enum pipe pipe;
int ret;
- memcpy(state->min_cdclk, dev_priv->min_cdclk,
- sizeof(state->min_cdclk));
- memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
- sizeof(state->min_voltage_level));
+ memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk,
+ sizeof(state->cdclk.min_cdclk));
+ memcpy(state->cdclk.min_voltage_level, dev_priv->cdclk.min_voltage_level,
+ sizeof(state->cdclk.min_voltage_level));
/* keep the current setting */
if (!state->cdclk.force_min_cdclk_changed)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index cf71394cc79c..3f3773c582ae 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -31,6 +31,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
+void intel_cdclk_clear_state(struct intel_atomic_state *state);
void intel_cdclk_swap_state(struct intel_atomic_state *state);
void
intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 930e9256596c..f3f9fe94ed41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7547,8 +7547,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
crtc->enabled_power_domains = 0;
dev_priv->active_pipes &= ~BIT(pipe);
- dev_priv->min_cdclk[pipe] = 0;
- dev_priv->min_voltage_level[pipe] = 0;
+ dev_priv->cdclk.min_cdclk[pipe] = 0;
+ dev_priv->cdclk.min_voltage_level[pipe] = 0;
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
@@ -18251,8 +18251,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
min_cdclk = 0;
}
- dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
- dev_priv->min_voltage_level[crtc->pipe] =
+ dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk;
+ dev_priv->cdclk.min_voltage_level[crtc->pipe] =
crtc_state->min_voltage_level;
intel_bw_crtc_update(bw_state, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2d8491590501..a6b95a8ab323 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -477,6 +477,12 @@ struct intel_atomic_state {
int force_min_cdclk;
bool force_min_cdclk_changed;
+
+ /* minimum acceptable cdclk for each pipe */
+ int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
+
/* pipe to which cd2x update is synchronized */
enum pipe pipe;
} cdclk;
@@ -494,10 +500,6 @@ struct intel_atomic_state {
u8 active_pipe_changes;
u8 active_pipes;
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a7f6275a79e6..650f42bd9cfb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1027,6 +1027,11 @@ struct drm_i915_private {
const struct intel_cdclk_vals *table;
int force_min_cdclk;
+
+ /* minimum acceptable cdclk for each pipe */
+ int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
} cdclk;
/**
@@ -1087,10 +1092,6 @@ struct drm_i915_private {
* any crtc lock is sufficient, for writing must hold all of them.
*/
u8 active_pipes;
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (4 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-24 12:24 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
` (17 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_cdclk_needs_cd2x_update() is named rather confusingly.
We don't have to do a cd2x update, rather we are allowed to
do one (as opposed to a full PLL reprogramming with its heavy
handed modeset). So let's rename the function to
intel_cdclk_can_cd2x_update().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7f886dcd6ae..9d4cf412b65d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1767,7 +1767,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
}
/**
- * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
+ * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need a cd2x divider update
* @dev_priv: Not a CDCLK state, it's the drm_i915_private!
* @a: first CDCLK state
* @b: second CDCLK state
@@ -1775,9 +1775,9 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
* Returns:
* True if the CDCLK states require just a cd2x divider update, false if not.
*/
-static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
{
/* Older hw doesn't have the capability */
if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
@@ -2393,9 +2393,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
}
if (is_power_of_2(state->active_pipes) &&
- intel_cdclk_needs_cd2x_update(dev_priv,
- &dev_priv->cdclk.actual,
- &state->cdclk.actual)) {
+ intel_cdclk_can_cd2x_update(dev_priv,
+ &dev_priv->cdclk.actual,
+ &state->cdclk.actual)) {
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (5 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
` (16 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I want to have a higher level cdclk state object so let's rename
the current lower level thing to cdclk_config (because I lack
imagination).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 426 +++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c | 8 +-
.../drm/i915/display/intel_display_types.h | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 20 +-
6 files changed, 246 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9d4cf412b65d..2a5491eb8af3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -55,43 +55,43 @@
*/
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
}
static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 200000;
+ cdclk_config->cdclk = 200000;
}
static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 266667;
+ cdclk_config->cdclk = 266667;
}
static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 333333;
+ cdclk_config->cdclk = 333333;
}
static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 400000;
+ cdclk_config->cdclk = 400000;
}
static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
}
static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
u16 hpllcc = 0;
@@ -102,7 +102,7 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
* FIXME is this the right way to detect 852GM/852GMV?
*/
if (pdev->revision == 0x1) {
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
return;
}
@@ -116,24 +116,24 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
case GC_CLOCK_133_200:
case GC_CLOCK_133_200_2:
case GC_CLOCK_100_200:
- cdclk_state->cdclk = 200000;
+ cdclk_config->cdclk = 200000;
break;
case GC_CLOCK_166_250:
- cdclk_state->cdclk = 250000;
+ cdclk_config->cdclk = 250000;
break;
case GC_CLOCK_100_133:
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
break;
case GC_CLOCK_133_266:
case GC_CLOCK_133_266_2:
case GC_CLOCK_166_266:
- cdclk_state->cdclk = 266667;
+ cdclk_config->cdclk = 266667;
break;
}
}
static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
u16 gcfgc = 0;
@@ -141,23 +141,23 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
pci_read_config_word(pdev, GCFGC, &gcfgc);
if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
return;
}
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
case GC_DISPLAY_CLOCK_333_320_MHZ:
- cdclk_state->cdclk = 333333;
+ cdclk_config->cdclk = 333333;
break;
default:
case GC_DISPLAY_CLOCK_190_200_MHZ:
- cdclk_state->cdclk = 190000;
+ cdclk_config->cdclk = 190000;
break;
}
}
static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
u16 gcfgc = 0;
@@ -165,17 +165,17 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
pci_read_config_word(pdev, GCFGC, &gcfgc);
if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
return;
}
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
case GC_DISPLAY_CLOCK_333_320_MHZ:
- cdclk_state->cdclk = 320000;
+ cdclk_config->cdclk = 320000;
break;
default:
case GC_DISPLAY_CLOCK_190_200_MHZ:
- cdclk_state->cdclk = 200000;
+ cdclk_config->cdclk = 200000;
break;
}
}
@@ -250,7 +250,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
}
static void g33_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
@@ -261,7 +261,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_state->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(dev_priv);
pci_read_config_word(pdev, GCFGC, &tmp);
@@ -270,7 +270,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
if (cdclk_sel >= ARRAY_SIZE(div_3200))
goto fail;
- switch (cdclk_state->vco) {
+ switch (cdclk_config->vco) {
case 3200000:
div_table = div_3200;
break;
@@ -287,18 +287,18 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
goto fail;
}
- cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
- div_table[cdclk_sel]);
+ cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
+ div_table[cdclk_sel]);
return;
fail:
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
- cdclk_state->vco, tmp);
- cdclk_state->cdclk = 190476;
+ cdclk_config->vco, tmp);
+ cdclk_config->cdclk = 190476;
}
static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
u16 gcfgc = 0;
@@ -307,31 +307,31 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
case GC_DISPLAY_CLOCK_267_MHZ_PNV:
- cdclk_state->cdclk = 266667;
+ cdclk_config->cdclk = 266667;
break;
case GC_DISPLAY_CLOCK_333_MHZ_PNV:
- cdclk_state->cdclk = 333333;
+ cdclk_config->cdclk = 333333;
break;
case GC_DISPLAY_CLOCK_444_MHZ_PNV:
- cdclk_state->cdclk = 444444;
+ cdclk_config->cdclk = 444444;
break;
case GC_DISPLAY_CLOCK_200_MHZ_PNV:
- cdclk_state->cdclk = 200000;
+ cdclk_config->cdclk = 200000;
break;
default:
DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
/* fall through */
case GC_DISPLAY_CLOCK_133_MHZ_PNV:
- cdclk_state->cdclk = 133333;
+ cdclk_config->cdclk = 133333;
break;
case GC_DISPLAY_CLOCK_167_MHZ_PNV:
- cdclk_state->cdclk = 166667;
+ cdclk_config->cdclk = 166667;
break;
}
}
static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
static const u8 div_3200[] = { 16, 10, 8 };
@@ -341,7 +341,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_state->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(dev_priv);
pci_read_config_word(pdev, GCFGC, &tmp);
@@ -350,7 +350,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
if (cdclk_sel >= ARRAY_SIZE(div_3200))
goto fail;
- switch (cdclk_state->vco) {
+ switch (cdclk_config->vco) {
case 3200000:
div_table = div_3200;
break;
@@ -364,62 +364,62 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
goto fail;
}
- cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
- div_table[cdclk_sel]);
+ cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
+ div_table[cdclk_sel]);
return;
fail:
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
- cdclk_state->vco, tmp);
- cdclk_state->cdclk = 200000;
+ cdclk_config->vco, tmp);
+ cdclk_config->cdclk = 200000;
}
static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_state->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(dev_priv);
pci_read_config_word(pdev, GCFGC, &tmp);
cdclk_sel = (tmp >> 12) & 0x1;
- switch (cdclk_state->vco) {
+ switch (cdclk_config->vco) {
case 2666667:
case 4000000:
case 5333333:
- cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
+ cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
break;
case 3200000:
- cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
+ cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
break;
default:
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
- cdclk_state->vco, tmp);
- cdclk_state->cdclk = 222222;
+ cdclk_config->vco, tmp);
+ cdclk_config->cdclk = 222222;
break;
}
}
static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 lcpll = I915_READ(LCPLL_CTL);
u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
- cdclk_state->cdclk = 800000;
+ cdclk_config->cdclk = 800000;
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
else if (freq == LCPLL_CLK_FREQ_450)
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
else if (IS_HSW_ULT(dev_priv))
- cdclk_state->cdclk = 337500;
+ cdclk_config->cdclk = 337500;
else
- cdclk_state->cdclk = 540000;
+ cdclk_config->cdclk = 540000;
}
static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
@@ -462,17 +462,17 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
}
static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 val;
vlv_iosf_sb_get(dev_priv,
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
- cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
- cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
- CCK_DISPLAY_CLOCK_CONTROL,
- cdclk_state->vco);
+ cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
+ cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
+ CCK_DISPLAY_CLOCK_CONTROL,
+ cdclk_config->vco);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -480,10 +480,10 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
if (IS_VALLEYVIEW(dev_priv))
- cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
+ cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
DSPFREQGUAR_SHIFT;
else
- cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
+ cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
DSPFREQGUAR_SHIFT_CHV;
}
@@ -524,11 +524,11 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
}
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- int cdclk = cdclk_state->cdclk;
- u32 val, cmd = cdclk_state->voltage_level;
+ int cdclk = cdclk_config->cdclk;
+ u32 val, cmd = cdclk_config->voltage_level;
intel_wakeref_t wakeref;
switch (cdclk) {
@@ -611,11 +611,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- int cdclk = cdclk_state->cdclk;
- u32 val, cmd = cdclk_state->voltage_level;
+ int cdclk = cdclk_config->cdclk;
+ u32 val, cmd = cdclk_config->voltage_level;
intel_wakeref_t wakeref;
switch (cdclk) {
@@ -685,37 +685,37 @@ static u8 bdw_calc_voltage_level(int cdclk)
}
static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 lcpll = I915_READ(LCPLL_CTL);
u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
- cdclk_state->cdclk = 800000;
+ cdclk_config->cdclk = 800000;
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
else if (freq == LCPLL_CLK_FREQ_450)
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
else if (freq == LCPLL_CLK_FREQ_54O_BDW)
- cdclk_state->cdclk = 540000;
+ cdclk_config->cdclk = 540000;
else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
- cdclk_state->cdclk = 337500;
+ cdclk_config->cdclk = 337500;
else
- cdclk_state->cdclk = 675000;
+ cdclk_config->cdclk = 675000;
/*
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
*/
- cdclk_state->voltage_level =
- bdw_calc_voltage_level(cdclk_state->cdclk);
+ cdclk_config->voltage_level =
+ bdw_calc_voltage_level(cdclk_config->cdclk);
}
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- int cdclk = cdclk_state->cdclk;
+ int cdclk = cdclk_config->cdclk;
u32 val;
int ret;
@@ -778,7 +778,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
DRM_ERROR("Switching back to LCPLL failed\n");
sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_state->voltage_level);
+ cdclk_config->voltage_level);
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -821,12 +821,12 @@ static u8 skl_calc_voltage_level(int cdclk)
}
static void skl_dpll0_update(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 val;
- cdclk_state->ref = 24000;
- cdclk_state->vco = 0;
+ cdclk_config->ref = 24000;
+ cdclk_config->vco = 0;
val = I915_READ(LCPLL1_CTL);
if ((val & LCPLL_PLL_ENABLE) == 0)
@@ -848,11 +848,11 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
- cdclk_state->vco = 8100000;
+ cdclk_config->vco = 8100000;
break;
case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
- cdclk_state->vco = 8640000;
+ cdclk_config->vco = 8640000;
break;
default:
MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
@@ -861,32 +861,32 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
}
static void skl_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 cdctl;
- skl_dpll0_update(dev_priv, cdclk_state);
+ skl_dpll0_update(dev_priv, cdclk_config);
- cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
+ cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
- if (cdclk_state->vco == 0)
+ if (cdclk_config->vco == 0)
goto out;
cdctl = I915_READ(CDCLK_CTL);
- if (cdclk_state->vco == 8640000) {
+ if (cdclk_config->vco == 8640000) {
switch (cdctl & CDCLK_FREQ_SEL_MASK) {
case CDCLK_FREQ_450_432:
- cdclk_state->cdclk = 432000;
+ cdclk_config->cdclk = 432000;
break;
case CDCLK_FREQ_337_308:
- cdclk_state->cdclk = 308571;
+ cdclk_config->cdclk = 308571;
break;
case CDCLK_FREQ_540:
- cdclk_state->cdclk = 540000;
+ cdclk_config->cdclk = 540000;
break;
case CDCLK_FREQ_675_617:
- cdclk_state->cdclk = 617143;
+ cdclk_config->cdclk = 617143;
break;
default:
MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
@@ -895,16 +895,16 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
} else {
switch (cdctl & CDCLK_FREQ_SEL_MASK) {
case CDCLK_FREQ_450_432:
- cdclk_state->cdclk = 450000;
+ cdclk_config->cdclk = 450000;
break;
case CDCLK_FREQ_337_308:
- cdclk_state->cdclk = 337500;
+ cdclk_config->cdclk = 337500;
break;
case CDCLK_FREQ_540:
- cdclk_state->cdclk = 540000;
+ cdclk_config->cdclk = 540000;
break;
case CDCLK_FREQ_675_617:
- cdclk_state->cdclk = 675000;
+ cdclk_config->cdclk = 675000;
break;
default:
MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
@@ -917,8 +917,8 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
*/
- cdclk_state->voltage_level =
- skl_calc_voltage_level(cdclk_state->cdclk);
+ cdclk_config->voltage_level =
+ skl_calc_voltage_level(cdclk_config->cdclk);
}
/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
@@ -989,11 +989,11 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
}
static void skl_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- int cdclk = cdclk_state->cdclk;
- int vco = cdclk_state->vco;
+ int cdclk = cdclk_config->cdclk;
+ int vco = cdclk_config->vco;
u32 freq_select, cdclk_ctl;
int ret;
@@ -1075,7 +1075,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
/* inform PCU of the change */
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_state->voltage_level);
+ cdclk_config->voltage_level);
intel_update_cdclk(dev_priv);
}
@@ -1093,7 +1093,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk.hw.vco == 0 ||
@@ -1124,7 +1124,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
static void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_state cdclk_state;
+ struct intel_cdclk_config cdclk_config;
skl_sanitize_cdclk(dev_priv);
@@ -1140,26 +1140,26 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv)
return;
}
- cdclk_state = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->cdclk.hw;
- cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
- if (cdclk_state.vco == 0)
- cdclk_state.vco = 8100000;
- cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
- cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
+ cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
+ if (cdclk_config.vco == 0)
+ cdclk_config.vco = 8100000;
+ cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
+ cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+ skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
+ cdclk_config.cdclk = cdclk_config.bypass;
+ cdclk_config.vco = 0;
+ cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+ skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
static const struct intel_cdclk_vals bxt_cdclk_table[] = {
@@ -1284,16 +1284,16 @@ static u8 ehl_calc_voltage_level(int cdclk)
}
static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
- cdclk_state->ref = 24000;
+ cdclk_config->ref = 24000;
else
- cdclk_state->ref = 19200;
+ cdclk_config->ref = 19200;
}
static void icl_readout_refclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
@@ -1302,28 +1302,28 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv,
MISSING_CASE(dssm);
/* fall through */
case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
- cdclk_state->ref = 24000;
+ cdclk_config->ref = 24000;
break;
case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
- cdclk_state->ref = 19200;
+ cdclk_config->ref = 19200;
break;
case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
- cdclk_state->ref = 38400;
+ cdclk_config->ref = 38400;
break;
}
}
static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 val, ratio;
if (INTEL_GEN(dev_priv) >= 11)
- icl_readout_refclk(dev_priv, cdclk_state);
+ icl_readout_refclk(dev_priv, cdclk_config);
else if (IS_CANNONLAKE(dev_priv))
- cnl_readout_refclk(dev_priv, cdclk_state);
+ cnl_readout_refclk(dev_priv, cdclk_config);
else
- cdclk_state->ref = 19200;
+ cdclk_config->ref = 19200;
val = I915_READ(BXT_DE_PLL_ENABLE);
if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
@@ -1332,7 +1332,7 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
* setting it to zero is a way to signal that.
*/
- cdclk_state->vco = 0;
+ cdclk_config->vco = 0;
return;
}
@@ -1345,26 +1345,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
else
ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
- cdclk_state->vco = ratio * cdclk_state->ref;
+ cdclk_config->vco = ratio * cdclk_config->ref;
}
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+ struct intel_cdclk_config *cdclk_config)
{
u32 divider;
int div;
- bxt_de_pll_readout(dev_priv, cdclk_state);
+ bxt_de_pll_readout(dev_priv, cdclk_config);
if (INTEL_GEN(dev_priv) >= 12)
- cdclk_state->bypass = cdclk_state->ref / 2;
+ cdclk_config->bypass = cdclk_config->ref / 2;
else if (INTEL_GEN(dev_priv) >= 11)
- cdclk_state->bypass = 50000;
+ cdclk_config->bypass = 50000;
else
- cdclk_state->bypass = cdclk_state->ref;
+ cdclk_config->bypass = cdclk_config->ref;
- if (cdclk_state->vco == 0) {
- cdclk_state->cdclk = cdclk_state->bypass;
+ if (cdclk_config->vco == 0) {
+ cdclk_config->cdclk = cdclk_config->bypass;
goto out;
}
@@ -1391,15 +1391,15 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
return;
}
- cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+ cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
out:
/*
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
*/
- cdclk_state->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_state->cdclk);
+ cdclk_config->voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1488,11 +1488,11 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe
}
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- int cdclk = cdclk_state->cdclk;
- int vco = cdclk_state->vco;
+ int cdclk = cdclk_config->cdclk;
+ int vco = cdclk_config->vco;
u32 val, divider;
int ret;
@@ -1573,7 +1573,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 10) {
ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_state->voltage_level);
+ cdclk_config->voltage_level);
} else {
/*
* The timeout isn't specified, the 2ms used here is based on
@@ -1583,7 +1583,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
*/
ret = sandybridge_pcode_write_timeout(dev_priv,
HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_state->voltage_level,
+ cdclk_config->voltage_level,
150, 2);
}
@@ -1600,7 +1600,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
+ dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1609,7 +1609,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
int cdclk, vco;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
@@ -1683,7 +1683,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_state cdclk_state;
+ struct intel_cdclk_config cdclk_config;
bxt_sanitize_cdclk(dev_priv);
@@ -1691,31 +1691,31 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco != 0)
return;
- cdclk_state = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->cdclk.hw;
/*
* FIXME:
* - The initial CDCLK needs to be read from VBT.
* Need to make this change after VBT has changes for BXT.
*/
- cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
- cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
- cdclk_state.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
+ cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
+ cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
+ cdclk_config.voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
- bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+ bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- cdclk_state.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
+ cdclk_config.cdclk = cdclk_config.bypass;
+ cdclk_config.vco = 0;
+ cdclk_config.voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
- bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+ bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
/**
@@ -1751,15 +1751,17 @@ void intel_cdclk_uninit(struct drm_i915_private *i915)
}
/**
- * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
- * @a: first CDCLK state
- * @b: second CDCLK state
+ * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
+ * configurations requires a modeset on all pipes
+ * @a: first CDCLK configuration
+ * @b: second CDCLK configuration
*
* Returns:
- * True if the CDCLK states require pipes to be off during reprogramming, false if not.
+ * True if changing between the two CDCLK configurations
+ * requires all pipes to be off, false if not.
*/
-bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
{
return a->cdclk != b->cdclk ||
a->vco != b->vco ||
@@ -1767,17 +1769,19 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
}
/**
- * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need a cd2x divider update
- * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
- * @a: first CDCLK state
- * @b: second CDCLK state
+ * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
+ * configurations requires only a cd2x divider update
+ * @dev_priv: i915 device
+ * @a: first CDCLK configuration
+ * @b: second CDCLK configuration
*
* Returns:
- * True if the CDCLK states require just a cd2x divider update, false if not.
+ * True if changing between the two CDCLK configurations
+ * can be done with just a cd2x divider update, false if not.
*/
static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
{
/* Older hw doesn't have the capability */
if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
@@ -1789,15 +1793,15 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
}
/**
- * intel_cdclk_changed - Determine if two CDCLK states are different
- * @a: first CDCLK state
- * @b: second CDCLK state
+ * intel_cdclk_changed - Determine if two CDCLK configurations are different
+ * @a: first CDCLK configuration
+ * @b: second CDCLK configuration
*
* Returns:
- * True if the CDCLK states don't match, false if they do.
+ * True if the CDCLK configurations don't match, false if they do.
*/
-static bool intel_cdclk_changed(const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
{
return intel_cdclk_needs_modeset(a, b) ||
a->voltage_level != b->voltage_level;
@@ -1843,59 +1847,59 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
swap(state->cdclk.actual, dev_priv->cdclk.actual);
}
-void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
- const char *context)
+void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+ const char *context)
{
DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
- context, cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref, cdclk_state->bypass,
- cdclk_state->voltage_level);
+ context, cdclk_config->cdclk, cdclk_config->vco,
+ cdclk_config->ref, cdclk_config->bypass,
+ cdclk_config->voltage_level);
}
/**
- * intel_set_cdclk - Push the CDCLK state to the hardware
+ * intel_set_cdclk - Push the CDCLK configuration to the hardware
* @dev_priv: i915 device
- * @cdclk_state: new CDCLK state
+ * @cdclk_config: new CDCLK configuration
* @pipe: pipe with which to synchronize the update
*
* Program the hardware based on the passed in CDCLK state,
* if necessary.
*/
static void intel_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
+ if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
return;
- intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
+ intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
- dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
- if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
+ if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
- intel_dump_cdclk_state(cdclk_state, "[sw state]");
+ intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
+ intel_dump_cdclk_config(cdclk_config, "[sw state]");
}
}
/**
- * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
+ * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware
* @dev_priv: i915 device
- * @old_state: old CDCLK state
- * @new_state: new CDCLK state
+ * @old_state: old CDCLK configuration
+ * @new_state: new CDCLK configuration
* @pipe: pipe with which to synchronize the update
*
* Program the hardware before updating the HW plane state based on the passed
- * in CDCLK state, if necessary.
+ * in CDCLK configuration, if necessary.
*/
void
intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *old_state,
- const struct intel_cdclk_state *new_state,
+ const struct intel_cdclk_config *old_state,
+ const struct intel_cdclk_config *new_state,
enum pipe pipe)
{
if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
@@ -1903,19 +1907,19 @@ intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
}
/**
- * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
+ * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware
* @dev_priv: i915 device
- * @old_state: old CDCLK state
- * @new_state: new CDCLK state
+ * @old_state: old CDCLK configuration
+ * @new_state: new CDCLK configuration
* @pipe: pipe with which to synchronize the update
*
* Program the hardware after updating the HW plane state based on the passed
- * in CDCLK state, if necessary.
+ * in CDCLK configuration, if necessary.
*/
void
intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *old_state,
- const struct intel_cdclk_state *new_state,
+ const struct intel_cdclk_config *old_state,
+ const struct intel_cdclk_config *new_state,
enum pipe pipe)
{
if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 3f3773c582ae..712cdaea4fef 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -12,7 +12,7 @@
struct drm_i915_private;
struct intel_atomic_state;
-struct intel_cdclk_state;
+struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_cdclk_vals {
@@ -29,22 +29,22 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
-bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b);
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b);
void intel_cdclk_clear_state(struct intel_atomic_state *state);
void intel_cdclk_swap_state(struct intel_atomic_state *state);
void
intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *old_state,
- const struct intel_cdclk_state *new_state,
+ const struct intel_cdclk_config *old_state,
+ const struct intel_cdclk_config *new_state,
enum pipe pipe);
void
intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *old_state,
- const struct intel_cdclk_state *new_state,
+ const struct intel_cdclk_config *old_state,
+ const struct intel_cdclk_config *new_state,
enum pipe pipe);
-void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
- const char *context);
+void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+ const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
#endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f3f9fe94ed41..de2ab44b9150 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17359,7 +17359,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
intel_update_cdclk(i915);
- intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21561acfa3ac..2dc00d4b115b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1037,7 +1037,7 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_state cdclk_state = {};
+ struct intel_cdclk_config cdclk_config = {};
if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
@@ -1046,9 +1046,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
+ dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
- WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
+ WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
@@ -4659,7 +4659,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a6b95a8ab323..485b26d05e90 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -463,17 +463,17 @@ struct intel_atomic_state {
struct {
/*
- * Logical state of cdclk (used for all scaling, watermark,
- * etc. calculations and checks). This is computed as if all
- * enabled crtcs were active.
+ * Logical configuration of cdclk (used for all scaling,
+ * watermark, etc. calculations and checks). This is
+ * computed as if all enabled crtcs were active.
*/
- struct intel_cdclk_state logical;
+ struct intel_cdclk_config logical;
/*
- * Actual state of cdclk, can be different from the logical
- * state only when all crtc's are DPMS off.
+ * Actual configuration of cdclk, can be different from the
+ * logical configuration only when all crtc's are DPMS off.
*/
- struct intel_cdclk_state actual;
+ struct intel_cdclk_config actual;
int force_min_cdclk;
bool force_min_cdclk_changed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 650f42bd9cfb..49276ce2819f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,18 +255,18 @@ struct sdvo_device_mapping {
struct intel_connector;
struct intel_encoder;
struct intel_atomic_state;
+struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
-struct intel_cdclk_state;
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state);
+ struct intel_cdclk_config *cdclk_config);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state,
+ const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
@@ -880,7 +880,7 @@ struct intel_wm_config {
bool sprites_scaled;
};
-struct intel_cdclk_state {
+struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
};
@@ -1011,17 +1011,17 @@ struct drm_i915_private {
*/
struct {
/*
- * The current logical cdclk state.
+ * The current logical cdclk configuration.
* See intel_atomic_state.cdclk.logical
*/
- struct intel_cdclk_state logical;
+ struct intel_cdclk_config logical;
/*
- * The current actual cdclk state.
+ * The current actual cdclk configuration.
* See intel_atomic_state.cdclk.actual
*/
- struct intel_cdclk_state actual;
- /* The current hardware cdclk state */
- struct intel_cdclk_state hw;
+ struct intel_cdclk_config actual;
+ /* The current hardware cdclk configuration */
+ struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (6 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
` (15 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move all the old vs. new state shenanigans
into intel_set_cdclk_{pre,post}_plane_update() so that the caller
doesn't need to know any of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++----------
drivers/gpu/drm/i915/display/intel_cdclk.h | 12 +-----
drivers/gpu/drm/i915/display/intel_display.c | 10 +----
3 files changed, 26 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2a5491eb8af3..a2b1401dcfbb 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1887,41 +1887,41 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
}
/**
- * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware
- * @dev_priv: i915 device
- * @old_state: old CDCLK configuration
- * @new_state: new CDCLK configuration
- * @pipe: pipe with which to synchronize the update
+ * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
+ * @state: intel atomic state
*
- * Program the hardware before updating the HW plane state based on the passed
- * in CDCLK configuration, if necessary.
+ * Program the hardware before updating the HW plane state based on the
+ * new CDCLK state, if necessary.
*/
void
-intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *old_state,
- const struct intel_cdclk_config *new_state,
- enum pipe pipe)
+intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ /* called after intel_cdclk_swap_state()! */
+ const struct intel_cdclk_config *old_state = &state->cdclk.actual;
+ const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual;
+ enum pipe pipe = state->cdclk.pipe;
+
if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
intel_set_cdclk(dev_priv, new_state, pipe);
}
/**
- * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware
- * @dev_priv: i915 device
- * @old_state: old CDCLK configuration
- * @new_state: new CDCLK configuration
- * @pipe: pipe with which to synchronize the update
+ * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
+ * @state: intel atomic state
*
- * Program the hardware after updating the HW plane state based on the passed
- * in CDCLK configuration, if necessary.
+ * Program the hardware before updating the HW plane state based on the
+ * new CDCLK state, if necessary.
*/
void
-intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *old_state,
- const struct intel_cdclk_config *new_state,
- enum pipe pipe)
+intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ /* called after intel_cdclk_swap_state()! */
+ const struct intel_cdclk_config *old_state = &state->cdclk.actual;
+ const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual;
+ enum pipe pipe = state->cdclk.pipe;
+
if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
intel_set_cdclk(dev_priv, new_state, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 712cdaea4fef..a3fb7b8e8d31 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -33,16 +33,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
void intel_cdclk_clear_state(struct intel_atomic_state *state);
void intel_cdclk_swap_state(struct intel_atomic_state *state);
-void
-intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *old_state,
- const struct intel_cdclk_config *new_state,
- enum pipe pipe);
-void
-intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *old_state,
- const struct intel_cdclk_config *new_state,
- enum pipe pipe);
+void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
+void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de2ab44b9150..25b0eab019cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15411,10 +15411,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
- intel_set_cdclk_pre_plane_update(dev_priv,
- &state->cdclk.actual,
- &dev_priv->cdclk.actual,
- state->cdclk.pipe);
+ intel_set_cdclk_pre_plane_update(state);
/*
* SKL workaround: bspec recommends we disable the SAGV when we
@@ -15450,10 +15447,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset) {
intel_encoders_update_complete(state);
- intel_set_cdclk_post_plane_update(dev_priv,
- &state->cdclk.actual,
- &dev_priv->cdclk.actual,
- state->cdclk.pipe);
+ intel_set_cdclk_post_plane_update(state);
}
/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
--
2.24.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (7 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
` (14 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use the same structure to store the cdclk state in both
intel_atomic_state and dev_priv. First step towards proper
old vs. new cdclk states.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
drivers/gpu/drm/i915/display/intel_audio.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 168 ++++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 29 ++-
.../drm/i915/display/intel_display_types.h | 30 +---
drivers/gpu/drm/i915/i915_drv.h | 51 ++++--
6 files changed, 151 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 3e97af682b1b..563caec1d201 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -159,6 +159,8 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct intel_cdclk_state *cdclk_state =
+ &dev_priv->cdclk_state;
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
@@ -182,11 +184,11 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
* safe as long we hold at least one crtc mutex (which
* must be true since we have crtc_state).
*/
- if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) {
+ if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
plane->base.base.id, plane->base.name,
crtc_state->min_cdclk[plane->id],
- dev_priv->cdclk.logical.cdclk);
+ cdclk_state->logical.cdclk);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index b18040793d9e..32e722128638 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -815,8 +815,8 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
state->acquire_ctx = &ctx;
retry:
- to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
- to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
+ to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
enable ? 2 * 96000 : 0;
/* Protects dev_priv->cdclk.force_min_cdclk */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a2b1401dcfbb..f8e70a668b74 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1815,8 +1815,8 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
*/
void intel_cdclk_clear_state(struct intel_atomic_state *state)
{
- memset(&state->cdclk, 0, sizeof(state->cdclk));
- state->cdclk.pipe = INVALID_PIPE;
+ memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
+ state->cdclk_state.pipe = INVALID_PIPE;
}
/**
@@ -1836,15 +1836,18 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
/* FIXME maybe swap() these too */
- memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk,
- sizeof(state->cdclk.min_cdclk));
- memcpy(dev_priv->cdclk.min_voltage_level, state->cdclk.min_voltage_level,
- sizeof(state->cdclk.min_voltage_level));
+ memcpy(dev_priv->cdclk_state.min_cdclk,
+ state->cdclk_state.min_cdclk,
+ sizeof(state->cdclk_state.min_cdclk));
+ memcpy(dev_priv->cdclk_state.min_voltage_level,
+ state->cdclk_state.min_voltage_level,
+ sizeof(state->cdclk_state.min_voltage_level));
- dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
+ dev_priv->cdclk_state.force_min_cdclk =
+ state->cdclk_state.force_min_cdclk;
- swap(state->cdclk.logical, dev_priv->cdclk.logical);
- swap(state->cdclk.actual, dev_priv->cdclk.actual);
+ swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical);
+ swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual);
}
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
@@ -1898,12 +1901,13 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
/* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_config *old_state = &state->cdclk.actual;
- const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual;
- enum pipe pipe = state->cdclk.pipe;
+ const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
+ const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
- if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
- intel_set_cdclk(dev_priv, new_state, pipe);
+ if (pipe == INVALID_PIPE ||
+ old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
+ intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
}
/**
@@ -1918,12 +1922,13 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
/* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_config *old_state = &state->cdclk.actual;
- const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual;
- enum pipe pipe = state->cdclk.pipe;
+ const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
+ const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
- if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
- intel_set_cdclk(dev_priv, new_state, pipe);
+ if (pipe != INVALID_PIPE &&
+ old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
+ intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
}
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
@@ -2052,6 +2057,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_compute_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
@@ -2064,19 +2070,19 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
if (min_cdclk < 0)
return min_cdclk;
- if (state->cdclk.min_cdclk[i] == min_cdclk)
+ if (cdclk_state->min_cdclk[i] == min_cdclk)
continue;
- state->cdclk.min_cdclk[i] = min_cdclk;
+ cdclk_state->min_cdclk[i] = min_cdclk;
ret = intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
- min_cdclk = state->cdclk.force_min_cdclk;
+ min_cdclk = cdclk_state->force_min_cdclk;
for_each_pipe(dev_priv, pipe)
- min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk);
+ min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
return min_cdclk;
}
@@ -2097,6 +2103,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
u8 min_voltage_level;
@@ -2111,10 +2118,10 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
else
min_voltage_level = 0;
- if (state->cdclk.min_voltage_level[i] == min_voltage_level)
+ if (cdclk_state->min_voltage_level[i] == min_voltage_level)
continue;
- state->cdclk.min_voltage_level[i] = min_voltage_level;
+ cdclk_state->min_voltage_level[i] = min_voltage_level;
ret = intel_atomic_lock_global_state(state);
if (ret)
@@ -2123,7 +2130,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
min_voltage_level = 0;
for_each_pipe(dev_priv, pipe)
- min_voltage_level = max(state->cdclk.min_voltage_level[pipe],
+ min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
min_voltage_level);
return min_voltage_level;
@@ -2132,6 +2139,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, cdclk;
min_cdclk = intel_compute_min_cdclk(state);
@@ -2140,18 +2148,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
+ cdclk_state->logical.cdclk = cdclk;
+ cdclk_state->logical.voltage_level =
vlv_calc_voltage_level(dev_priv, cdclk);
if (!state->active_pipes) {
- cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+ cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
+ cdclk_state->actual.cdclk = cdclk;
+ cdclk_state->actual.voltage_level =
vlv_calc_voltage_level(dev_priv, cdclk);
} else {
- state->cdclk.actual = state->cdclk.logical;
+ cdclk_state->actual = cdclk_state->logical;
}
return 0;
@@ -2159,6 +2167,7 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
{
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, cdclk;
min_cdclk = intel_compute_min_cdclk(state);
@@ -2171,18 +2180,18 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
*/
cdclk = bdw_calc_cdclk(min_cdclk);
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
+ cdclk_state->logical.cdclk = cdclk;
+ cdclk_state->logical.voltage_level =
bdw_calc_voltage_level(cdclk);
if (!state->active_pipes) {
- cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
+ cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
+ cdclk_state->actual.cdclk = cdclk;
+ cdclk_state->actual.voltage_level =
bdw_calc_voltage_level(cdclk);
} else {
- state->cdclk.actual = state->cdclk.logical;
+ cdclk_state->actual = cdclk_state->logical;
}
return 0;
@@ -2191,11 +2200,12 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
static int skl_dpll0_vco(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int vco, i;
- vco = state->cdclk.logical.vco;
+ vco = cdclk_state->logical.vco;
if (!vco)
vco = dev_priv->skl_preferred_vco_freq;
@@ -2226,6 +2236,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
{
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, cdclk, vco;
min_cdclk = intel_compute_min_cdclk(state);
@@ -2240,20 +2251,20 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
*/
cdclk = skl_calc_cdclk(min_cdclk, vco);
- state->cdclk.logical.vco = vco;
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
+ cdclk_state->logical.vco = vco;
+ cdclk_state->logical.cdclk = cdclk;
+ cdclk_state->logical.voltage_level =
skl_calc_voltage_level(cdclk);
if (!state->active_pipes) {
- cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco);
+ cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
- state->cdclk.actual.vco = vco;
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
+ cdclk_state->actual.vco = vco;
+ cdclk_state->actual.cdclk = cdclk;
+ cdclk_state->actual.voltage_level =
skl_calc_voltage_level(cdclk);
} else {
- state->cdclk.actual = state->cdclk.logical;
+ cdclk_state->actual = cdclk_state->logical;
}
return 0;
@@ -2262,6 +2273,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, min_voltage_level, cdclk, vco;
min_cdclk = intel_compute_min_cdclk(state);
@@ -2275,22 +2287,22 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- state->cdclk.logical.vco = vco;
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
+ cdclk_state->logical.vco = vco;
+ cdclk_state->logical.cdclk = cdclk;
+ cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
dev_priv->display.calc_voltage_level(cdclk));
if (!state->active_pipes) {
- cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+ cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- state->cdclk.actual.vco = vco;
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
+ cdclk_state->actual.vco = vco;
+ cdclk_state->actual.cdclk = cdclk;
+ cdclk_state->actual.voltage_level =
dev_priv->display.calc_voltage_level(cdclk);
} else {
- state->cdclk.actual = state->cdclk.logical;
+ cdclk_state->actual = cdclk_state->logical;
}
return 0;
@@ -2354,20 +2366,22 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
+ struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
enum pipe pipe;
int ret;
- memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk,
- sizeof(state->cdclk.min_cdclk));
- memcpy(state->cdclk.min_voltage_level, dev_priv->cdclk.min_voltage_level,
- sizeof(state->cdclk.min_voltage_level));
+ memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
+ sizeof(new_cdclk_state->min_cdclk));
+ memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
+ sizeof(new_cdclk_state->min_voltage_level));
/* keep the current setting */
- if (!state->cdclk.force_min_cdclk_changed)
- state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+ if (!new_cdclk_state->force_min_cdclk_changed)
+ new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
- state->cdclk.logical = dev_priv->cdclk.logical;
- state->cdclk.actual = dev_priv->cdclk.actual;
+ new_cdclk_state->logical = old_cdclk_state->logical;
+ new_cdclk_state->actual = old_cdclk_state->actual;
ret = dev_priv->display.modeset_calc_cdclk(state);
if (ret)
@@ -2378,8 +2392,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
* by holding all the crtc mutexes even if we don't end up
* touching the hardware
*/
- if (intel_cdclk_changed(&dev_priv->cdclk.actual,
- &state->cdclk.actual)) {
+ if (intel_cdclk_changed(&old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
/*
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
@@ -2387,8 +2401,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
ret = intel_atomic_serialize_global_state(state);
if (ret)
return ret;
- } else if (intel_cdclk_changed(&dev_priv->cdclk.logical,
- &state->cdclk.logical)) {
+ } else if (intel_cdclk_changed(&old_cdclk_state->logical,
+ &new_cdclk_state->logical)) {
ret = intel_atomic_lock_global_state(state);
if (ret)
return ret;
@@ -2398,8 +2412,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (is_power_of_2(state->active_pipes) &&
intel_cdclk_can_cd2x_update(dev_priv,
- &dev_priv->cdclk.actual,
- &state->cdclk.actual)) {
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
@@ -2417,28 +2431,28 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
}
if (pipe != INVALID_PIPE) {
- state->cdclk.pipe = pipe;
+ new_cdclk_state->pipe = pipe;
DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
pipe_name(pipe));
- } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
- &state->cdclk.actual)) {
+ } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
/* All pipes must be switched off while we change the cdclk. */
ret = intel_modeset_all_pipes(state);
if (ret)
return ret;
- state->cdclk.pipe = INVALID_PIPE;
+ new_cdclk_state->pipe = INVALID_PIPE;
DRM_DEBUG_KMS("Modeset required for cdclk change\n");
}
DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
- state->cdclk.logical.cdclk,
- state->cdclk.actual.cdclk);
+ new_cdclk_state->logical.cdclk,
+ new_cdclk_state->actual.cdclk);
DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
- state->cdclk.logical.voltage_level,
- state->cdclk.actual.voltage_level);
+ new_cdclk_state->logical.voltage_level,
+ new_cdclk_state->actual.voltage_level);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25b0eab019cb..63efb8f9c669 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7481,6 +7481,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
+ struct intel_cdclk_state *cdclk_state =
+ &dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum intel_display_power_domain domain;
@@ -7547,8 +7549,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
crtc->enabled_power_domains = 0;
dev_priv->active_pipes &= ~BIT(pipe);
- dev_priv->cdclk.min_cdclk[pipe] = 0;
- dev_priv->cdclk.min_voltage_level[pipe] = 0;
+ cdclk_state->min_cdclk[pipe] = 0;
+ cdclk_state->min_voltage_level[pipe] = 0;
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
@@ -7784,6 +7786,8 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
to_i915(crtc_state->uapi.crtc->dev);
struct intel_atomic_state *intel_state =
to_intel_atomic_state(crtc_state->uapi.state);
+ const struct intel_cdclk_state *cdclk_state =
+ &intel_state->cdclk_state;
if (!hsw_crtc_state_ips_capable(crtc_state))
return false;
@@ -7803,7 +7807,7 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
if (IS_BROADWELL(dev_priv) &&
- crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
+ crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
return false;
return true;
@@ -12545,12 +12549,14 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
+ const struct intel_cdclk_state *cdclk_state =
+ &state->cdclk_state;
if (!crtc_state->hw.enable)
return 0;
return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- state->cdclk.logical.cdclk);
+ cdclk_state->logical.cdclk);
}
static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
@@ -14754,7 +14760,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- any_ms |= state->cdclk.force_min_cdclk_changed;
+ any_ms |= state->cdclk_state.force_min_cdclk_changed;
ret = intel_atomic_check_planes(state, &any_ms);
if (ret)
@@ -14765,7 +14771,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
} else {
- state->cdclk.logical = dev_priv->cdclk.logical;
+ state->cdclk_state.logical = dev_priv->cdclk_state.logical;
}
ret = intel_atomic_check_crtcs(state);
@@ -17352,9 +17358,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
+ struct intel_cdclk_state *cdclk_state =
+ &i915->cdclk_state;
+
intel_update_cdclk(i915);
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
- i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
+ cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
}
/*
@@ -18177,6 +18186,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
+ struct intel_cdclk_state *cdclk_state =
+ &dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -18245,8 +18256,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
min_cdclk = 0;
}
- dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk;
- dev_priv->cdclk.min_voltage_level[crtc->pipe] =
+ cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
+ cdclk_state->min_voltage_level[crtc->pipe] =
crtc_state->min_voltage_level;
intel_bw_crtc_update(bw_state, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 485b26d05e90..b31ed828fa8f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -461,31 +461,7 @@ struct intel_atomic_state {
intel_wakeref_t wakeref;
- struct {
- /*
- * Logical configuration of cdclk (used for all scaling,
- * watermark, etc. calculations and checks). This is
- * computed as if all enabled crtcs were active.
- */
- struct intel_cdclk_config logical;
-
- /*
- * Actual configuration of cdclk, can be different from the
- * logical configuration only when all crtc's are DPMS off.
- */
- struct intel_cdclk_config actual;
-
- int force_min_cdclk;
- bool force_min_cdclk_changed;
-
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
-
- /* pipe to which cd2x update is synchronized */
- enum pipe pipe;
- } cdclk;
+ struct intel_cdclk_state cdclk_state;
bool dpll_set, modeset;
@@ -513,9 +489,7 @@ struct intel_atomic_state {
/*
* active_pipes
- * min_cdclk[]
- * min_voltage_level[]
- * cdclk.*
+ * cdclk_state
*/
bool global_state_changed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49276ce2819f..1787bfdd057f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -65,6 +65,7 @@
#include "i915_utils.h"
#include "display/intel_bios.h"
+#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
@@ -889,6 +890,33 @@ struct i915_selftest_stash {
atomic_t counter;
};
+struct intel_cdclk_state {
+ /*
+ * Logical configuration of cdclk (used for all scaling,
+ * watermark, etc. calculations and checks). This is
+ * computed as if all enabled crtcs were active.
+ */
+ struct intel_cdclk_config logical;
+
+ /*
+ * Actual configuration of cdclk, can be different from the
+ * logical configuration only when all crtc's are DPMS off.
+ */
+ struct intel_cdclk_config actual;
+
+ /* minimum acceptable cdclk for each pipe */
+ int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
+
+ /* pipe to which cd2x update is synchronized */
+ enum pipe pipe;
+
+ /* forced minimum cdclk for glk+ audio w/a */
+ int force_min_cdclk;
+ bool force_min_cdclk_changed;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -1009,29 +1037,14 @@ struct drm_i915_private {
* For reading holding any crtc lock is sufficient,
* for writing must hold all of them.
*/
+ struct intel_cdclk_state cdclk_state;
+
struct {
- /*
- * The current logical cdclk configuration.
- * See intel_atomic_state.cdclk.logical
- */
- struct intel_cdclk_config logical;
- /*
- * The current actual cdclk configuration.
- * See intel_atomic_state.cdclk.actual
- */
- struct intel_cdclk_config actual;
/* The current hardware cdclk configuration */
struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
-
- int force_min_cdclk;
-
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
} cdclk;
/**
@@ -1088,8 +1101,8 @@ struct drm_i915_private {
struct mutex dpll_lock;
/*
- * For reading active_pipes, min_cdclk, min_voltage_level holding
- * any crtc lock is sufficient, for writing must hold all of them.
+ * For reading active_pipes, cdclk_state holding any crtc
+ * lock is sufficient, for writing must hold all of them.
*/
u8 active_pipes;
--
2.24.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (8 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-24 15:06 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
` (13 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To make life less confusing let's swap() the entire cdclk state
rather than swapping some parts, copying other parts, and leaving
the rest just as is.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---------------
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f8e70a668b74..002044e80868 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1835,19 +1835,7 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- /* FIXME maybe swap() these too */
- memcpy(dev_priv->cdclk_state.min_cdclk,
- state->cdclk_state.min_cdclk,
- sizeof(state->cdclk_state.min_cdclk));
- memcpy(dev_priv->cdclk_state.min_voltage_level,
- state->cdclk_state.min_voltage_level,
- sizeof(state->cdclk_state.min_voltage_level));
-
- dev_priv->cdclk_state.force_min_cdclk =
- state->cdclk_state.force_min_cdclk;
-
- swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical);
- swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual);
+ swap(state->cdclk_state, dev_priv->cdclk_state);
}
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
@@ -1903,7 +1891,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
/* called after intel_cdclk_swap_state()! */
const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
- enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
+ enum pipe pipe = new_cdclk_state->pipe;
if (pipe == INVALID_PIPE ||
old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
@@ -1924,7 +1912,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
/* called after intel_cdclk_swap_state()! */
const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
- enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
+ enum pipe pipe = new_cdclk_state->pipe;
if (pipe != INVALID_PIPE &&
old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
--
2.24.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (9 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-24 15:08 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
` (12 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give the cdclk init/uninit functions a _hw suffix to make
it clear they are about initializing the actual hardware.
I'll be wanting to to add a intel_cdclk_init() which is
purely initializing software structures.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++----------
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++--
.../drm/i915/display/intel_display_power.c | 16 ++++++-------
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 002044e80868..701a63c3ca38 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco = -1;
}
-static void skl_init_cdclk(struct drm_i915_private *dev_priv)
+static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config;
@@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv)
skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
-static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
+static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
@@ -1681,7 +1681,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco = -1;
}
-static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config;
@@ -1706,7 +1706,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
-static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
@@ -1719,7 +1719,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
}
/**
- * intel_cdclk_init - Initialize CDCLK
+ * intel_cdclk_init_hw - Initialize CDCLK hardware
* @i915: i915 device
*
* Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
@@ -1727,27 +1727,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
*/
-void intel_cdclk_init(struct drm_i915_private *i915)
+void intel_cdclk_init_hw(struct drm_i915_private *i915)
{
if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
- bxt_init_cdclk(i915);
+ bxt_cdclk_init_hw(i915);
else if (IS_GEN9_BC(i915))
- skl_init_cdclk(i915);
+ skl_cdclk_init_hw(i915);
}
/**
- * intel_cdclk_uninit - Uninitialize CDCLK
+ * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
* @i915: i915 device
*
* Uninitialize CDCLK. This is done only during the display core
* uninitialization sequence.
*/
-void intel_cdclk_uninit(struct drm_i915_private *i915)
+void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
{
if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
- bxt_uninit_cdclk(i915);
+ bxt_cdclk_uninit_hw(i915);
else if (IS_GEN9_BC(i915))
- skl_uninit_cdclk(i915);
+ skl_cdclk_uninit_hw(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index a3fb7b8e8d31..4b965db07720 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -23,8 +23,8 @@ struct intel_cdclk_vals {
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-void intel_cdclk_init(struct drm_i915_private *i915);
-void intel_cdclk_uninit(struct drm_i915_private *i915);
+void intel_cdclk_init_hw(struct drm_i915_private *i915);
+void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2dc00d4b115b..3412c56bea6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4763,7 +4763,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
- intel_cdclk_init(dev_priv);
+ intel_cdclk_init_hw(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -4780,7 +4780,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
- intel_cdclk_uninit(dev_priv);
+ intel_cdclk_uninit_hw(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -4824,7 +4824,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
mutex_unlock(&power_domains->lock);
- intel_cdclk_init(dev_priv);
+ intel_cdclk_init_hw(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -4841,7 +4841,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
- intel_cdclk_uninit(dev_priv);
+ intel_cdclk_uninit_hw(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
@@ -4883,7 +4883,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
mutex_unlock(&power_domains->lock);
/* 5. Enable CD clock */
- intel_cdclk_init(dev_priv);
+ intel_cdclk_init_hw(dev_priv);
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
@@ -4905,7 +4905,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- intel_cdclk_uninit(dev_priv);
+ intel_cdclk_uninit_hw(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
@@ -4997,7 +4997,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
/* 4. Enable CDCLK. */
- intel_cdclk_init(dev_priv);
+ intel_cdclk_init_hw(dev_priv);
/* 5. Enable DBUF. */
icl_dbuf_enable(dev_priv);
@@ -5026,7 +5026,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
icl_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- intel_cdclk_uninit(dev_priv);
+ intel_cdclk_uninit_hw(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
--
2.24.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (10 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-24 15:19 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
` (11 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_atomic_state_free() next to its counterpart.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 11 +++++++++++
drivers/gpu/drm/i915/display/intel_atomic.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 11 -----------
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 1269f63ea006..1c13423d4945 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -495,6 +495,17 @@ intel_atomic_state_alloc(struct drm_device *dev)
return &state->base;
}
+void intel_atomic_state_free(struct drm_atomic_state *_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(_state);
+
+ drm_atomic_state_default_release(&state->base);
+
+ i915_sw_fence_fini(&state->commit_ready);
+
+ kfree(state);
+}
+
void intel_atomic_state_clear(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 74c749dbfb4f..88133eea0a17 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -45,6 +45,7 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
+void intel_atomic_state_free(struct drm_atomic_state *state);
void intel_atomic_state_clear(struct drm_atomic_state *state);
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 63efb8f9c669..3b725764bdcd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17116,17 +17116,6 @@ intel_user_framebuffer_create(struct drm_device *dev,
return fb;
}
-static void intel_atomic_state_free(struct drm_atomic_state *state)
-{
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-
- drm_atomic_state_default_release(state);
-
- i915_sw_fence_fini(&intel_state->commit_ready);
-
- kfree(state);
-}
-
static enum drm_mode_status
intel_mode_valid(struct drm_device *dev,
const struct drm_display_mode *mode)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (11 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-28 14:44 ` Lisovskiy, Stanislav
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
` (10 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Our current global state handling is pretty ad-hoc. Let's try to
make it better by imitating the standard drm core private object
approach.
The reason why we don't want to directly use the private objects
is locking; Each private object has its own lock so if we
introduce any global private objects we get serialized by that
single lock across all pipes. The global state apporoach instead
uses a read/write lock type of approach where each individual
crtc lock counts as a read lock, and grabbing all the crtc locks
allows one write access.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 15 +-
.../drm/i915/display/intel_display_types.h | 4 +
.../gpu/drm/i915/display/intel_global_state.c | 223 ++++++++++++++++++
.../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
drivers/gpu/drm/i915/i915_drv.h | 3 +
10 files changed, 342 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c88d7d8c764..787ffe669810 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -190,6 +190,7 @@ i915-y += \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
+ display/intel_global_state.o \
display/intel_hdcp.o \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 1c13423d4945..45842ebcdebd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -37,6 +37,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -500,6 +501,7 @@ void intel_atomic_state_free(struct drm_atomic_state *_state)
struct intel_atomic_state *state = to_intel_atomic_state(_state);
drm_atomic_state_default_release(&state->base);
+ kfree(state->global_objs);
i915_sw_fence_fini(&state->commit_ready);
@@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
struct intel_atomic_state *state = to_intel_atomic_state(s);
drm_atomic_state_default_clear(&state->base);
+ intel_atomic_clear_global_state(state);
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
@@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
-int intel_atomic_lock_global_state(struct intel_atomic_state *state)
+int _intel_atomic_lock_global_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct intel_atomic_state *state)
return 0;
}
-int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
+int _intel_atomic_serialize_global_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 88133eea0a17..11146292b06f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
-int intel_atomic_lock_global_state(struct intel_atomic_state *state);
+int _intel_atomic_lock_global_state(struct intel_atomic_state *state);
-int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+int _intel_atomic_serialize_global_state(struct intel_atomic_state *state);
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 32e722128638..12626fd94d29 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -820,7 +820,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
enable ? 2 * 96000 : 0;
/* Protects dev_priv->cdclk.force_min_cdclk */
- ret = intel_atomic_lock_global_state(to_intel_atomic_state(state));
+ ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
if (!ret)
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 701a63c3ca38..3b7932ae2a77 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2063,7 +2063,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
cdclk_state->min_cdclk[i] = min_cdclk;
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -2111,7 +2111,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
cdclk_state->min_voltage_level[i] = min_voltage_level;
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -2386,12 +2386,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
*/
- ret = intel_atomic_serialize_global_state(state);
+ ret = _intel_atomic_serialize_global_state(state);
if (ret)
return ret;
} else if (intel_cdclk_changed(&old_cdclk_state->logical,
&new_cdclk_state->logical)) {
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3b725764bdcd..70eb6eaab095 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14381,7 +14381,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
}
if (state->active_pipe_changes) {
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -15652,6 +15652,8 @@ static int intel_atomic_commit(struct drm_device *dev,
ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
if (!ret)
ret = drm_atomic_helper_swap_state(&state->base, true);
+ if (!ret)
+ intel_atomic_swap_global_state(state);
if (ret) {
i915_sw_fence_commit(&state->commit_ready);
@@ -17518,6 +17520,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
struct drm_mode_config *mode_config = &i915->drm.mode_config;
drm_mode_config_init(&i915->drm);
+ INIT_LIST_HEAD(&i915->global_obj_list);
mode_config->min_width = 0;
mode_config->min_height = 0;
@@ -17559,6 +17562,12 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
}
}
+static void intel_mode_config_cleanup(struct drm_i915_private *i915)
+{
+ intel_atomic_global_obj_cleanup(i915);
+ drm_mode_config_cleanup(&i915->drm);
+}
+
int intel_modeset_init(struct drm_i915_private *i915)
{
struct drm_device *dev = &i915->drm;
@@ -17598,7 +17607,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
for_each_pipe(i915, pipe) {
ret = intel_crtc_init(i915, pipe);
if (ret) {
- drm_mode_config_cleanup(dev);
+ intel_mode_config_cleanup(i915);
return ret;
}
}
@@ -18551,7 +18560,7 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
intel_hdcp_component_fini(i915);
- drm_mode_config_cleanup(&i915->drm);
+ intel_mode_config_cleanup(i915);
intel_overlay_cleanup(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b31ed828fa8f..628c4a56a9e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -46,6 +46,7 @@
#include "i915_drv.h"
struct drm_printer;
+struct __intel_global_objs_state;
/*
* Display related stuff
@@ -461,6 +462,9 @@ struct intel_atomic_state {
intel_wakeref_t wakeref;
+ struct __intel_global_objs_state *global_objs;
+ int num_global_objs;
+
struct intel_cdclk_state cdclk_state;
bool dpll_set, modeset;
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c
new file mode 100644
index 000000000000..162fae080c04
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_state.c
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include <linux/string.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_display_types.h"
+#include "intel_global_state.h"
+
+void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
+ struct intel_global_obj *obj,
+ struct intel_global_state *state,
+ const struct intel_global_state_funcs *funcs)
+{
+ memset(obj, 0, sizeof(*obj));
+
+ obj->state = state;
+ obj->funcs = funcs;
+ list_add_tail(&obj->head, &dev_priv->global_obj_list);
+}
+
+void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv)
+{
+ struct intel_global_obj *obj, *next;
+
+ list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) {
+ list_del(&obj->head);
+ obj->funcs->atomic_destroy_state(obj, obj->state);
+ }
+}
+
+static void assert_global_state_write_locked(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc)
+ drm_modeset_lock_assert_held(&crtc->base.mutex);
+}
+
+static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx,
+ struct drm_modeset_lock *lock)
+{
+ struct drm_modeset_lock *l;
+
+ list_for_each_entry(l, &ctx->locked, head) {
+ if (lock == l)
+ return true;
+ }
+
+ return false;
+}
+
+static void assert_global_state_read_locked(struct intel_atomic_state *state)
+{
+ struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ if (modeset_lock_is_held(ctx, &crtc->base.mutex))
+ return;
+ }
+
+ WARN(1, "Global state not read locked\n");
+}
+
+struct intel_global_state *
+intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int index, num_objs, i;
+ size_t size;
+ struct __intel_global_objs_state *arr;
+ struct intel_global_state *obj_state;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].state;
+
+ assert_global_state_read_locked(state);
+
+ num_objs = state->num_global_objs + 1;
+ size = sizeof(*state->global_objs) * num_objs;
+ arr = krealloc(state->global_objs, size, GFP_KERNEL);
+ if (!arr)
+ return ERR_PTR(-ENOMEM);
+
+ state->global_objs = arr;
+ index = state->num_global_objs;
+ memset(&state->global_objs[index], 0, sizeof(*state->global_objs));
+
+ obj_state = obj->funcs->atomic_duplicate_state(obj);
+ if (!obj_state)
+ return ERR_PTR(-ENOMEM);
+
+ obj_state->changed = false;
+
+ state->global_objs[index].state = obj_state;
+ state->global_objs[index].old_state = obj->state;
+ state->global_objs[index].new_state = obj_state;
+ state->global_objs[index].ptr = obj;
+ obj_state->state = state;
+
+ state->num_global_objs = num_objs;
+
+ DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
+ obj, obj_state, state);
+
+ return obj_state;
+}
+
+struct intel_global_state *
+intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].old_state;
+
+ return NULL;
+}
+
+struct intel_global_state *
+intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].new_state;
+
+ return NULL;
+}
+
+void intel_atomic_swap_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *old_obj_state, *new_obj_state;
+ struct intel_global_obj *obj;
+ int i;
+
+ for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
+ new_obj_state, i) {
+ WARN_ON(obj->state != old_obj_state);
+
+ /*
+ * If the new state wasn't modified (and properly
+ * locked for write access) we throw it away.
+ */
+ if (!new_obj_state->changed)
+ continue;
+
+ assert_global_state_write_locked(dev_priv);
+
+ old_obj_state->state = state;
+ new_obj_state->state = NULL;
+
+ state->global_objs[i].state = old_obj_state;
+ obj->state = new_obj_state;
+ }
+}
+
+void intel_atomic_clear_global_state(struct intel_atomic_state *state)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++) {
+ struct intel_global_obj *obj = state->global_objs[i].ptr;
+
+ obj->funcs->atomic_destroy_state(obj,
+ state->global_objs[i].state);
+ state->global_objs[i].ptr = NULL;
+ state->global_objs[i].state = NULL;
+ state->global_objs[i].old_state = NULL;
+ state->global_objs[i].new_state = NULL;
+ }
+ state->num_global_objs = 0;
+}
+
+int intel_atomic_lock_global_state(struct intel_global_state *obj_state)
+{
+ struct intel_atomic_state *state = obj_state->state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ int ret;
+
+ ret = drm_modeset_lock(&crtc->base.mutex,
+ state->base.acquire_ctx);
+ if (ret)
+ return ret;
+ }
+
+ obj_state->changed = true;
+
+ return 0;
+}
+
+int intel_atomic_serialize_global_state(struct intel_global_state *obj_state)
+{
+ struct intel_atomic_state *state = obj_state->state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ obj_state->changed = true;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
new file mode 100644
index 000000000000..e6163a469029
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_state.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_GLOBAL_STATE_H__
+#define __INTEL_GLOBAL_STATE_H__
+
+#include <linux/list.h>
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_global_obj;
+struct intel_global_state;
+
+struct intel_global_state_funcs {
+ struct intel_global_state *(*atomic_duplicate_state)(struct intel_global_obj *obj);
+ void (*atomic_destroy_state)(struct intel_global_obj *obj,
+ struct intel_global_state *state);
+};
+
+struct intel_global_obj {
+ struct list_head head;
+ struct intel_global_state *state;
+ const struct intel_global_state_funcs *funcs;
+};
+
+#define intel_for_each_global_obj(obj, dev_priv) \
+ list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
+
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+struct intel_global_state {
+ struct intel_atomic_state *state;
+ bool changed;
+};
+
+struct __intel_global_objs_state {
+ struct intel_global_obj *ptr;
+ struct intel_global_state *state, *old_state, *new_state;
+};
+
+void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
+ struct intel_global_obj *obj,
+ struct intel_global_state *state,
+ const struct intel_global_state_funcs *funcs);
+void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv);
+
+struct intel_global_state *
+intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+struct intel_global_state *
+intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+struct intel_global_state *
+intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+
+void intel_atomic_swap_global_state(struct intel_atomic_state *state);
+void intel_atomic_clear_global_state(struct intel_atomic_state *state);
+int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
+int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1787bfdd057f..b558e68b4dbd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -71,6 +71,7 @@
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
+#include "display/intel_global_state.h"
#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
@@ -1100,6 +1101,8 @@ struct drm_i915_private {
*/
struct mutex dpll_lock;
+ struct list_head global_obj_list;
+
/*
* For reading active_pipes, cdclk_state holding any crtc
* lock is sufficient, for writing must hold all of them.
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 13/17] drm/i915: Introduce better global state handling
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (12 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-22 19:00 ` Souza, Jose
2020-01-27 15:02 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
` (9 subsequent siblings)
23 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Our current global state handling is pretty ad-hoc. Let's try to
make it better by imitating the standard drm core private object
approach.
The reason why we don't want to directly use the private objects
is locking; Each private object has its own lock so if we
introduce any global private objects we get serialized by that
single lock across all pipes. The global state apporoach instead
uses a read/write lock type of approach where each individual
crtc lock counts as a read lock, and grabbing all the crtc locks
allows one write access.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 15 +-
.../drm/i915/display/intel_display_types.h | 4 +
.../gpu/drm/i915/display/intel_global_state.c | 223 ++++++++++++++++++
.../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
drivers/gpu/drm/i915/i915_drv.h | 3 +
10 files changed, 342 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c88d7d8c764..787ffe669810 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -190,6 +190,7 @@ i915-y += \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
+ display/intel_global_state.o \
display/intel_hdcp.o \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 1c13423d4945..45842ebcdebd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -37,6 +37,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -500,6 +501,7 @@ void intel_atomic_state_free(struct drm_atomic_state *_state)
struct intel_atomic_state *state = to_intel_atomic_state(_state);
drm_atomic_state_default_release(&state->base);
+ kfree(state->global_objs);
i915_sw_fence_fini(&state->commit_ready);
@@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
struct intel_atomic_state *state = to_intel_atomic_state(s);
drm_atomic_state_default_clear(&state->base);
+ intel_atomic_clear_global_state(state);
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
@@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
-int intel_atomic_lock_global_state(struct intel_atomic_state *state)
+int _intel_atomic_lock_global_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct intel_atomic_state *state)
return 0;
}
-int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
+int _intel_atomic_serialize_global_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 88133eea0a17..11146292b06f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
-int intel_atomic_lock_global_state(struct intel_atomic_state *state);
+int _intel_atomic_lock_global_state(struct intel_atomic_state *state);
-int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+int _intel_atomic_serialize_global_state(struct intel_atomic_state *state);
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 32e722128638..12626fd94d29 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -820,7 +820,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
enable ? 2 * 96000 : 0;
/* Protects dev_priv->cdclk.force_min_cdclk */
- ret = intel_atomic_lock_global_state(to_intel_atomic_state(state));
+ ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
if (!ret)
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 701a63c3ca38..3b7932ae2a77 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2063,7 +2063,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
cdclk_state->min_cdclk[i] = min_cdclk;
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -2111,7 +2111,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
cdclk_state->min_voltage_level[i] = min_voltage_level;
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -2386,12 +2386,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
*/
- ret = intel_atomic_serialize_global_state(state);
+ ret = _intel_atomic_serialize_global_state(state);
if (ret)
return ret;
} else if (intel_cdclk_changed(&old_cdclk_state->logical,
&new_cdclk_state->logical)) {
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3b725764bdcd..70eb6eaab095 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14381,7 +14381,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
}
if (state->active_pipe_changes) {
- ret = intel_atomic_lock_global_state(state);
+ ret = _intel_atomic_lock_global_state(state);
if (ret)
return ret;
}
@@ -15652,6 +15652,8 @@ static int intel_atomic_commit(struct drm_device *dev,
ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
if (!ret)
ret = drm_atomic_helper_swap_state(&state->base, true);
+ if (!ret)
+ intel_atomic_swap_global_state(state);
if (ret) {
i915_sw_fence_commit(&state->commit_ready);
@@ -17518,6 +17520,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
struct drm_mode_config *mode_config = &i915->drm.mode_config;
drm_mode_config_init(&i915->drm);
+ INIT_LIST_HEAD(&i915->global_obj_list);
mode_config->min_width = 0;
mode_config->min_height = 0;
@@ -17559,6 +17562,12 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
}
}
+static void intel_mode_config_cleanup(struct drm_i915_private *i915)
+{
+ intel_atomic_global_obj_cleanup(i915);
+ drm_mode_config_cleanup(&i915->drm);
+}
+
int intel_modeset_init(struct drm_i915_private *i915)
{
struct drm_device *dev = &i915->drm;
@@ -17598,7 +17607,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
for_each_pipe(i915, pipe) {
ret = intel_crtc_init(i915, pipe);
if (ret) {
- drm_mode_config_cleanup(dev);
+ intel_mode_config_cleanup(i915);
return ret;
}
}
@@ -18551,7 +18560,7 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
intel_hdcp_component_fini(i915);
- drm_mode_config_cleanup(&i915->drm);
+ intel_mode_config_cleanup(i915);
intel_overlay_cleanup(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b31ed828fa8f..628c4a56a9e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -46,6 +46,7 @@
#include "i915_drv.h"
struct drm_printer;
+struct __intel_global_objs_state;
/*
* Display related stuff
@@ -461,6 +462,9 @@ struct intel_atomic_state {
intel_wakeref_t wakeref;
+ struct __intel_global_objs_state *global_objs;
+ int num_global_objs;
+
struct intel_cdclk_state cdclk_state;
bool dpll_set, modeset;
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c
new file mode 100644
index 000000000000..a0cc894c3868
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_state.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include <linux/string.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_display_types.h"
+#include "intel_global_state.h"
+
+void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
+ struct intel_global_obj *obj,
+ struct intel_global_state *state,
+ const struct intel_global_state_funcs *funcs)
+{
+ memset(obj, 0, sizeof(*obj));
+
+ obj->state = state;
+ obj->funcs = funcs;
+ list_add_tail(&obj->head, &dev_priv->global_obj_list);
+}
+
+void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv)
+{
+ struct intel_global_obj *obj, *next;
+
+ list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) {
+ list_del(&obj->head);
+ obj->funcs->atomic_destroy_state(obj, obj->state);
+ }
+}
+
+static void assert_global_state_write_locked(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc)
+ drm_modeset_lock_assert_held(&crtc->base.mutex);
+}
+
+static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx,
+ struct drm_modeset_lock *lock)
+{
+ struct drm_modeset_lock *l;
+
+ list_for_each_entry(l, &ctx->locked, head) {
+ if (lock == l)
+ return true;
+ }
+
+ return false;
+}
+
+static void assert_global_state_read_locked(struct intel_atomic_state *state)
+{
+ struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ if (modeset_lock_is_held(ctx, &crtc->base.mutex))
+ return;
+ }
+
+ WARN(1, "Global state not read locked\n");
+}
+
+struct intel_global_state *
+intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int index, num_objs, i;
+ size_t size;
+ struct __intel_global_objs_state *arr;
+ struct intel_global_state *obj_state;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].state;
+
+ assert_global_state_read_locked(state);
+
+ num_objs = state->num_global_objs + 1;
+ size = sizeof(*state->global_objs) * num_objs;
+ arr = krealloc(state->global_objs, size, GFP_KERNEL);
+ if (!arr)
+ return ERR_PTR(-ENOMEM);
+
+ state->global_objs = arr;
+ index = state->num_global_objs;
+ memset(&state->global_objs[index], 0, sizeof(*state->global_objs));
+
+ obj_state = obj->funcs->atomic_duplicate_state(obj);
+ if (!obj_state)
+ return ERR_PTR(-ENOMEM);
+
+ obj_state->changed = false;
+
+ state->global_objs[index].state = obj_state;
+ state->global_objs[index].old_state = obj->state;
+ state->global_objs[index].new_state = obj_state;
+ state->global_objs[index].ptr = obj;
+ obj_state->state = state;
+
+ state->num_global_objs = num_objs;
+
+ DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
+ obj, obj_state, state);
+
+ return obj_state;
+}
+
+struct intel_global_state *
+intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].old_state;
+
+ return NULL;
+}
+
+struct intel_global_state *
+intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++)
+ if (obj == state->global_objs[i].ptr)
+ return state->global_objs[i].new_state;
+
+ return NULL;
+}
+
+void intel_atomic_swap_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *old_obj_state, *new_obj_state;
+ struct intel_global_obj *obj;
+ int i;
+
+ for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
+ new_obj_state, i) {
+ WARN_ON(obj->state != old_obj_state);
+
+ /*
+ * If the new state wasn't modified (and properly
+ * locked for write access) we throw it away.
+ */
+ if (!new_obj_state->changed)
+ continue;
+
+ assert_global_state_write_locked(dev_priv);
+
+ old_obj_state->state = state;
+ new_obj_state->state = NULL;
+
+ state->global_objs[i].state = old_obj_state;
+ obj->state = new_obj_state;
+ }
+}
+
+void intel_atomic_clear_global_state(struct intel_atomic_state *state)
+{
+ int i;
+
+ for (i = 0; i < state->num_global_objs; i++) {
+ struct intel_global_obj *obj = state->global_objs[i].ptr;
+
+ obj->funcs->atomic_destroy_state(obj,
+ state->global_objs[i].state);
+ state->global_objs[i].ptr = NULL;
+ state->global_objs[i].state = NULL;
+ state->global_objs[i].old_state = NULL;
+ state->global_objs[i].new_state = NULL;
+ }
+ state->num_global_objs = 0;
+}
+
+int intel_atomic_lock_global_state(struct intel_global_state *obj_state)
+{
+ struct intel_atomic_state *state = obj_state->state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ int ret;
+
+ ret = drm_modeset_lock(&crtc->base.mutex,
+ state->base.acquire_ctx);
+ if (ret)
+ return ret;
+ }
+
+ obj_state->changed = true;
+
+ return 0;
+}
+
+int intel_atomic_serialize_global_state(struct intel_global_state *obj_state)
+{
+ struct intel_atomic_state *state = obj_state->state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ obj_state->changed = true;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
new file mode 100644
index 000000000000..e6163a469029
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_global_state.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_GLOBAL_STATE_H__
+#define __INTEL_GLOBAL_STATE_H__
+
+#include <linux/list.h>
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_global_obj;
+struct intel_global_state;
+
+struct intel_global_state_funcs {
+ struct intel_global_state *(*atomic_duplicate_state)(struct intel_global_obj *obj);
+ void (*atomic_destroy_state)(struct intel_global_obj *obj,
+ struct intel_global_state *state);
+};
+
+struct intel_global_obj {
+ struct list_head head;
+ struct intel_global_state *state;
+ const struct intel_global_state_funcs *funcs;
+};
+
+#define intel_for_each_global_obj(obj, dev_priv) \
+ list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
+
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
+
+struct intel_global_state {
+ struct intel_atomic_state *state;
+ bool changed;
+};
+
+struct __intel_global_objs_state {
+ struct intel_global_obj *ptr;
+ struct intel_global_state *state, *old_state, *new_state;
+};
+
+void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
+ struct intel_global_obj *obj,
+ struct intel_global_state *state,
+ const struct intel_global_state_funcs *funcs);
+void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv);
+
+struct intel_global_state *
+intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+struct intel_global_state *
+intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+struct intel_global_state *
+intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
+ struct intel_global_obj *obj);
+
+void intel_atomic_swap_global_state(struct intel_atomic_state *state);
+void intel_atomic_clear_global_state(struct intel_atomic_state *state);
+int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
+int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1787bfdd057f..b558e68b4dbd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -71,6 +71,7 @@
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
+#include "display/intel_global_state.h"
#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
@@ -1100,6 +1101,8 @@ struct drm_i915_private {
*/
struct mutex dpll_lock;
+ struct list_head global_obj_list;
+
/*
* For reading active_pipes, cdclk_state holding any crtc
* lock is sufficient, for writing must hold all of them.
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (13 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-27 15:21 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
` (8 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that we have the more formal global state thing let's
use if for memory bandwidth tracking. No real difference
to the current private object usage since we already
tried to avoid taking the single serializing lock needlessly.
But since we're going to roll the global state out to more
things probably a good idea to unify the approaches a bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 31 +++++++++-----------
drivers/gpu/drm/i915/display/intel_bw.h | 4 +--
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/i915_drv.h | 2 +-
4 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b228671d5a5d..316abcf3e6a2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,10 +374,9 @@ static struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct drm_private_state *bw_state;
+ struct intel_global_state *bw_state;
- bw_state = drm_atomic_get_private_obj_state(&state->base,
- &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj);
if (IS_ERR(bw_state))
return ERR_CAST(bw_state);
@@ -392,7 +391,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -433,6 +432,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (!bw_state)
return 0;
+ ret = intel_atomic_lock_global_state(&bw_state->base);
+ if (ret)
+ return ret;
+
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
@@ -449,7 +452,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return 0;
}
-static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj)
+static struct intel_global_state *
+intel_bw_duplicate_state(struct intel_global_obj *obj)
{
struct intel_bw_state *state;
@@ -457,18 +461,16 @@ static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj
if (!state)
return NULL;
- __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
-
return &state->base;
}
-static void intel_bw_destroy_state(struct drm_private_obj *obj,
- struct drm_private_state *state)
+static void intel_bw_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
{
kfree(state);
}
-static const struct drm_private_state_funcs intel_bw_funcs = {
+static const struct intel_global_state_funcs intel_bw_funcs = {
.atomic_duplicate_state = intel_bw_duplicate_state,
.atomic_destroy_state = intel_bw_destroy_state,
};
@@ -481,13 +483,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
if (!state)
return -ENOMEM;
- drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj,
- &state->base, &intel_bw_funcs);
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj,
+ &state->base, &intel_bw_funcs);
return 0;
}
-
-void intel_bw_cleanup(struct drm_i915_private *dev_priv)
-{
- drm_atomic_private_obj_fini(&dev_priv->bw_obj);
-}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 20b9ad241802..a8aa7624c5aa 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -9,13 +9,14 @@
#include <drm/drm_atomic.h>
#include "intel_display.h"
+#include "intel_global_state.h"
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
struct intel_bw_state {
- struct drm_private_state base;
+ struct intel_global_state base;
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
@@ -25,7 +26,6 @@ struct intel_bw_state {
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
-void intel_bw_cleanup(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70eb6eaab095..f5396c5c00c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18566,8 +18566,6 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
intel_gmbus_teardown(i915);
- intel_bw_cleanup(i915);
-
destroy_workqueue(i915->flip_wq);
destroy_workqueue(i915->modeset_wq);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b558e68b4dbd..63cda89a4e62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1251,7 +1251,7 @@ struct drm_i915_private {
u8 num_planes;
} max_bw[6];
- struct drm_private_obj bw_obj;
+ struct intel_global_obj bw_obj;
struct intel_runtime_pm runtime_pm;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes()
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (14 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-27 15:25 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
` (7 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract a small helper to compute the active pipes bitmask
based on the old bitmask + the crtcs in the atomic state.
I want to decouple the cdclk state entirely from the current
global state so I want to track the active pipes also inside
the (to be introduced) full cdclk state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
drivers/gpu/drm/i915/display/intel_display.h | 3 ++
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f5396c5c00c6..dc767efffd9a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14359,26 +14359,32 @@ static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
return 0;
}
+u8 intel_calc_active_pipes(struct intel_atomic_state *state,
+ u8 active_pipes)
+{
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (crtc_state->hw.active)
+ active_pipes |= BIT(crtc->pipe);
+ else
+ active_pipes &= ~BIT(crtc->pipe);
+ }
+
+ return active_pipes;
+}
+
static int intel_modeset_checks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc_state *old_crtc_state, *new_crtc_state;
- struct intel_crtc *crtc;
- int ret, i;
+ int ret;
state->modeset = true;
- state->active_pipes = dev_priv->active_pipes;
+ state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes);
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- if (new_crtc_state->hw.active)
- state->active_pipes |= BIT(crtc->pipe);
- else
- state->active_pipes &= ~BIT(crtc->pipe);
-
- if (old_crtc_state->hw.active != new_crtc_state->hw.active)
- state->active_pipe_changes |= BIT(crtc->pipe);
- }
+ state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes;
if (state->active_pipe_changes) {
ret = _intel_atomic_lock_global_state(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 028aab728514..e2de0d9d22bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -44,6 +44,7 @@ struct drm_modeset_acquire_ctx;
struct drm_plane;
struct drm_plane_state;
struct i915_ggtt_view;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
@@ -469,6 +470,8 @@ enum phy_fia {
((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+u8 intel_calc_active_pipes(struct intel_atomic_state *state,
+ u8 active_pipes);
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (15 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-21 14:03 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
` (6 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's convert cdclk_state to be a proper global state. That allows
us to use the regular atomic old vs. new state accessor, hopefully
making the code less confusing.
We do have to deal with a few more error cases in case the cdclk
state duplication fails. But so be it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
.../gpu/drm/i915/display/intel_atomic_plane.c | 68 ++++---
.../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
drivers/gpu/drm/i915/display/intel_audio.c | 39 +++-
drivers/gpu/drm/i915/display/intel_cdclk.c | 192 ++++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 45 +++-
drivers/gpu/drm/i915/display/intel_display.c | 122 +++++++----
.../drm/i915/display/intel_display_types.h | 3 -
drivers/gpu/drm/i915/i915_drv.h | 45 +---
9 files changed, 316 insertions(+), 204 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 45842ebcdebd..b51ddf9a250f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -518,7 +518,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
- intel_cdclk_clear_state(state);
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 563caec1d201..1a0bbcf52516 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -37,6 +37,7 @@
#include "i915_trace.h"
#include "intel_atomic_plane.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
@@ -155,44 +156,61 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
-bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
- struct intel_plane *plane)
+int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane,
+ bool *need_cdclk_calc)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
- struct intel_crtc_state *crtc_state;
+ const struct intel_cdclk_state *cdclk_state;
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
if (!plane_state->uapi.visible || !plane->min_cdclk)
- return false;
+ return 0;
+
+ new_crtc_state->min_cdclk[plane->id] =
+ plane->min_cdclk(new_crtc_state, plane_state);
- crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ /*
+ * No need to check against the cdclk state if
+ * the min cdclk for the plane doesn't increase.
+ *
+ * Ie. we only ever increase the cdclk due to plane
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
+ */
+ if (new_crtc_state->min_cdclk[plane->id] <=
+ old_crtc_state->min_cdclk[plane->id])
+ return 0;
- crtc_state->min_cdclk[plane->id] =
- plane->min_cdclk(crtc_state, plane_state);
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
/*
- * Does the cdclk need to be bumbed up?
+ * No need to recalculate the cdclk state if
+ * the min cdclk for the pipe doesn't increase.
*
- * Note: we obviously need to be called before the new
- * cdclk frequency is calculated so state->cdclk.logical
- * hasn't been populated yet. Hence we look at the old
- * cdclk state under dev_priv->cdclk.logical. This is
- * safe as long we hold at least one crtc mutex (which
- * must be true since we have crtc_state).
+ * Ie. we only ever increase the cdclk due to plane
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
*/
- if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
- DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
- plane->base.base.id, plane->base.name,
- crtc_state->min_cdclk[plane->id],
- cdclk_state->logical.cdclk);
- return true;
- }
+ if (cdclk_state->min_cdclk[crtc->pipe] <=
+ new_crtc_state->min_cdclk[plane->id])
+ return 0;
+
+ DRM_DEBUG_KMS("[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
+ plane->base.base.id, plane->base.name,
+ new_crtc_state->min_cdclk[plane->id],
+ crtc->base.base.id, crtc->base.name,
+ cdclk_state->min_cdclk[crtc->pipe]);
+ *need_cdclk_calc = true;
- return false;
+ return 0;
}
static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 5cedafdddb55..2bcf15e34728 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *plane_state);
-bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
- struct intel_plane *plane);
+int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane,
+ bool *need_cdclk_calc);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 12626fd94d29..9debac75eaec 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -30,6 +30,7 @@
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_audio.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_lpe_audio.h"
@@ -800,6 +801,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state;
+ struct intel_crtc *crtc;
+ int ret;
+
+ /* need to hold at least one crtc lock for the global state */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
+ if (ret)
+ return ret;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ cdclk_state->force_min_cdclk_changed = true;
+ cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
+
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
+ if (ret)
+ return ret;
+
+ return drm_atomic_commit(&state->base);
+}
+
static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
bool enable)
{
@@ -815,15 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
state->acquire_ctx = &ctx;
retry:
- to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
- to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
- enable ? 2 * 96000 : 0;
-
- /* Protects dev_priv->cdclk.force_min_cdclk */
- ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
- if (!ret)
- ret = drm_atomic_commit(state);
-
+ ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
if (ret == -EDEADLK) {
drm_atomic_state_clear(state);
drm_modeset_backoff(&ctx);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3b7932ae2a77..e14bda2bec71 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1807,37 +1807,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
a->voltage_level != b->voltage_level;
}
-/**
- * intel_cdclk_clear_state - clear the cdclk state
- * @state: atomic state
- *
- * Clear the cdclk state for ww_mutex backoff.
- */
-void intel_cdclk_clear_state(struct intel_atomic_state *state)
-{
- memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
- state->cdclk_state.pipe = INVALID_PIPE;
-}
-
-/**
- * intel_cdclk_swap_state - make atomic CDCLK configuration effective
- * @state: atomic state
- *
- * This is the CDCLK version of drm_atomic_helper_swap_state() since the
- * helper does not handle driver-specific global state.
- *
- * Similarly to the atomic helpers this function does a complete swap,
- * i.e. it also puts the old state into @state. This is used by the commit
- * code to determine how CDCLK has changed (for instance did it increase or
- * decrease).
- */
-void intel_cdclk_swap_state(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-
- swap(state->cdclk_state, dev_priv->cdclk_state);
-}
-
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context)
{
@@ -1888,14 +1857,22 @@ void
intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- /* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
- const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state =
+ intel_atomic_get_old_cdclk_state(state);
+ const struct intel_cdclk_state *new_cdclk_state =
+ intel_atomic_get_new_cdclk_state(state);
enum pipe pipe = new_cdclk_state->pipe;
+ if (!intel_cdclk_changed(&old_cdclk_state->actual,
+ &new_cdclk_state->actual))
+ return;
+
if (pipe == INVALID_PIPE ||
- old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
+ old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
+ WARN_ON(!new_cdclk_state->base.changed);
+
intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
+ }
}
/**
@@ -1909,14 +1886,22 @@ void
intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- /* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
- const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state =
+ intel_atomic_get_old_cdclk_state(state);
+ const struct intel_cdclk_state *new_cdclk_state =
+ intel_atomic_get_new_cdclk_state(state);
enum pipe pipe = new_cdclk_state->pipe;
+ if (!intel_cdclk_changed(&old_cdclk_state->actual,
+ &new_cdclk_state->actual))
+ return;
+
if (pipe != INVALID_PIPE &&
- old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
+ old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
+ WARN_ON(!new_cdclk_state->base.changed);
+
intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
+ }
}
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
@@ -2042,10 +2027,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
-static int intel_compute_min_cdclk(struct intel_atomic_state *state)
+static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
@@ -2063,7 +2048,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
cdclk_state->min_cdclk[i] = min_cdclk;
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
if (ret)
return ret;
}
@@ -2088,10 +2073,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
* future platforms this code will need to be
* adjusted.
*/
-static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
+static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
u8 min_voltage_level;
@@ -2111,7 +2096,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
cdclk_state->min_voltage_level[i] = min_voltage_level;
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
if (ret)
return ret;
}
@@ -2124,13 +2109,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
return min_voltage_level;
}
-static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, cdclk;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
@@ -2153,12 +2138,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
+ struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
@@ -2185,10 +2170,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int skl_dpll0_vco(struct intel_atomic_state *state)
+static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int vco, i;
@@ -2222,16 +2207,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
return vco;
}
-static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
+ struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk, vco;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
- vco = skl_dpll0_vco(state);
+ vco = skl_dpll0_vco(cdclk_state);
/*
* FIXME should also account for plane ratio
@@ -2258,17 +2243,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, min_voltage_level, cdclk, vco;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
- min_voltage_level = bxt_compute_min_voltage_level(state);
+ min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
if (min_voltage_level < 0)
return min_voltage_level;
@@ -2335,7 +2320,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
return 0;
}
-static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
int min_cdclk;
@@ -2344,54 +2329,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
* check that the required minimum frequency doesn't exceed
* the actual cdclk frequency.
*/
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
return 0;
}
+static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
+ if (!cdclk_state)
+ return NULL;
+
+ cdclk_state->force_min_cdclk_changed = false;
+ cdclk_state->pipe = INVALID_PIPE;
+
+ return &cdclk_state->base;
+}
+
+static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_cdclk_funcs = {
+ .atomic_duplicate_state = intel_cdclk_duplicate_state,
+ .atomic_destroy_state = intel_cdclk_destroy_state,
+};
+
+struct intel_cdclk_state *
+intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *cdclk_state;
+
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ if (IS_ERR(cdclk_state))
+ return ERR_CAST(cdclk_state);
+
+ return to_intel_cdclk_state(cdclk_state);
+}
+
+int intel_cdclk_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
+ if (!cdclk_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ &cdclk_state->base, &intel_cdclk_funcs);
+
+ return 0;
+}
+
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
- struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state;
+ struct intel_cdclk_state *new_cdclk_state;
enum pipe pipe;
int ret;
- memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
- sizeof(new_cdclk_state->min_cdclk));
- memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
- sizeof(new_cdclk_state->min_voltage_level));
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
- /* keep the current setting */
- if (!new_cdclk_state->force_min_cdclk_changed)
- new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
+ old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
- new_cdclk_state->logical = old_cdclk_state->logical;
- new_cdclk_state->actual = old_cdclk_state->actual;
-
- ret = dev_priv->display.modeset_calc_cdclk(state);
+ ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
if (ret)
return ret;
- /*
- * Writes to dev_priv->cdclk.{actual,logical} must protected
- * by holding all the crtc mutexes even if we don't end up
- * touching the hardware
- */
if (intel_cdclk_changed(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
/*
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
*/
- ret = _intel_atomic_serialize_global_state(state);
+ ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
if (ret)
return ret;
} else if (intel_cdclk_changed(&old_cdclk_state->logical,
&new_cdclk_state->logical)) {
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
if (ret)
return ret;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 4b965db07720..195fca70bfcb 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -8,11 +8,12 @@
#include <linux/types.h>
+#include "i915_drv.h"
#include "intel_display.h"
+#include "intel_global_state.h"
struct drm_i915_private;
struct intel_atomic_state;
-struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_cdclk_vals {
@@ -22,6 +23,35 @@ struct intel_cdclk_vals {
u8 ratio;
};
+struct intel_cdclk_state {
+ struct intel_global_state base;
+
+ /*
+ * Logical configuration of cdclk (used for all scaling,
+ * watermark, etc. calculations and checks). This is
+ * computed as if all enabled crtcs were active.
+ */
+ struct intel_cdclk_config logical;
+
+ /*
+ * Actual configuration of cdclk, can be different from the
+ * logical configuration only when all crtc's are DPMS off.
+ */
+ struct intel_cdclk_config actual;
+
+ /* minimum acceptable cdclk for each pipe */
+ int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
+
+ /* pipe to which cd2x update is synchronized */
+ enum pipe pipe;
+
+ /* forced minimum cdclk for glk+ audio w/a */
+ int force_min_cdclk;
+ bool force_min_cdclk_changed;
+};
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
void intel_cdclk_init_hw(struct drm_i915_private *i915);
void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
@@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
-void intel_cdclk_clear_state(struct intel_atomic_state *state);
-void intel_cdclk_swap_state(struct intel_atomic_state *state);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
+struct intel_cdclk_state *
+intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
+
+#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
+#define intel_atomic_get_old_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+#define intel_atomic_get_new_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+
+int intel_cdclk_init(struct drm_i915_private *dev_priv);
+
#endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dc767efffd9a..dca100546be8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7482,7 +7482,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum intel_display_power_domain domain;
@@ -7780,17 +7780,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
return true;
}
-static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
+static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
to_i915(crtc_state->uapi.crtc->dev);
- struct intel_atomic_state *intel_state =
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
- const struct intel_cdclk_state *cdclk_state =
- &intel_state->cdclk_state;
+
+ crtc_state->ips_enabled = false;
if (!hsw_crtc_state_ips_capable(crtc_state))
- return false;
+ return 0;
/*
* When IPS gets enabled, the pipe CRC changes. Since IPS gets
@@ -7799,18 +7799,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
* completely disable it.
*/
if (crtc_state->crc_enabled)
- return false;
+ return 0;
/* IPS should be fine as long as at least one plane is enabled. */
if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
- return false;
+ return 0;
- /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (IS_BROADWELL(dev_priv) &&
- crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
- return false;
+ if (IS_BROADWELL(dev_priv)) {
+ const struct intel_cdclk_state *cdclk_state;
- return true;
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+ if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+ return 0;
+ }
+
+ crtc_state->ips_enabled = true;
+
+ return 0;
}
static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
@@ -12543,14 +12552,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
adjusted_mode->crtc_clock);
}
-static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_cdclk_state *cdclk_state)
{
- const struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- const struct intel_cdclk_state *cdclk_state =
- &state->cdclk_state;
if (!crtc_state->hw.enable)
return 0;
@@ -12580,6 +12586,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
return linetime_wm;
}
+static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_cdclk_state *cdclk_state;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ crtc_state->linetime = skl_linetime_wm(crtc_state);
+ else
+ crtc_state->linetime = hsw_linetime_wm(crtc_state);
+
+ if (!hsw_crtc_supports_ips(crtc))
+ return 0;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
+ cdclk_state);
+
+ return 0;
+}
+
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -12615,7 +12647,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- ret = 0;
if (dev_priv->display.compute_pipe_wm) {
ret = dev_priv->display.compute_pipe_wm(crtc_state);
if (ret) {
@@ -12646,20 +12677,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (!ret)
ret = intel_atomic_setup_scalers(dev_priv, crtc,
crtc_state);
+ if (ret)
+ return ret;
}
- if (HAS_IPS(dev_priv))
- crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
+ if (HAS_IPS(dev_priv)) {
+ ret = hsw_compute_ips_config(crtc_state);
+ if (ret)
+ return ret;
+ }
+
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ ret = hsw_compute_linetime_wm(state, crtc);
+ if (ret)
+ return ret;
- if (INTEL_GEN(dev_priv) >= 9) {
- crtc_state->linetime = skl_linetime_wm(crtc_state);
- } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
- crtc_state->linetime = hsw_linetime_wm(crtc_state);
- if (hsw_crtc_supports_ips(crtc))
- crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
}
- return ret;
+ return 0;
}
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
@@ -14478,7 +14514,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
}
static int intel_atomic_check_planes(struct intel_atomic_state *state,
- bool *need_modeset)
+ bool *need_cdclk_calc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
@@ -14532,8 +14568,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
* affected planes are part of the state. We can now
* compute the minimum cdclk for each plane.
*/
- for_each_new_intel_plane_in_state(state, plane, plane_state, i)
- *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -14654,6 +14693,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_atomic_state *state = to_intel_atomic_state(_state);
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_cdclk_state *new_cdclk_state;
struct intel_crtc *crtc;
int ret, i;
bool any_ms = false;
@@ -14766,18 +14806,18 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- any_ms |= state->cdclk_state.force_min_cdclk_changed;
-
ret = intel_atomic_check_planes(state, &any_ms);
if (ret)
goto fail;
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
+ any_ms = true;
+
if (any_ms) {
ret = intel_modeset_checks(state);
if (ret)
goto fail;
- } else {
- state->cdclk_state.logical = dev_priv->cdclk_state.logical;
}
ret = intel_atomic_check_crtcs(state);
@@ -15676,8 +15716,6 @@ static int intel_atomic_commit(struct drm_device *dev,
assert_global_state_locked(dev_priv);
dev_priv->active_pipes = state->active_pipes;
-
- intel_cdclk_swap_state(state);
}
drm_atomic_state_get(&state->base);
@@ -17356,7 +17394,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
struct intel_cdclk_state *cdclk_state =
- &i915->cdclk_state;
+ to_intel_cdclk_state(i915->cdclk.obj.state);
intel_update_cdclk(i915);
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
@@ -17587,6 +17625,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_mode_config_init(i915);
+ ret = intel_cdclk_init(i915);
+ if (ret)
+ return ret;
+
ret = intel_bw_init(i915);
if (ret)
return ret;
@@ -18071,6 +18113,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
static void intel_modeset_readout_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_cdclk_state *cdclk_state =
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -18190,8 +18234,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
- struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 628c4a56a9e9..524b6d5235ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -465,8 +465,6 @@ struct intel_atomic_state {
struct __intel_global_objs_state *global_objs;
int num_global_objs;
- struct intel_cdclk_state cdclk_state;
-
bool dpll_set, modeset;
/*
@@ -493,7 +491,6 @@ struct intel_atomic_state {
/*
* active_pipes
- * cdclk_state
*/
bool global_state_changed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63cda89a4e62..2e6b149478c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -65,7 +65,6 @@
#include "i915_utils.h"
#include "display/intel_bios.h"
-#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
@@ -258,7 +257,8 @@ struct intel_connector;
struct intel_encoder;
struct intel_atomic_state;
struct intel_cdclk_config;
-struct intel_crtc_state;
+struct intel_cdclk_state;
+struct intel_cdclk_vals;
struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
@@ -282,7 +282,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
- int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
+ int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -891,33 +891,6 @@ struct i915_selftest_stash {
atomic_t counter;
};
-struct intel_cdclk_state {
- /*
- * Logical configuration of cdclk (used for all scaling,
- * watermark, etc. calculations and checks). This is
- * computed as if all enabled crtcs were active.
- */
- struct intel_cdclk_config logical;
-
- /*
- * Actual configuration of cdclk, can be different from the
- * logical configuration only when all crtc's are DPMS off.
- */
- struct intel_cdclk_config actual;
-
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
-
- /* pipe to which cd2x update is synchronized */
- enum pipe pipe;
-
- /* forced minimum cdclk for glk+ audio w/a */
- int force_min_cdclk;
- bool force_min_cdclk_changed;
-};
-
struct drm_i915_private {
struct drm_device drm;
@@ -1034,18 +1007,14 @@ struct drm_i915_private {
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- /*
- * For reading holding any crtc lock is sufficient,
- * for writing must hold all of them.
- */
- struct intel_cdclk_state cdclk_state;
-
struct {
/* The current hardware cdclk configuration */
struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
} cdclk;
/**
@@ -1104,8 +1073,8 @@ struct drm_i915_private {
struct list_head global_obj_list;
/*
- * For reading active_pipes, cdclk_state holding any crtc
- * lock is sufficient, for writing must hold all of them.
+ * For reading active_pipes holding any crtc lock is
+ * sufficient, for writing must hold all of them.
*/
u8 active_pipes;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (16 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
@ 2020-01-20 17:47 ` Ville Syrjala
2020-01-27 17:11 ` Imre Deak
2020-01-20 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework Patchwork
` (5 subsequent siblings)
23 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-20 17:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's add a copy of the active_pipes bitmask into the cdclk_state.
While this is duplicating a bit of information we may already
have elsewhere, I think it's worth it to decopule the cdclk stuff
from whatever else wants to use that bitmask. Also we want to get
rid of all the old ad-hoc global state which is what the current
bitmask is, so this removes one obstacle.
The one extra thing we have to remember is write locking the cdclk
state whenever the bitmask changes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 20 +++++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 8 +++++---
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e14bda2bec71..f8e4510f4bd9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2125,7 +2125,7 @@ static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.voltage_level =
vlv_calc_voltage_level(dev_priv, cdclk);
- if (!state->active_pipes) {
+ if (!cdclk_state->active_pipes) {
cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
cdclk_state->actual.cdclk = cdclk;
@@ -2140,7 +2140,6 @@ static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk;
min_cdclk = intel_compute_min_cdclk(cdclk_state);
@@ -2157,7 +2156,7 @@ static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.voltage_level =
bdw_calc_voltage_level(cdclk);
- if (!state->active_pipes) {
+ if (!cdclk_state->active_pipes) {
cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
cdclk_state->actual.cdclk = cdclk;
@@ -2209,7 +2208,6 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk, vco;
min_cdclk = intel_compute_min_cdclk(cdclk_state);
@@ -2229,7 +2227,7 @@ static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.voltage_level =
skl_calc_voltage_level(cdclk);
- if (!state->active_pipes) {
+ if (!cdclk_state->active_pipes) {
cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
cdclk_state->actual.vco = vco;
@@ -2266,7 +2264,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
max_t(int, min_voltage_level,
dev_priv->display.calc_voltage_level(cdclk));
- if (!state->active_pipes) {
+ if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
@@ -2402,6 +2400,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
+ new_cdclk_state->active_pipes =
+ intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
+
ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
if (ret)
return ret;
@@ -2415,7 +2416,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
if (ret)
return ret;
- } else if (intel_cdclk_changed(&old_cdclk_state->logical,
+ } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
+ intel_cdclk_changed(&old_cdclk_state->logical,
&new_cdclk_state->logical)) {
ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
if (ret)
@@ -2424,14 +2426,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
- if (is_power_of_2(state->active_pipes) &&
+ if (is_power_of_2(new_cdclk_state->active_pipes) &&
intel_cdclk_can_cd2x_update(dev_priv,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- pipe = ilog2(state->active_pipes);
+ pipe = ilog2(new_cdclk_state->active_pipes);
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 195fca70bfcb..df21dbdcc575 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -50,6 +50,9 @@ struct intel_cdclk_state {
/* forced minimum cdclk for glk+ audio w/a */
int force_min_cdclk;
bool force_min_cdclk_changed;
+
+ /* bitmask of active pipes */
+ u8 active_pipes;
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dca100546be8..27878c484307 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7551,6 +7551,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
dev_priv->active_pipes &= ~BIT(pipe);
cdclk_state->min_cdclk[pipe] = 0;
cdclk_state->min_voltage_level[pipe] = 0;
+ cdclk_state->active_pipes &= ~BIT(pipe);
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
@@ -18120,10 +18121,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_encoder *encoder;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
+ u8 active_pipes = 0;
int i;
- dev_priv->active_pipes = 0;
-
for_each_intel_crtc(dev, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -18139,13 +18139,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc->active = crtc_state->hw.active;
if (crtc_state->hw.active)
- dev_priv->active_pipes |= BIT(crtc->pipe);
+ active_pipes |= BIT(crtc->pipe);
DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
crtc->base.base.id, crtc->base.name,
enableddisabled(crtc_state->hw.active));
}
+ dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
+
readout_plane_state(dev_priv);
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (17 preceding siblings ...)
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
@ 2020-01-20 18:43 ` Patchwork
2020-01-21 2:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-20 18:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework
URL : https://patchwork.freedesktop.org/series/72301/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e1d119e88d09 drm/i915: Polish WM_LINETIME register stuff
15d81d275b12 drm/i915: Move linetime wms into the crtc state
a12b752d48ca drm/i915: Nuke skl wm.dirty_pipes bitmask
7ba0656a9ef9 drm/i915: Move more cdclk state handling into the cdclk code
8fa8a8a6f02c drm/i915: Collect more cdclk state under the same roof
ed13dd33279b drm/i915: s/need_cd2x_updare/can_cd2x_update/
0a56243699e8 drm/i915: s/cdclk_state/cdclk_config/
-:519: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#519: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:870:
+ cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
total: 0 errors, 0 warnings, 1 checks, 1148 lines checked
6135aca100dd drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
05f542367737 drm/i915: Extract intel_cdclk_state
-:541: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#541: FILE: drivers/gpu/drm/i915/display/intel_display.c:17366:
+ cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
total: 0 errors, 0 warnings, 1 checks, 621 lines checked
d5ec3a11033c drm/i915: swap() the entire cdclk state
108769339a1d drm/i915: s/init_cdclk/init_cdclk_hw/
c2a1d81e4b77 drm/i915: Move intel_atomic_state_free() into intel_atomic.c
dd55cc8a69c4 drm/i915: Intrduce better global state handling
-:230: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#230:
new file mode 100644
-:235: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_global_state.c', please use '//' instead
#235: FILE: drivers/gpu/drm/i915/display/intel_global_state.c:1:
+/* SPDX-License-Identifier: MIT */
-:235: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#235: FILE: drivers/gpu/drm/i915/display/intel_global_state.c:1:
+/* SPDX-License-Identifier: MIT */
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
total: 0 errors, 3 warnings, 9 checks, 484 lines checked
2f070d20f5ad drm/i915: Convert bandwidth state to global state
b7355be8116f drm/i915: Introduce intel_calc_active_pipes()
5f3f030c5ac1 drm/i915: Convert cdclk to global state
-:633: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#633: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:74:
+#define intel_atomic_get_old_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:634: WARNING:LONG_LINE: line over 100 characters
#634: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:75:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:635: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#635: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:76:
+#define intel_atomic_get_new_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:636: WARNING:LONG_LINE: line over 100 characters
#636: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:77:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
total: 0 errors, 2 warnings, 2 checks, 922 lines checked
dd68e8f33fde drm/i915: Store active_pipes bitmask in cdclk state
-:164: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#164: FILE: drivers/gpu/drm/i915/display/intel_display.c:18149:
+ dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
total: 0 errors, 0 warnings, 1 checks, 123 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Global state rework
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (18 preceding siblings ...)
2020-01-20 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework Patchwork
@ 2020-01-21 2:10 ` Patchwork
2020-01-21 13:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-21 2:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework
URL : https://patchwork.freedesktop.org/series/72301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7781 -> Patchwork_16175
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/index.html
Known issues
------------
Here are the changes found in Patchwork_16175 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-no-display:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#58] / [k.org#198133])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/fi-glk-dsi/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/fi-glk-dsi/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][3] -> [DMESG-WARN][4] ([i915#889]) +23 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gt_lrc:
- fi-skl-6600u: [PASS][5] -> [DMESG-FAIL][6] ([i915#889]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/fi-hsw-4770r/igt@i915_selftest@live_blt.html
#### Warnings ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [TIMEOUT][9] ([fdo#112271]) -> [INCOMPLETE][10] ([i915#45])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 38)
------------------------------
Missing (12): fi-ilk-m540 fi-ehl-1 fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-snb-2520m fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7781 -> Patchwork_16175
CI-20190529: 20190529
CI_DRM_7781: 3f2b341ae1fde67f823aeb715c6f489affdef8b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5374: 83c32e859202e43ff6a8cca162c76fcd90ad6e3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16175: dd68e8f33fde8b9c142b0475bceb4f95c1185aaf @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dd68e8f33fde drm/i915: Store active_pipes bitmask in cdclk state
5f3f030c5ac1 drm/i915: Convert cdclk to global state
b7355be8116f drm/i915: Introduce intel_calc_active_pipes()
2f070d20f5ad drm/i915: Convert bandwidth state to global state
dd55cc8a69c4 drm/i915: Intrduce better global state handling
c2a1d81e4b77 drm/i915: Move intel_atomic_state_free() into intel_atomic.c
108769339a1d drm/i915: s/init_cdclk/init_cdclk_hw/
d5ec3a11033c drm/i915: swap() the entire cdclk state
05f542367737 drm/i915: Extract intel_cdclk_state
6135aca100dd drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
0a56243699e8 drm/i915: s/cdclk_state/cdclk_config/
ed13dd33279b drm/i915: s/need_cd2x_updare/can_cd2x_update/
8fa8a8a6f02c drm/i915: Collect more cdclk state under the same roof
7ba0656a9ef9 drm/i915: Move more cdclk state handling into the cdclk code
a12b752d48ca drm/i915: Nuke skl wm.dirty_pipes bitmask
15d81d275b12 drm/i915: Move linetime wms into the crtc state
e1d119e88d09 drm/i915: Polish WM_LINETIME register stuff
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Global state rework
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (19 preceding siblings ...)
2020-01-21 2:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-01-21 13:32 ` Patchwork
2020-01-21 17:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2) Patchwork
` (2 subsequent siblings)
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-21 13:32 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework
URL : https://patchwork.freedesktop.org/series/72301/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7781_full -> Patchwork_16175_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16175_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16175_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16175_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-glk1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
Known issues
------------
Here are the changes found in Patchwork_16175_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111735] / [i915#472]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb8/igt@gem_ctx_shared@q-smoketest-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb1/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_create@forked:
- shard-glk: [PASS][9] -> [TIMEOUT][10] ([fdo#112271] / [i915#940])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-glk5/igt@gem_exec_create@forked.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk6/igt@gem_exec_create@forked.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd.html
* igt@gem_exec_schedule@smoketest-all:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#463] / [i915#472])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb4/igt@gem_exec_schedule@smoketest-all.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb6/igt@gem_exec_schedule@smoketest-all.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103665] / [i915#530])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl4/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl2/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
- shard-apl: [PASS][21] -> [INCOMPLETE][22] ([CI#80] / [fdo#103927] / [i915#530])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-apl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
- shard-tglb: [PASS][23] -> [TIMEOUT][24] ([fdo#112126] / [fdo#112271] / [i915#530])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-skl: [PASS][25] -> [TIMEOUT][26] ([fdo#112271] / [i915#530])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
- shard-kbl: [PASS][27] -> [TIMEOUT][28] ([fdo#112271] / [i915#530])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrash-inactive:
- shard-hsw: [PASS][29] -> [TIMEOUT][30] ([fdo#112271] / [i915#530]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw2/igt@gem_persistent_relocs@forked-thrash-inactive.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw5/igt@gem_persistent_relocs@forked-thrash-inactive.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-tglb: [PASS][31] -> [INCOMPLETE][32] ([i915#470] / [i915#472] / [i915#475])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb2/igt@gem_ppgtt@blt-vs-render-ctxn.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb3/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][33] -> [FAIL][34] ([i915#644])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [PASS][35] -> [INCOMPLETE][36] ([i915#472]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb1/igt@gem_sync@basic-store-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb4/igt@gem_sync@basic-store-all.html
* igt@gem_tiled_blits@normal:
- shard-hsw: [PASS][37] -> [FAIL][38] ([i915#694])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw4/igt@gem_tiled_blits@normal.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw4/igt@gem_tiled_blits@normal.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
- shard-kbl: [PASS][41] -> [INCOMPLETE][42] ([fdo#103665])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl7/igt@gem_workarounds@suspend-resume-context.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl2/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][43] -> [DMESG-WARN][44] ([i915#716])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_selftest@mock_requests:
- shard-skl: [PASS][45] -> [INCOMPLETE][46] ([i915#198])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl4/igt@i915_selftest@mock_requests.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl7/igt@i915_selftest@mock_requests.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-snb: [PASS][47] -> [SKIP][48] ([fdo#109271]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-snb6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-snb4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][49] -> [DMESG-WARN][50] ([i915#109]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl1/igt@kms_color@pipe-a-ctm-green-to-red.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl10/igt@kms_color@pipe-a-ctm-green-to-red.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][51] -> [INCOMPLETE][52] ([i915#61])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [PASS][53] -> [FAIL][54] ([i915#49])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][59] -> [SKIP][60] ([fdo#109441]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-iclb: [PASS][61] -> [DMESG-WARN][62] ([fdo#111764]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][63] -> [INCOMPLETE][64] ([i915#69])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109276]) +12 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@rcs0-mixed-process:
- shard-skl: [FAIL][69] ([i915#679]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl10/igt@gem_ctx_persistence@rcs0-mixed-process.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl9/igt@gem_ctx_persistence@rcs0-mixed-process.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [SKIP][71] ([fdo#109276] / [fdo#112080]) -> [PASS][72] +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb3/igt@gem_ctx_persistence@vcs1-queued.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][73] ([fdo#110854]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb3/igt@gem_exec_balancer@smoke.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb2/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_gttfill@basic:
- shard-tglb: [INCOMPLETE][75] ([fdo#111593] / [i915#472]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb3/igt@gem_exec_gttfill@basic.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb8/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_parallel@vcs0-fds:
- shard-tglb: [INCOMPLETE][77] ([i915#470] / [i915#472]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb2/igt@gem_exec_parallel@vcs0-fds.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb5/igt@gem_exec_parallel@vcs0-fds.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [SKIP][79] ([i915#677]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb4/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb8/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@pi-shared-iova-bsd2:
- shard-iclb: [SKIP][81] ([fdo#109276]) -> [PASS][82] +15 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb3/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb2/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][83] ([fdo#112146]) -> [PASS][84] +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-hsw: [INCOMPLETE][85] ([i915#530] / [i915#61]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw7/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-kbl: [TIMEOUT][87] ([fdo#112271] / [i915#530]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][89] ([i915#644]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][91] ([i915#472] / [i915#707]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb6/igt@gem_sync@basic-each.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb1/igt@gem_sync@basic-each.html
* igt@gem_sync@basic-store-each:
- shard-tglb: [INCOMPLETE][93] ([i915#472]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb7/igt@gem_sync@basic-store-each.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb5/igt@gem_sync@basic-store-each.html
* igt@i915_selftest@mock_requests:
- shard-hsw: [INCOMPLETE][95] ([i915#61]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw1/igt@i915_selftest@mock_requests.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw6/igt@i915_selftest@mock_requests.html
- shard-iclb: [INCOMPLETE][97] ([i915#140]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb8/igt@i915_selftest@mock_requests.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb3/igt@i915_selftest@mock_requests.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [FAIL][99] ([i915#54]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-tglb: [FAIL][101] ([i915#49]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][103] ([i915#180]) -> [PASS][104] +5 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [INCOMPLETE][105] ([i915#69]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][107] ([fdo#108145]) -> [PASS][108] +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][109] ([fdo#109441]) -> [PASS][110] +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][111] ([i915#31]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-apl2/igt@kms_setmode@basic.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-apl7/igt@kms_setmode@basic.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [SKIP][113] ([fdo#112080]) -> [PASS][114] +10 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb3/igt@perf_pmu@init-busy-vcs1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][115] ([fdo#109276] / [fdo#112080]) -> [FAIL][116] ([IGT#28]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_tiled_blits@interruptible:
- shard-hsw: [FAIL][117] ([i915#818]) -> [DMESG-FAIL][118] ([i915#44])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-hsw7/igt@gem_tiled_blits@interruptible.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-hsw7/igt@gem_tiled_blits@interruptible.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [FAIL][119] ([i915#454]) -> [SKIP][120] ([i915#468])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-tglb4/igt@i915_pm_dc@dc6-dpms.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
* igt@runner@aborted:
- shard-glk: [FAIL][121] ([i915#997] / [k.org#202321]) -> ([FAIL][122], [FAIL][123], [FAIL][124]) ([i915#940] / [i915#997] / [k.org#202321])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-glk1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk5/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk2/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-glk6/igt@runner@aborted.html
- shard-skl: ([FAIL][125], [FAIL][126]) ([i915#69] / [i915#997]) -> ([FAIL][127], [FAIL][128], [FAIL][129]) ([i915#69] / [i915#873] / [i915#997])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7781/shard-skl8/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl8/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl7/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/shard-skl6/igt@runner@aborted.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#475]: https://gitlab.freedesktop.org/drm/intel/issues/475
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#873]: https://gitlab.freedesktop.org/drm/intel/issues/873
[i915#940]: https://gitlab.freedesktop.org/drm/intel/issues/940
[i915#997]: https://gitlab.freedesktop.org/drm/intel/issues/997
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7781 -> Patchwork_16175
CI-20190529: 20190529
CI_DRM_7781: 3f2b341ae1fde67f823aeb715c6f489affdef8b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5374: 83c32e859202e43ff6a8cca162c76fcd90ad6e3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16175: dd68e8f33fde8b9c142b0475bceb4f95c1185aaf @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16175/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 16/17] drm/i915: Convert cdclk to global state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
@ 2020-01-21 14:03 ` Ville Syrjala
2020-01-27 17:03 ` Imre Deak
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2020-01-21 14:03 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's convert cdclk_state to be a proper global state. That allows
us to use the regular atomic old vs. new state accessor, hopefully
making the code less confusing.
We do have to deal with a few more error cases in case the cdclk
state duplication fails. But so be it.
v2: Fix new plane min_cdclk vs. old crtc min_cdclk check
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
.../gpu/drm/i915/display/intel_atomic_plane.c | 68 ++++---
.../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
drivers/gpu/drm/i915/display/intel_audio.c | 39 +++-
drivers/gpu/drm/i915/display/intel_cdclk.c | 192 ++++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 45 +++-
drivers/gpu/drm/i915/display/intel_display.c | 122 +++++++----
.../drm/i915/display/intel_display_types.h | 3 -
drivers/gpu/drm/i915/i915_drv.h | 45 +---
9 files changed, 316 insertions(+), 204 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 45842ebcdebd..b51ddf9a250f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -518,7 +518,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
- intel_cdclk_clear_state(state);
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 563caec1d201..230d0e4f6169 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -37,6 +37,7 @@
#include "i915_trace.h"
#include "intel_atomic_plane.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
@@ -155,44 +156,61 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
-bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
- struct intel_plane *plane)
+int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane,
+ bool *need_cdclk_calc)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
- struct intel_crtc_state *crtc_state;
+ const struct intel_cdclk_state *cdclk_state;
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
if (!plane_state->uapi.visible || !plane->min_cdclk)
- return false;
+ return 0;
+
+ new_crtc_state->min_cdclk[plane->id] =
+ plane->min_cdclk(new_crtc_state, plane_state);
- crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ /*
+ * No need to check against the cdclk state if
+ * the min cdclk for the plane doesn't increase.
+ *
+ * Ie. we only ever increase the cdclk due to plane
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
+ */
+ if (new_crtc_state->min_cdclk[plane->id] <=
+ old_crtc_state->min_cdclk[plane->id])
+ return 0;
- crtc_state->min_cdclk[plane->id] =
- plane->min_cdclk(crtc_state, plane_state);
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
/*
- * Does the cdclk need to be bumbed up?
+ * No need to recalculate the cdclk state if
+ * the min cdclk for the pipe doesn't increase.
*
- * Note: we obviously need to be called before the new
- * cdclk frequency is calculated so state->cdclk.logical
- * hasn't been populated yet. Hence we look at the old
- * cdclk state under dev_priv->cdclk.logical. This is
- * safe as long we hold at least one crtc mutex (which
- * must be true since we have crtc_state).
+ * Ie. we only ever increase the cdclk due to plane
+ * requirements. This can reduce back and forth
+ * display blinking due to constant cdclk changes.
*/
- if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
- DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
- plane->base.base.id, plane->base.name,
- crtc_state->min_cdclk[plane->id],
- cdclk_state->logical.cdclk);
- return true;
- }
+ if (new_crtc_state->min_cdclk[plane->id] <=
+ cdclk_state->min_cdclk[crtc->pipe])
+ return 0;
+
+ DRM_DEBUG_KMS("[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
+ plane->base.base.id, plane->base.name,
+ new_crtc_state->min_cdclk[plane->id],
+ crtc->base.base.id, crtc->base.name,
+ cdclk_state->min_cdclk[crtc->pipe]);
+ *need_cdclk_calc = true;
- return false;
+ return 0;
}
static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 5cedafdddb55..2bcf15e34728 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *plane_state);
-bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
- struct intel_plane *plane);
+int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane,
+ bool *need_cdclk_calc);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 12626fd94d29..9debac75eaec 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -30,6 +30,7 @@
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_audio.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_lpe_audio.h"
@@ -800,6 +801,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *cdclk_state;
+ struct intel_crtc *crtc;
+ int ret;
+
+ /* need to hold at least one crtc lock for the global state */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
+ if (ret)
+ return ret;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ cdclk_state->force_min_cdclk_changed = true;
+ cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
+
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
+ if (ret)
+ return ret;
+
+ return drm_atomic_commit(&state->base);
+}
+
static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
bool enable)
{
@@ -815,15 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
state->acquire_ctx = &ctx;
retry:
- to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
- to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
- enable ? 2 * 96000 : 0;
-
- /* Protects dev_priv->cdclk.force_min_cdclk */
- ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
- if (!ret)
- ret = drm_atomic_commit(state);
-
+ ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
if (ret == -EDEADLK) {
drm_atomic_state_clear(state);
drm_modeset_backoff(&ctx);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3b7932ae2a77..e14bda2bec71 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1807,37 +1807,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
a->voltage_level != b->voltage_level;
}
-/**
- * intel_cdclk_clear_state - clear the cdclk state
- * @state: atomic state
- *
- * Clear the cdclk state for ww_mutex backoff.
- */
-void intel_cdclk_clear_state(struct intel_atomic_state *state)
-{
- memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
- state->cdclk_state.pipe = INVALID_PIPE;
-}
-
-/**
- * intel_cdclk_swap_state - make atomic CDCLK configuration effective
- * @state: atomic state
- *
- * This is the CDCLK version of drm_atomic_helper_swap_state() since the
- * helper does not handle driver-specific global state.
- *
- * Similarly to the atomic helpers this function does a complete swap,
- * i.e. it also puts the old state into @state. This is used by the commit
- * code to determine how CDCLK has changed (for instance did it increase or
- * decrease).
- */
-void intel_cdclk_swap_state(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-
- swap(state->cdclk_state, dev_priv->cdclk_state);
-}
-
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context)
{
@@ -1888,14 +1857,22 @@ void
intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- /* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
- const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state =
+ intel_atomic_get_old_cdclk_state(state);
+ const struct intel_cdclk_state *new_cdclk_state =
+ intel_atomic_get_new_cdclk_state(state);
enum pipe pipe = new_cdclk_state->pipe;
+ if (!intel_cdclk_changed(&old_cdclk_state->actual,
+ &new_cdclk_state->actual))
+ return;
+
if (pipe == INVALID_PIPE ||
- old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
+ old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
+ WARN_ON(!new_cdclk_state->base.changed);
+
intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
+ }
}
/**
@@ -1909,14 +1886,22 @@ void
intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- /* called after intel_cdclk_swap_state()! */
- const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
- const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state =
+ intel_atomic_get_old_cdclk_state(state);
+ const struct intel_cdclk_state *new_cdclk_state =
+ intel_atomic_get_new_cdclk_state(state);
enum pipe pipe = new_cdclk_state->pipe;
+ if (!intel_cdclk_changed(&old_cdclk_state->actual,
+ &new_cdclk_state->actual))
+ return;
+
if (pipe != INVALID_PIPE &&
- old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
+ old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
+ WARN_ON(!new_cdclk_state->base.changed);
+
intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
+ }
}
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
@@ -2042,10 +2027,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
-static int intel_compute_min_cdclk(struct intel_atomic_state *state)
+static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
@@ -2063,7 +2048,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
cdclk_state->min_cdclk[i] = min_cdclk;
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
if (ret)
return ret;
}
@@ -2088,10 +2073,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
* future platforms this code will need to be
* adjusted.
*/
-static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
+static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
u8 min_voltage_level;
@@ -2111,7 +2096,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
cdclk_state->min_voltage_level[i] = min_voltage_level;
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&cdclk_state->base);
if (ret)
return ret;
}
@@ -2124,13 +2109,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
return min_voltage_level;
}
-static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, cdclk;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
@@ -2153,12 +2138,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
+ struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
@@ -2185,10 +2170,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int skl_dpll0_vco(struct intel_atomic_state *state)
+static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int vco, i;
@@ -2222,16 +2207,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
return vco;
}
-static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
+ struct intel_atomic_state *state = cdclk_state->base.state;
int min_cdclk, cdclk, vco;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
- vco = skl_dpll0_vco(state);
+ vco = skl_dpll0_vco(cdclk_state);
/*
* FIXME should also account for plane ratio
@@ -2258,17 +2243,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
+ struct intel_atomic_state *state = cdclk_state->base.state;
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
int min_cdclk, min_voltage_level, cdclk, vco;
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
- min_voltage_level = bxt_compute_min_voltage_level(state);
+ min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
if (min_voltage_level < 0)
return min_voltage_level;
@@ -2335,7 +2320,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
return 0;
}
-static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
+static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
int min_cdclk;
@@ -2344,54 +2329,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
* check that the required minimum frequency doesn't exceed
* the actual cdclk frequency.
*/
- min_cdclk = intel_compute_min_cdclk(state);
+ min_cdclk = intel_compute_min_cdclk(cdclk_state);
if (min_cdclk < 0)
return min_cdclk;
return 0;
}
+static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
+ if (!cdclk_state)
+ return NULL;
+
+ cdclk_state->force_min_cdclk_changed = false;
+ cdclk_state->pipe = INVALID_PIPE;
+
+ return &cdclk_state->base;
+}
+
+static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_cdclk_funcs = {
+ .atomic_duplicate_state = intel_cdclk_duplicate_state,
+ .atomic_destroy_state = intel_cdclk_destroy_state,
+};
+
+struct intel_cdclk_state *
+intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *cdclk_state;
+
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ if (IS_ERR(cdclk_state))
+ return ERR_CAST(cdclk_state);
+
+ return to_intel_cdclk_state(cdclk_state);
+}
+
+int intel_cdclk_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
+ if (!cdclk_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ &cdclk_state->base, &intel_cdclk_funcs);
+
+ return 0;
+}
+
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
- struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
+ const struct intel_cdclk_state *old_cdclk_state;
+ struct intel_cdclk_state *new_cdclk_state;
enum pipe pipe;
int ret;
- memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
- sizeof(new_cdclk_state->min_cdclk));
- memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
- sizeof(new_cdclk_state->min_voltage_level));
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
- /* keep the current setting */
- if (!new_cdclk_state->force_min_cdclk_changed)
- new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
+ old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
- new_cdclk_state->logical = old_cdclk_state->logical;
- new_cdclk_state->actual = old_cdclk_state->actual;
-
- ret = dev_priv->display.modeset_calc_cdclk(state);
+ ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
if (ret)
return ret;
- /*
- * Writes to dev_priv->cdclk.{actual,logical} must protected
- * by holding all the crtc mutexes even if we don't end up
- * touching the hardware
- */
if (intel_cdclk_changed(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
/*
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
*/
- ret = _intel_atomic_serialize_global_state(state);
+ ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
if (ret)
return ret;
} else if (intel_cdclk_changed(&old_cdclk_state->logical,
&new_cdclk_state->logical)) {
- ret = _intel_atomic_lock_global_state(state);
+ ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
if (ret)
return ret;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 4b965db07720..195fca70bfcb 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -8,11 +8,12 @@
#include <linux/types.h>
+#include "i915_drv.h"
#include "intel_display.h"
+#include "intel_global_state.h"
struct drm_i915_private;
struct intel_atomic_state;
-struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_cdclk_vals {
@@ -22,6 +23,35 @@ struct intel_cdclk_vals {
u8 ratio;
};
+struct intel_cdclk_state {
+ struct intel_global_state base;
+
+ /*
+ * Logical configuration of cdclk (used for all scaling,
+ * watermark, etc. calculations and checks). This is
+ * computed as if all enabled crtcs were active.
+ */
+ struct intel_cdclk_config logical;
+
+ /*
+ * Actual configuration of cdclk, can be different from the
+ * logical configuration only when all crtc's are DPMS off.
+ */
+ struct intel_cdclk_config actual;
+
+ /* minimum acceptable cdclk for each pipe */
+ int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
+
+ /* pipe to which cd2x update is synchronized */
+ enum pipe pipe;
+
+ /* forced minimum cdclk for glk+ audio w/a */
+ int force_min_cdclk;
+ bool force_min_cdclk_changed;
+};
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
void intel_cdclk_init_hw(struct drm_i915_private *i915);
void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
@@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
-void intel_cdclk_clear_state(struct intel_atomic_state *state);
-void intel_cdclk_swap_state(struct intel_atomic_state *state);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
+struct intel_cdclk_state *
+intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
+
+#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
+#define intel_atomic_get_old_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+#define intel_atomic_get_new_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+
+int intel_cdclk_init(struct drm_i915_private *dev_priv);
+
#endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dc767efffd9a..dca100546be8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7482,7 +7482,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum intel_display_power_domain domain;
@@ -7780,17 +7780,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
return true;
}
-static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
+static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
to_i915(crtc_state->uapi.crtc->dev);
- struct intel_atomic_state *intel_state =
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
- const struct intel_cdclk_state *cdclk_state =
- &intel_state->cdclk_state;
+
+ crtc_state->ips_enabled = false;
if (!hsw_crtc_state_ips_capable(crtc_state))
- return false;
+ return 0;
/*
* When IPS gets enabled, the pipe CRC changes. Since IPS gets
@@ -7799,18 +7799,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
* completely disable it.
*/
if (crtc_state->crc_enabled)
- return false;
+ return 0;
/* IPS should be fine as long as at least one plane is enabled. */
if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
- return false;
+ return 0;
- /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (IS_BROADWELL(dev_priv) &&
- crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
- return false;
+ if (IS_BROADWELL(dev_priv)) {
+ const struct intel_cdclk_state *cdclk_state;
- return true;
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+ if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+ return 0;
+ }
+
+ crtc_state->ips_enabled = true;
+
+ return 0;
}
static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
@@ -12543,14 +12552,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
adjusted_mode->crtc_clock);
}
-static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_cdclk_state *cdclk_state)
{
- const struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- const struct intel_cdclk_state *cdclk_state =
- &state->cdclk_state;
if (!crtc_state->hw.enable)
return 0;
@@ -12580,6 +12586,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
return linetime_wm;
}
+static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_cdclk_state *cdclk_state;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ crtc_state->linetime = skl_linetime_wm(crtc_state);
+ else
+ crtc_state->linetime = hsw_linetime_wm(crtc_state);
+
+ if (!hsw_crtc_supports_ips(crtc))
+ return 0;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
+ cdclk_state);
+
+ return 0;
+}
+
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -12615,7 +12647,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- ret = 0;
if (dev_priv->display.compute_pipe_wm) {
ret = dev_priv->display.compute_pipe_wm(crtc_state);
if (ret) {
@@ -12646,20 +12677,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (!ret)
ret = intel_atomic_setup_scalers(dev_priv, crtc,
crtc_state);
+ if (ret)
+ return ret;
}
- if (HAS_IPS(dev_priv))
- crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
+ if (HAS_IPS(dev_priv)) {
+ ret = hsw_compute_ips_config(crtc_state);
+ if (ret)
+ return ret;
+ }
+
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ ret = hsw_compute_linetime_wm(state, crtc);
+ if (ret)
+ return ret;
- if (INTEL_GEN(dev_priv) >= 9) {
- crtc_state->linetime = skl_linetime_wm(crtc_state);
- } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
- crtc_state->linetime = hsw_linetime_wm(crtc_state);
- if (hsw_crtc_supports_ips(crtc))
- crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
}
- return ret;
+ return 0;
}
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
@@ -14478,7 +14514,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
}
static int intel_atomic_check_planes(struct intel_atomic_state *state,
- bool *need_modeset)
+ bool *need_cdclk_calc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
@@ -14532,8 +14568,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
* affected planes are part of the state. We can now
* compute the minimum cdclk for each plane.
*/
- for_each_new_intel_plane_in_state(state, plane, plane_state, i)
- *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -14654,6 +14693,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_atomic_state *state = to_intel_atomic_state(_state);
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_cdclk_state *new_cdclk_state;
struct intel_crtc *crtc;
int ret, i;
bool any_ms = false;
@@ -14766,18 +14806,18 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- any_ms |= state->cdclk_state.force_min_cdclk_changed;
-
ret = intel_atomic_check_planes(state, &any_ms);
if (ret)
goto fail;
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
+ any_ms = true;
+
if (any_ms) {
ret = intel_modeset_checks(state);
if (ret)
goto fail;
- } else {
- state->cdclk_state.logical = dev_priv->cdclk_state.logical;
}
ret = intel_atomic_check_crtcs(state);
@@ -15676,8 +15716,6 @@ static int intel_atomic_commit(struct drm_device *dev,
assert_global_state_locked(dev_priv);
dev_priv->active_pipes = state->active_pipes;
-
- intel_cdclk_swap_state(state);
}
drm_atomic_state_get(&state->base);
@@ -17356,7 +17394,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
struct intel_cdclk_state *cdclk_state =
- &i915->cdclk_state;
+ to_intel_cdclk_state(i915->cdclk.obj.state);
intel_update_cdclk(i915);
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
@@ -17587,6 +17625,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_mode_config_init(i915);
+ ret = intel_cdclk_init(i915);
+ if (ret)
+ return ret;
+
ret = intel_bw_init(i915);
if (ret)
return ret;
@@ -18071,6 +18113,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
static void intel_modeset_readout_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_cdclk_state *cdclk_state =
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -18190,8 +18234,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
- struct intel_cdclk_state *cdclk_state =
- &dev_priv->cdclk_state;
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 628c4a56a9e9..524b6d5235ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -465,8 +465,6 @@ struct intel_atomic_state {
struct __intel_global_objs_state *global_objs;
int num_global_objs;
- struct intel_cdclk_state cdclk_state;
-
bool dpll_set, modeset;
/*
@@ -493,7 +491,6 @@ struct intel_atomic_state {
/*
* active_pipes
- * cdclk_state
*/
bool global_state_changed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63cda89a4e62..2e6b149478c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -65,7 +65,6 @@
#include "i915_utils.h"
#include "display/intel_bios.h"
-#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
@@ -258,7 +257,8 @@ struct intel_connector;
struct intel_encoder;
struct intel_atomic_state;
struct intel_cdclk_config;
-struct intel_crtc_state;
+struct intel_cdclk_state;
+struct intel_cdclk_vals;
struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
@@ -282,7 +282,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
- int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
+ int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -891,33 +891,6 @@ struct i915_selftest_stash {
atomic_t counter;
};
-struct intel_cdclk_state {
- /*
- * Logical configuration of cdclk (used for all scaling,
- * watermark, etc. calculations and checks). This is
- * computed as if all enabled crtcs were active.
- */
- struct intel_cdclk_config logical;
-
- /*
- * Actual configuration of cdclk, can be different from the
- * logical configuration only when all crtc's are DPMS off.
- */
- struct intel_cdclk_config actual;
-
- /* minimum acceptable cdclk for each pipe */
- int min_cdclk[I915_MAX_PIPES];
- /* minimum acceptable voltage level for each pipe */
- u8 min_voltage_level[I915_MAX_PIPES];
-
- /* pipe to which cd2x update is synchronized */
- enum pipe pipe;
-
- /* forced minimum cdclk for glk+ audio w/a */
- int force_min_cdclk;
- bool force_min_cdclk_changed;
-};
-
struct drm_i915_private {
struct drm_device drm;
@@ -1034,18 +1007,14 @@ struct drm_i915_private {
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- /*
- * For reading holding any crtc lock is sufficient,
- * for writing must hold all of them.
- */
- struct intel_cdclk_state cdclk_state;
-
struct {
/* The current hardware cdclk configuration */
struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
} cdclk;
/**
@@ -1104,8 +1073,8 @@ struct drm_i915_private {
struct list_head global_obj_list;
/*
- * For reading active_pipes, cdclk_state holding any crtc
- * lock is sufficient, for writing must hold all of them.
+ * For reading active_pipes holding any crtc lock is
+ * sufficient, for writing must hold all of them.
*/
u8 active_pipes;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2)
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (20 preceding siblings ...)
2020-01-21 13:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-01-21 17:58 ` Patchwork
2020-01-21 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-23 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-21 17:58 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework (rev2)
URL : https://patchwork.freedesktop.org/series/72301/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6ee8aa846aab drm/i915: Polish WM_LINETIME register stuff
a5c714cbc1b1 drm/i915: Move linetime wms into the crtc state
3d4bad98ff35 drm/i915: Nuke skl wm.dirty_pipes bitmask
91a2393ccd09 drm/i915: Move more cdclk state handling into the cdclk code
2dc3b77d21ab drm/i915: Collect more cdclk state under the same roof
58762cf832fb drm/i915: s/need_cd2x_updare/can_cd2x_update/
882b4774005d drm/i915: s/cdclk_state/cdclk_config/
-:519: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#519: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:870:
+ cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
total: 0 errors, 0 warnings, 1 checks, 1148 lines checked
7cd74aefdc85 drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
156b0ecd892d drm/i915: Extract intel_cdclk_state
-:541: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#541: FILE: drivers/gpu/drm/i915/display/intel_display.c:17366:
+ cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
total: 0 errors, 0 warnings, 1 checks, 621 lines checked
49fde73eb22f drm/i915: swap() the entire cdclk state
9e2da7c71fec drm/i915: s/init_cdclk/init_cdclk_hw/
131e92e40122 drm/i915: Move intel_atomic_state_free() into intel_atomic.c
91fd07c1cb34 drm/i915: Intrduce better global state handling
-:230: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#230:
new file mode 100644
-:235: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_global_state.c', please use '//' instead
#235: FILE: drivers/gpu/drm/i915/display/intel_global_state.c:1:
+/* SPDX-License-Identifier: MIT */
-:235: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#235: FILE: drivers/gpu/drm/i915/display/intel_global_state.c:1:
+/* SPDX-License-Identifier: MIT */
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:494: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#494: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:31:
+#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:502: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#502: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:39:
+#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
-:510: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#510: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:47:
+#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_global_objs && \
+ ((obj) = (__state)->global_objs[__i].ptr, \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, \
+ (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
+ (__i)++) \
+ for_each_if(obj)
total: 0 errors, 3 warnings, 9 checks, 484 lines checked
82426865c238 drm/i915: Convert bandwidth state to global state
81d4a119f677 drm/i915: Introduce intel_calc_active_pipes()
8b4ed3aff508 drm/i915: Convert cdclk to global state
-:635: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#635: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:74:
+#define intel_atomic_get_old_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:636: WARNING:LONG_LINE: line over 100 characters
#636: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:75:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:637: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#637: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:76:
+#define intel_atomic_get_new_cdclk_state(state) \
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
-:638: WARNING:LONG_LINE: line over 100 characters
#638: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:77:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
total: 0 errors, 2 warnings, 2 checks, 922 lines checked
c3282508b4ed drm/i915: Store active_pipes bitmask in cdclk state
-:164: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#164: FILE: drivers/gpu/drm/i915/display/intel_display.c:18149:
+ dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
total: 0 errors, 0 warnings, 1 checks, 123 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Global state rework (rev2)
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (21 preceding siblings ...)
2020-01-21 17:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2) Patchwork
@ 2020-01-21 18:45 ` Patchwork
2020-01-23 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-21 18:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework (rev2)
URL : https://patchwork.freedesktop.org/series/72301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7786 -> Patchwork_16191
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/index.html
Known issues
------------
Here are the changes found in Patchwork_16191 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-no-display:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#58] / [k.org#198133])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-glk-dsi/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-glk-dsi/igt@i915_module_load@reload-no-display.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [PASS][3] -> [DMESG-FAIL][4] ([i915#770])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-ivb-3770/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-ivb-3770: [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-kbl-soraka: [DMESG-FAIL][7] ([i915#656]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [INCOMPLETE][9] ([CI#80] / [i915#424]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][11] ([i915#770]) -> [DMESG-FAIL][12] ([i915#725])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-hsw-4770r/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][13] ([i915#563]) -> [DMESG-FAIL][14] ([i915#725])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-hsw-4770/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][15] ([IGT#4] / [i915#263]) -> [DMESG-FAIL][16] ([IGT#4] / [i915#263])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-cml-s: [FAIL][17] ([fdo#111764] / [i915#577]) -> [FAIL][18] ([i915#577])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/fi-cml-s/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/fi-cml-s/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#577]: https://gitlab.freedesktop.org/drm/intel/issues/577
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#968]: https://gitlab.freedesktop.org/drm/intel/issues/968
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (45 -> 39)
------------------------------
Additional (4): fi-skl-lmem fi-blb-e6850 fi-skl-6600u fi-elk-e7500
Missing (10): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7786 -> Patchwork_16191
CI-20190529: 20190529
CI_DRM_7786: 72275204176397fc718218335edabb840f520024 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5376: 5cf58d947a02379d2885d6dd4f8bb487cfc3eed2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16191: c3282508b4ed1464aba5645604bf41750f53c96d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c3282508b4ed drm/i915: Store active_pipes bitmask in cdclk state
8b4ed3aff508 drm/i915: Convert cdclk to global state
81d4a119f677 drm/i915: Introduce intel_calc_active_pipes()
82426865c238 drm/i915: Convert bandwidth state to global state
91fd07c1cb34 drm/i915: Intrduce better global state handling
131e92e40122 drm/i915: Move intel_atomic_state_free() into intel_atomic.c
9e2da7c71fec drm/i915: s/init_cdclk/init_cdclk_hw/
49fde73eb22f drm/i915: swap() the entire cdclk state
156b0ecd892d drm/i915: Extract intel_cdclk_state
7cd74aefdc85 drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
882b4774005d drm/i915: s/cdclk_state/cdclk_config/
58762cf832fb drm/i915: s/need_cd2x_updare/can_cd2x_update/
2dc3b77d21ab drm/i915: Collect more cdclk state under the same roof
91a2393ccd09 drm/i915: Move more cdclk state handling into the cdclk code
3d4bad98ff35 drm/i915: Nuke skl wm.dirty_pipes bitmask
a5c714cbc1b1 drm/i915: Move linetime wms into the crtc state
6ee8aa846aab drm/i915: Polish WM_LINETIME register stuff
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
@ 2020-01-22 18:39 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 18:39 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the initial setup of state-
> >{cdclk,min_cdclk[],min_voltage_level[]}
> into intel_modeset_calc_cdclk(), and we'll move the counterparts into
> intel_cdclk_swap_state(). This encapsulates the cdclk state much
> better.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26 +++++++++++++++---
> --
> drivers/gpu/drm/i915/display/intel_display.c | 11 ---------
> 2 files changed, 20 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0ce5926006ca..05f6c6456ddf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1819,6 +1819,14 @@ void intel_cdclk_swap_state(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> + /* FIXME maybe swap() these too */
> + memcpy(dev_priv->min_cdclk, state->min_cdclk,
> + sizeof(state->min_cdclk));
> + memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
> + sizeof(state->min_voltage_level));
> +
> + dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
> +
> swap(state->cdclk.logical, dev_priv->cdclk.logical);
> swap(state->cdclk.actual, dev_priv->cdclk.actual);
> }
> @@ -2033,9 +2041,6 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> int min_cdclk, i;
> enum pipe pipe;
>
> - memcpy(state->min_cdclk, dev_priv->min_cdclk,
> - sizeof(state->min_cdclk));
> -
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
>
> @@ -2082,9 +2087,6 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
> int i;
> enum pipe pipe;
>
> - memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
> - sizeof(state->min_voltage_level));
> -
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
>
> @@ -2339,6 +2341,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> enum pipe pipe;
> int ret;
>
> + memcpy(state->min_cdclk, dev_priv->min_cdclk,
> + sizeof(state->min_cdclk));
> + memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
> + sizeof(state->min_voltage_level));
> +
> + /* keep the current setting */
> + if (!state->cdclk.force_min_cdclk_changed)
> + state->cdclk.force_min_cdclk = dev_priv-
> >cdclk.force_min_cdclk;
> +
> + state->cdclk.logical = dev_priv->cdclk.logical;
> + state->cdclk.actual = dev_priv->cdclk.actual;
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8dcb86c51aaa..930e9256596c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14360,14 +14360,8 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state)
> struct intel_crtc *crtc;
> int ret, i;
>
> - /* keep the current setting */
> - if (!state->cdclk.force_min_cdclk_changed)
> - state->cdclk.force_min_cdclk = dev_priv-
> >cdclk.force_min_cdclk;
> -
> state->modeset = true;
> state->active_pipes = dev_priv->active_pipes;
> - state->cdclk.logical = dev_priv->cdclk.logical;
> - state->cdclk.actual = dev_priv->cdclk.actual;
>
> for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> new_crtc_state, i) {
> @@ -15673,12 +15667,7 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> if (state->global_state_changed) {
> assert_global_state_locked(dev_priv);
>
> - memcpy(dev_priv->min_cdclk, state->min_cdclk,
> - sizeof(state->min_cdclk));
> - memcpy(dev_priv->min_voltage_level, state-
> >min_voltage_level,
> - sizeof(state->min_voltage_level));
> dev_priv->active_pipes = state->active_pipes;
> - dev_priv->cdclk.force_min_cdclk = state-
> >cdclk.force_min_cdclk;
>
> intel_cdclk_swap_state(state);
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
@ 2020-01-22 18:43 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 18:43 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the min_cdclk[] and min_voltage_level[] arrays under the
> rest of the cdclk state. And while at it provide a simple
> helper (intel_cdclk_clear_state()) to clear the state during
> the ww_mutex backoff dance.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 9 ++---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++-----
> --
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
> .../drm/i915/display/intel_display_types.h | 10 +++--
> drivers/gpu/drm/i915/i915_drv.h | 9 +++--
> 6 files changed, 46 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c362eecdd414..1269f63ea006 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -35,6 +35,7 @@
> #include <drm/drm_plane_helper.h>
>
> #include "intel_atomic.h"
> +#include "intel_cdclk.h"
> #include "intel_display_types.h"
> #include "intel_hdcp.h"
> #include "intel_psr.h"
> @@ -497,15 +498,13 @@ intel_atomic_state_alloc(struct drm_device
> *dev)
> void intel_atomic_state_clear(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> +
> drm_atomic_state_default_clear(&state->base);
> +
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> state->active_pipes = 0;
> - memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
> - memset(&state->min_voltage_level, 0, sizeof(state-
> >min_voltage_level));
> - memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
> - memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
> - state->cdclk.pipe = INVALID_PIPE;
> + intel_cdclk_clear_state(state);
> }
>
> struct intel_crtc_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 05f6c6456ddf..f7f886dcd6ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1803,6 +1803,18 @@ static bool intel_cdclk_changed(const struct
> intel_cdclk_state *a,
> a->voltage_level != b->voltage_level;
> }
>
> +/**
> + * intel_cdclk_clear_state - clear the cdclk state
> + * @state: atomic state
> + *
> + * Clear the cdclk state for ww_mutex backoff.
> + */
> +void intel_cdclk_clear_state(struct intel_atomic_state *state)
> +{
> + memset(&state->cdclk, 0, sizeof(state->cdclk));
> + state->cdclk.pipe = INVALID_PIPE;
> +}
> +
> /**
> * intel_cdclk_swap_state - make atomic CDCLK configuration
> effective
> * @state: atomic state
> @@ -1820,10 +1832,10 @@ void intel_cdclk_swap_state(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> /* FIXME maybe swap() these too */
> - memcpy(dev_priv->min_cdclk, state->min_cdclk,
> - sizeof(state->min_cdclk));
> - memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
> - sizeof(state->min_voltage_level));
> + memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk,
> + sizeof(state->cdclk.min_cdclk));
> + memcpy(dev_priv->cdclk.min_voltage_level, state-
> >cdclk.min_voltage_level,
> + sizeof(state->cdclk.min_voltage_level));
>
> dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
>
> @@ -2048,10 +2060,10 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> - if (state->min_cdclk[i] == min_cdclk)
> + if (state->cdclk.min_cdclk[i] == min_cdclk)
> continue;
>
> - state->min_cdclk[i] = min_cdclk;
> + state->cdclk.min_cdclk[i] = min_cdclk;
>
> ret = intel_atomic_lock_global_state(state);
> if (ret)
> @@ -2060,7 +2072,7 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
>
> min_cdclk = state->cdclk.force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> - min_cdclk = max(state->min_cdclk[pipe], min_cdclk);
> + min_cdclk = max(state->cdclk.min_cdclk[pipe],
> min_cdclk);
>
> return min_cdclk;
> }
> @@ -2095,10 +2107,10 @@ static int
> bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> else
> min_voltage_level = 0;
>
> - if (state->min_voltage_level[i] == min_voltage_level)
> + if (state->cdclk.min_voltage_level[i] ==
> min_voltage_level)
> continue;
>
> - state->min_voltage_level[i] = min_voltage_level;
> + state->cdclk.min_voltage_level[i] = min_voltage_level;
>
> ret = intel_atomic_lock_global_state(state);
> if (ret)
> @@ -2107,7 +2119,7 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
>
> min_voltage_level = 0;
> for_each_pipe(dev_priv, pipe)
> - min_voltage_level = max(state->min_voltage_level[pipe],
> + min_voltage_level = max(state-
> >cdclk.min_voltage_level[pipe],
> min_voltage_level);
>
> return min_voltage_level;
> @@ -2341,10 +2353,10 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> enum pipe pipe;
> int ret;
>
> - memcpy(state->min_cdclk, dev_priv->min_cdclk,
> - sizeof(state->min_cdclk));
> - memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
> - sizeof(state->min_voltage_level));
> + memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk,
> + sizeof(state->cdclk.min_cdclk));
> + memcpy(state->cdclk.min_voltage_level, dev_priv-
> >cdclk.min_voltage_level,
> + sizeof(state->cdclk.min_voltage_level));
>
> /* keep the current setting */
> if (!state->cdclk.force_min_cdclk_changed)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index cf71394cc79c..3f3773c582ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -31,6 +31,7 @@ void intel_update_cdclk(struct drm_i915_private
> *dev_priv);
> void intel_update_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
> const struct intel_cdclk_state *b);
> +void intel_cdclk_clear_state(struct intel_atomic_state *state);
> void intel_cdclk_swap_state(struct intel_atomic_state *state);
> void
> intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 930e9256596c..f3f9fe94ed41 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7547,8 +7547,8 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
> crtc->enabled_power_domains = 0;
>
> dev_priv->active_pipes &= ~BIT(pipe);
> - dev_priv->min_cdclk[pipe] = 0;
> - dev_priv->min_voltage_level[pipe] = 0;
> + dev_priv->cdclk.min_cdclk[pipe] = 0;
> + dev_priv->cdclk.min_voltage_level[pipe] = 0;
>
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> @@ -18251,8 +18251,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> min_cdclk = 0;
> }
>
> - dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
> - dev_priv->min_voltage_level[crtc->pipe] =
> + dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk;
> + dev_priv->cdclk.min_voltage_level[crtc->pipe] =
> crtc_state->min_voltage_level;
>
> intel_bw_crtc_update(bw_state, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2d8491590501..a6b95a8ab323 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -477,6 +477,12 @@ struct intel_atomic_state {
>
> int force_min_cdclk;
> bool force_min_cdclk_changed;
> +
> + /* minimum acceptable cdclk for each pipe */
> + int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage level for each pipe */
> + u8 min_voltage_level[I915_MAX_PIPES];
> +
> /* pipe to which cd2x update is synchronized */
> enum pipe pipe;
> } cdclk;
> @@ -494,10 +500,6 @@ struct intel_atomic_state {
> u8 active_pipe_changes;
>
> u8 active_pipes;
> - /* minimum acceptable cdclk for each pipe */
> - int min_cdclk[I915_MAX_PIPES];
> - /* minimum acceptable voltage level for each pipe */
> - u8 min_voltage_level[I915_MAX_PIPES];
>
> struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index a7f6275a79e6..650f42bd9cfb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1027,6 +1027,11 @@ struct drm_i915_private {
> const struct intel_cdclk_vals *table;
>
> int force_min_cdclk;
> +
> + /* minimum acceptable cdclk for each pipe */
> + int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage level for each pipe */
> + u8 min_voltage_level[I915_MAX_PIPES];
> } cdclk;
>
> /**
> @@ -1087,10 +1092,6 @@ struct drm_i915_private {
> * any crtc lock is sufficient, for writing must hold all of
> them.
> */
> u8 active_pipes;
> - /* minimum acceptable cdclk for each pipe */
> - int min_cdclk[I915_MAX_PIPES];
> - /* minimum acceptable voltage level for each pipe */
> - u8 min_voltage_level[I915_MAX_PIPES];
>
> int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
>
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
@ 2020-01-22 18:51 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 18:51 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the same structure to store the cdclk state in both
> intel_atomic_state and dev_priv. First step towards proper
> old vs. new cdclk states.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 168 ++++++++++----
> ----
> drivers/gpu/drm/i915/display/intel_display.c | 29 ++-
> .../drm/i915/display/intel_display_types.h | 30 +---
> drivers/gpu/drm/i915/i915_drv.h | 51 ++++--
> 6 files changed, 151 insertions(+), 137 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 3e97af682b1b..563caec1d201 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -159,6 +159,8 @@ bool intel_plane_calc_min_cdclk(struct
> intel_atomic_state *state,
> struct intel_plane *plane)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + const struct intel_cdclk_state *cdclk_state =
> + &dev_priv->cdclk_state;
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
> @@ -182,11 +184,11 @@ bool intel_plane_calc_min_cdclk(struct
> intel_atomic_state *state,
> * safe as long we hold at least one crtc mutex (which
> * must be true since we have crtc_state).
> */
> - if (crtc_state->min_cdclk[plane->id] > dev_priv-
> >cdclk.logical.cdclk) {
> + if (crtc_state->min_cdclk[plane->id] > cdclk_state-
> >logical.cdclk) {
> DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) >
> logical cdclk (%d kHz)\n",
> plane->base.base.id, plane->base.name,
> crtc_state->min_cdclk[plane->id],
> - dev_priv->cdclk.logical.cdclk);
> + cdclk_state->logical.cdclk);
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index b18040793d9e..32e722128638 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -815,8 +815,8 @@ static void glk_force_audio_cdclk(struct
> drm_i915_private *dev_priv,
> state->acquire_ctx = &ctx;
>
> retry:
> - to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed =
> true;
> - to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + to_intel_atomic_state(state)-
> >cdclk_state.force_min_cdclk_changed = true;
> + to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
> enable ? 2 * 96000 : 0;
>
> /* Protects dev_priv->cdclk.force_min_cdclk */
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a2b1401dcfbb..f8e70a668b74 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1815,8 +1815,8 @@ static bool intel_cdclk_changed(const struct
> intel_cdclk_config *a,
> */
> void intel_cdclk_clear_state(struct intel_atomic_state *state)
> {
> - memset(&state->cdclk, 0, sizeof(state->cdclk));
> - state->cdclk.pipe = INVALID_PIPE;
> + memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
> + state->cdclk_state.pipe = INVALID_PIPE;
> }
>
> /**
> @@ -1836,15 +1836,18 @@ void intel_cdclk_swap_state(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> /* FIXME maybe swap() these too */
> - memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk,
> - sizeof(state->cdclk.min_cdclk));
> - memcpy(dev_priv->cdclk.min_voltage_level, state-
> >cdclk.min_voltage_level,
> - sizeof(state->cdclk.min_voltage_level));
> + memcpy(dev_priv->cdclk_state.min_cdclk,
> + state->cdclk_state.min_cdclk,
> + sizeof(state->cdclk_state.min_cdclk));
> + memcpy(dev_priv->cdclk_state.min_voltage_level,
> + state->cdclk_state.min_voltage_level,
> + sizeof(state->cdclk_state.min_voltage_level));
>
> - dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
> + dev_priv->cdclk_state.force_min_cdclk =
> + state->cdclk_state.force_min_cdclk;
>
> - swap(state->cdclk.logical, dev_priv->cdclk.logical);
> - swap(state->cdclk.actual, dev_priv->cdclk.actual);
> + swap(state->cdclk_state.logical, dev_priv-
> >cdclk_state.logical);
> + swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual);
> }
>
> void intel_dump_cdclk_config(const struct intel_cdclk_config
> *cdclk_config,
> @@ -1898,12 +1901,13 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> /* called after intel_cdclk_swap_state()! */
> - const struct intel_cdclk_config *old_state = &state-
> >cdclk.actual;
> - const struct intel_cdclk_config *new_state = &dev_priv-
> >cdclk.actual;
> - enum pipe pipe = state->cdclk.pipe;
> + const struct intel_cdclk_state *old_cdclk_state = &state-
> >cdclk_state;
> + const struct intel_cdclk_state *new_cdclk_state = &dev_priv-
> >cdclk_state;
> + enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
>
> - if (pipe == INVALID_PIPE || old_state->cdclk <= new_state-
> >cdclk)
> - intel_set_cdclk(dev_priv, new_state, pipe);
> + if (pipe == INVALID_PIPE ||
> + old_cdclk_state->actual.cdclk <= new_cdclk_state-
> >actual.cdclk)
> + intel_set_cdclk(dev_priv, &new_cdclk_state->actual,
> pipe);
> }
>
> /**
> @@ -1918,12 +1922,13 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> /* called after intel_cdclk_swap_state()! */
> - const struct intel_cdclk_config *old_state = &state-
> >cdclk.actual;
> - const struct intel_cdclk_config *new_state = &dev_priv-
> >cdclk.actual;
> - enum pipe pipe = state->cdclk.pipe;
> + const struct intel_cdclk_state *old_cdclk_state = &state-
> >cdclk_state;
> + const struct intel_cdclk_state *new_cdclk_state = &dev_priv-
> >cdclk_state;
> + enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
>
> - if (pipe != INVALID_PIPE && old_state->cdclk > new_state-
> >cdclk)
> - intel_set_cdclk(dev_priv, new_state, pipe);
> + if (pipe != INVALID_PIPE &&
> + old_cdclk_state->actual.cdclk > new_cdclk_state-
> >actual.cdclk)
> + intel_set_cdclk(dev_priv, &new_cdclk_state->actual,
> pipe);
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state
> *crtc_state)
> @@ -2052,6 +2057,7 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> @@ -2064,19 +2070,19 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> - if (state->cdclk.min_cdclk[i] == min_cdclk)
> + if (cdclk_state->min_cdclk[i] == min_cdclk)
> continue;
>
> - state->cdclk.min_cdclk[i] = min_cdclk;
> + cdclk_state->min_cdclk[i] = min_cdclk;
>
> ret = intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
>
> - min_cdclk = state->cdclk.force_min_cdclk;
> + min_cdclk = cdclk_state->force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> - min_cdclk = max(state->cdclk.min_cdclk[pipe],
> min_cdclk);
> + min_cdclk = max(cdclk_state->min_cdclk[pipe],
> min_cdclk);
>
> return min_cdclk;
> }
> @@ -2097,6 +2103,7 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> static int bxt_compute_min_voltage_level(struct intel_atomic_state
> *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> u8 min_voltage_level;
> @@ -2111,10 +2118,10 @@ static int
> bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> else
> min_voltage_level = 0;
>
> - if (state->cdclk.min_voltage_level[i] ==
> min_voltage_level)
> + if (cdclk_state->min_voltage_level[i] ==
> min_voltage_level)
> continue;
>
> - state->cdclk.min_voltage_level[i] = min_voltage_level;
> + cdclk_state->min_voltage_level[i] = min_voltage_level;
>
> ret = intel_atomic_lock_global_state(state);
> if (ret)
> @@ -2123,7 +2130,7 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
>
> min_voltage_level = 0;
> for_each_pipe(dev_priv, pipe)
> - min_voltage_level = max(state-
> >cdclk.min_voltage_level[pipe],
> + min_voltage_level = max(cdclk_state-
> >min_voltage_level[pipe],
> min_voltage_level);
>
> return min_voltage_level;
> @@ -2132,6 +2139,7 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
> static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, cdclk;
>
> min_cdclk = intel_compute_min_cdclk(state);
> @@ -2140,18 +2148,18 @@ static int vlv_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
>
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> + cdclk_state->logical.cdclk = cdclk;
> + cdclk_state->logical.voltage_level =
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> if (!state->active_pipes) {
> - cdclk = vlv_calc_cdclk(dev_priv, state-
> >cdclk.force_min_cdclk);
> + cdclk = vlv_calc_cdclk(dev_priv, cdclk_state-
> >force_min_cdclk);
>
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> + cdclk_state->actual.cdclk = cdclk;
> + cdclk_state->actual.voltage_level =
> vlv_calc_voltage_level(dev_priv, cdclk);
> } else {
> - state->cdclk.actual = state->cdclk.logical;
> + cdclk_state->actual = cdclk_state->logical;
> }
>
> return 0;
> @@ -2159,6 +2167,7 @@ static int vlv_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, cdclk;
>
> min_cdclk = intel_compute_min_cdclk(state);
> @@ -2171,18 +2180,18 @@ static int bdw_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> */
> cdclk = bdw_calc_cdclk(min_cdclk);
>
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> + cdclk_state->logical.cdclk = cdclk;
> + cdclk_state->logical.voltage_level =
> bdw_calc_voltage_level(cdclk);
>
> if (!state->active_pipes) {
> - cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
> + cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
>
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> + cdclk_state->actual.cdclk = cdclk;
> + cdclk_state->actual.voltage_level =
> bdw_calc_voltage_level(cdclk);
> } else {
> - state->cdclk.actual = state->cdclk.logical;
> + cdclk_state->actual = cdclk_state->logical;
> }
>
> return 0;
> @@ -2191,11 +2200,12 @@ static int bdw_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> static int skl_dpll0_vco(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int vco, i;
>
> - vco = state->cdclk.logical.vco;
> + vco = cdclk_state->logical.vco;
> if (!vco)
> vco = dev_priv->skl_preferred_vco_freq;
>
> @@ -2226,6 +2236,7 @@ static int skl_dpll0_vco(struct
> intel_atomic_state *state)
>
> static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, cdclk, vco;
>
> min_cdclk = intel_compute_min_cdclk(state);
> @@ -2240,20 +2251,20 @@ static int skl_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> */
> cdclk = skl_calc_cdclk(min_cdclk, vco);
>
> - state->cdclk.logical.vco = vco;
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> + cdclk_state->logical.vco = vco;
> + cdclk_state->logical.cdclk = cdclk;
> + cdclk_state->logical.voltage_level =
> skl_calc_voltage_level(cdclk);
>
> if (!state->active_pipes) {
> - cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk,
> vco);
> + cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk,
> vco);
>
> - state->cdclk.actual.vco = vco;
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> + cdclk_state->actual.vco = vco;
> + cdclk_state->actual.cdclk = cdclk;
> + cdclk_state->actual.voltage_level =
> skl_calc_voltage_level(cdclk);
> } else {
> - state->cdclk.actual = state->cdclk.logical;
> + cdclk_state->actual = cdclk_state->logical;
> }
>
> return 0;
> @@ -2262,6 +2273,7 @@ static int skl_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, min_voltage_level, cdclk, vco;
>
> min_cdclk = intel_compute_min_cdclk(state);
> @@ -2275,22 +2287,22 @@ static int bxt_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> - state->cdclk.logical.vco = vco;
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> + cdclk_state->logical.vco = vco;
> + cdclk_state->logical.cdclk = cdclk;
> + cdclk_state->logical.voltage_level =
> max_t(int, min_voltage_level,
> dev_priv->display.calc_voltage_level(cdclk));
>
> if (!state->active_pipes) {
> - cdclk = bxt_calc_cdclk(dev_priv, state-
> >cdclk.force_min_cdclk);
> + cdclk = bxt_calc_cdclk(dev_priv, cdclk_state-
> >force_min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> - state->cdclk.actual.vco = vco;
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> + cdclk_state->actual.vco = vco;
> + cdclk_state->actual.cdclk = cdclk;
> + cdclk_state->actual.voltage_level =
> dev_priv->display.calc_voltage_level(cdclk);
> } else {
> - state->cdclk.actual = state->cdclk.logical;
> + cdclk_state->actual = cdclk_state->logical;
> }
>
> return 0;
> @@ -2354,20 +2366,22 @@ static int fixed_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_cdclk_state *old_cdclk_state = &dev_priv-
> >cdclk_state;
> + struct intel_cdclk_state *new_cdclk_state = &state-
> >cdclk_state;
> enum pipe pipe;
> int ret;
>
> - memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk,
> - sizeof(state->cdclk.min_cdclk));
> - memcpy(state->cdclk.min_voltage_level, dev_priv-
> >cdclk.min_voltage_level,
> - sizeof(state->cdclk.min_voltage_level));
> + memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
> + sizeof(new_cdclk_state->min_cdclk));
> + memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state-
> >min_voltage_level,
> + sizeof(new_cdclk_state->min_voltage_level));
>
> /* keep the current setting */
> - if (!state->cdclk.force_min_cdclk_changed)
> - state->cdclk.force_min_cdclk = dev_priv-
> >cdclk.force_min_cdclk;
> + if (!new_cdclk_state->force_min_cdclk_changed)
> + new_cdclk_state->force_min_cdclk = old_cdclk_state-
> >force_min_cdclk;
>
> - state->cdclk.logical = dev_priv->cdclk.logical;
> - state->cdclk.actual = dev_priv->cdclk.actual;
> + new_cdclk_state->logical = old_cdclk_state->logical;
> + new_cdclk_state->actual = old_cdclk_state->actual;
>
> ret = dev_priv->display.modeset_calc_cdclk(state);
> if (ret)
> @@ -2378,8 +2392,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> * by holding all the crtc mutexes even if we don't end up
> * touching the hardware
> */
> - if (intel_cdclk_changed(&dev_priv->cdclk.actual,
> - &state->cdclk.actual)) {
> + if (intel_cdclk_changed(&old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> /*
> * Also serialize commits across all crtcs
> * if the actual hw needs to be poked.
> @@ -2387,8 +2401,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> ret = intel_atomic_serialize_global_state(state);
> if (ret)
> return ret;
> - } else if (intel_cdclk_changed(&dev_priv->cdclk.logical,
> - &state->cdclk.logical)) {
> + } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> + &new_cdclk_state->logical)) {
> ret = intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> @@ -2398,8 +2412,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> if (is_power_of_2(state->active_pipes) &&
> intel_cdclk_can_cd2x_update(dev_priv,
> - &dev_priv->cdclk.actual,
> - &state->cdclk.actual)) {
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
>
> @@ -2417,28 +2431,28 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> }
>
> if (pipe != INVALID_PIPE) {
> - state->cdclk.pipe = pipe;
> + new_cdclk_state->pipe = pipe;
>
> DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
> pipe_name(pipe));
> - } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
> - &state->cdclk.actual)) {
> + } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> + &new_cdclk_state->actual))
> {
> /* All pipes must be switched off while we change the
> cdclk. */
> ret = intel_modeset_all_pipes(state);
> if (ret)
> return ret;
>
> - state->cdclk.pipe = INVALID_PIPE;
> + new_cdclk_state->pipe = INVALID_PIPE;
>
> DRM_DEBUG_KMS("Modeset required for cdclk change\n");
> }
>
> DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz,
> actual %u kHz\n",
> - state->cdclk.logical.cdclk,
> - state->cdclk.actual.cdclk);
> + new_cdclk_state->logical.cdclk,
> + new_cdclk_state->actual.cdclk);
> DRM_DEBUG_KMS("New voltage level calculated to be logical %u,
> actual %u\n",
> - state->cdclk.logical.voltage_level,
> - state->cdclk.actual.voltage_level);
> + new_cdclk_state->logical.voltage_level,
> + new_cdclk_state->actual.voltage_level);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 25b0eab019cb..63efb8f9c669 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7481,6 +7481,8 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_bw_state *bw_state =
> to_intel_bw_state(dev_priv->bw_obj.state);
> + struct intel_cdclk_state *cdclk_state =
> + &dev_priv->cdclk_state;
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum intel_display_power_domain domain;
> @@ -7547,8 +7549,8 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
> crtc->enabled_power_domains = 0;
>
> dev_priv->active_pipes &= ~BIT(pipe);
> - dev_priv->cdclk.min_cdclk[pipe] = 0;
> - dev_priv->cdclk.min_voltage_level[pipe] = 0;
> + cdclk_state->min_cdclk[pipe] = 0;
> + cdclk_state->min_voltage_level[pipe] = 0;
>
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> @@ -7784,6 +7786,8 @@ static bool hsw_compute_ips_config(struct
> intel_crtc_state *crtc_state)
> to_i915(crtc_state->uapi.crtc->dev);
> struct intel_atomic_state *intel_state =
> to_intel_atomic_state(crtc_state->uapi.state);
> + const struct intel_cdclk_state *cdclk_state =
> + &intel_state->cdclk_state;
>
> if (!hsw_crtc_state_ips_capable(crtc_state))
> return false;
> @@ -7803,7 +7807,7 @@ static bool hsw_compute_ips_config(struct
> intel_crtc_state *crtc_state)
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> if (IS_BROADWELL(dev_priv) &&
> - crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk *
> 95 / 100)
> + crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 /
> 100)
> return false;
>
> return true;
> @@ -12545,12 +12549,14 @@ static u16 hsw_ips_linetime_wm(const struct
> intel_crtc_state *crtc_state)
> to_intel_atomic_state(crtc_state->uapi.state);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> + const struct intel_cdclk_state *cdclk_state =
> + &state->cdclk_state;
>
> if (!crtc_state->hw.enable)
> return 0;
>
> return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> - state->cdclk.logical.cdclk);
> + cdclk_state->logical.cdclk);
> }
>
> static u16 skl_linetime_wm(const struct intel_crtc_state
> *crtc_state)
> @@ -14754,7 +14760,7 @@ static int intel_atomic_check(struct
> drm_device *dev,
> if (ret)
> goto fail;
>
> - any_ms |= state->cdclk.force_min_cdclk_changed;
> + any_ms |= state->cdclk_state.force_min_cdclk_changed;
>
> ret = intel_atomic_check_planes(state, &any_ms);
> if (ret)
> @@ -14765,7 +14771,7 @@ static int intel_atomic_check(struct
> drm_device *dev,
> if (ret)
> goto fail;
> } else {
> - state->cdclk.logical = dev_priv->cdclk.logical;
> + state->cdclk_state.logical = dev_priv-
> >cdclk_state.logical;
> }
>
> ret = intel_atomic_check_crtcs(state);
> @@ -17352,9 +17358,12 @@ void intel_init_display_hooks(struct
> drm_i915_private *dev_priv)
>
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> + struct intel_cdclk_state *cdclk_state =
> + &i915->cdclk_state;
> +
> intel_update_cdclk(i915);
> intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
> - i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> + cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
> }
>
> /*
> @@ -18177,6 +18186,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> for_each_intel_crtc(dev, crtc) {
> struct intel_bw_state *bw_state =
> to_intel_bw_state(dev_priv->bw_obj.state);
> + struct intel_cdclk_state *cdclk_state =
> + &dev_priv->cdclk_state;
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> struct intel_plane *plane;
> @@ -18245,8 +18256,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> min_cdclk = 0;
> }
>
> - dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk;
> - dev_priv->cdclk.min_voltage_level[crtc->pipe] =
> + cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
> + cdclk_state->min_voltage_level[crtc->pipe] =
> crtc_state->min_voltage_level;
>
> intel_bw_crtc_update(bw_state, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 485b26d05e90..b31ed828fa8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -461,31 +461,7 @@ struct intel_atomic_state {
>
> intel_wakeref_t wakeref;
>
> - struct {
> - /*
> - * Logical configuration of cdclk (used for all
> scaling,
> - * watermark, etc. calculations and checks). This is
> - * computed as if all enabled crtcs were active.
> - */
> - struct intel_cdclk_config logical;
> -
> - /*
> - * Actual configuration of cdclk, can be different from
> the
> - * logical configuration only when all crtc's are DPMS
> off.
> - */
> - struct intel_cdclk_config actual;
> -
> - int force_min_cdclk;
> - bool force_min_cdclk_changed;
> -
> - /* minimum acceptable cdclk for each pipe */
> - int min_cdclk[I915_MAX_PIPES];
> - /* minimum acceptable voltage level for each pipe */
> - u8 min_voltage_level[I915_MAX_PIPES];
> -
> - /* pipe to which cd2x update is synchronized */
> - enum pipe pipe;
> - } cdclk;
> + struct intel_cdclk_state cdclk_state;
>
> bool dpll_set, modeset;
>
> @@ -513,9 +489,7 @@ struct intel_atomic_state {
>
> /*
> * active_pipes
> - * min_cdclk[]
> - * min_voltage_level[]
> - * cdclk.*
> + * cdclk_state
> */
> bool global_state_changed;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 49276ce2819f..1787bfdd057f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -65,6 +65,7 @@
> #include "i915_utils.h"
>
> #include "display/intel_bios.h"
> +#include "display/intel_cdclk.h"
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> #include "display/intel_dpll_mgr.h"
> @@ -889,6 +890,33 @@ struct i915_selftest_stash {
> atomic_t counter;
> };
>
> +struct intel_cdclk_state {
> + /*
> + * Logical configuration of cdclk (used for all scaling,
> + * watermark, etc. calculations and checks). This is
> + * computed as if all enabled crtcs were active.
> + */
> + struct intel_cdclk_config logical;
> +
> + /*
> + * Actual configuration of cdclk, can be different from the
> + * logical configuration only when all crtc's are DPMS off.
> + */
> + struct intel_cdclk_config actual;
> +
> + /* minimum acceptable cdclk for each pipe */
> + int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage level for each pipe */
> + u8 min_voltage_level[I915_MAX_PIPES];
> +
> + /* pipe to which cd2x update is synchronized */
> + enum pipe pipe;
> +
> + /* forced minimum cdclk for glk+ audio w/a */
> + int force_min_cdclk;
> + bool force_min_cdclk_changed;
> +};
> +
> struct drm_i915_private {
> struct drm_device drm;
>
> @@ -1009,29 +1037,14 @@ struct drm_i915_private {
> * For reading holding any crtc lock is sufficient,
> * for writing must hold all of them.
> */
> + struct intel_cdclk_state cdclk_state;
> +
> struct {
> - /*
> - * The current logical cdclk configuration.
> - * See intel_atomic_state.cdclk.logical
> - */
> - struct intel_cdclk_config logical;
> - /*
> - * The current actual cdclk configuration.
> - * See intel_atomic_state.cdclk.actual
> - */
> - struct intel_cdclk_config actual;
> /* The current hardware cdclk configuration */
> struct intel_cdclk_config hw;
>
> /* cdclk, divider, and ratio table from bspec */
> const struct intel_cdclk_vals *table;
> -
> - int force_min_cdclk;
> -
> - /* minimum acceptable cdclk for each pipe */
> - int min_cdclk[I915_MAX_PIPES];
> - /* minimum acceptable voltage level for each pipe */
> - u8 min_voltage_level[I915_MAX_PIPES];
> } cdclk;
>
> /**
> @@ -1088,8 +1101,8 @@ struct drm_i915_private {
> struct mutex dpll_lock;
>
> /*
> - * For reading active_pipes, min_cdclk, min_voltage_level
> holding
> - * any crtc lock is sufficient, for writing must hold all of
> them.
> + * For reading active_pipes, cdclk_state holding any crtc
> + * lock is sufficient, for writing must hold all of them.
> */
> u8 active_pipes;
>
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
@ 2020-01-22 18:51 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 18:51 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I want to have a higher level cdclk state object so let's rename
> the current lower level thing to cdclk_config (because I lack
> imagination).
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 426 +++++++++-------
> --
> drivers/gpu/drm/i915/display/intel_cdclk.h | 18 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_power.c | 8 +-
> .../drm/i915/display/intel_display_types.h | 14 +-
> drivers/gpu/drm/i915/i915_drv.h | 20 +-
> 6 files changed, 246 insertions(+), 242 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9d4cf412b65d..2a5491eb8af3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -55,43 +55,43 @@
> */
>
> static void fixed_133mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> }
>
> static void fixed_200mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 200000;
> + cdclk_config->cdclk = 200000;
> }
>
> static void fixed_266mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 266667;
> + cdclk_config->cdclk = 266667;
> }
>
> static void fixed_333mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 333333;
> + cdclk_config->cdclk = 333333;
> }
>
> static void fixed_400mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 400000;
> + cdclk_config->cdclk = 400000;
> }
>
> static void fixed_450mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> - struct intel_cdclk_state
> *cdclk_state)
> + struct intel_cdclk_config
> *cdclk_config)
> {
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> }
>
> static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u16 hpllcc = 0;
> @@ -102,7 +102,7 @@ static void i85x_get_cdclk(struct
> drm_i915_private *dev_priv,
> * FIXME is this the right way to detect 852GM/852GMV?
> */
> if (pdev->revision == 0x1) {
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> return;
> }
>
> @@ -116,24 +116,24 @@ static void i85x_get_cdclk(struct
> drm_i915_private *dev_priv,
> case GC_CLOCK_133_200:
> case GC_CLOCK_133_200_2:
> case GC_CLOCK_100_200:
> - cdclk_state->cdclk = 200000;
> + cdclk_config->cdclk = 200000;
> break;
> case GC_CLOCK_166_250:
> - cdclk_state->cdclk = 250000;
> + cdclk_config->cdclk = 250000;
> break;
> case GC_CLOCK_100_133:
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> break;
> case GC_CLOCK_133_266:
> case GC_CLOCK_133_266_2:
> case GC_CLOCK_166_266:
> - cdclk_state->cdclk = 266667;
> + cdclk_config->cdclk = 266667;
> break;
> }
> }
>
> static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u16 gcfgc = 0;
> @@ -141,23 +141,23 @@ static void i915gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> pci_read_config_word(pdev, GCFGC, &gcfgc);
>
> if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> return;
> }
>
> switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
> case GC_DISPLAY_CLOCK_333_320_MHZ:
> - cdclk_state->cdclk = 333333;
> + cdclk_config->cdclk = 333333;
> break;
> default:
> case GC_DISPLAY_CLOCK_190_200_MHZ:
> - cdclk_state->cdclk = 190000;
> + cdclk_config->cdclk = 190000;
> break;
> }
> }
>
> static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u16 gcfgc = 0;
> @@ -165,17 +165,17 @@ static void i945gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> pci_read_config_word(pdev, GCFGC, &gcfgc);
>
> if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> return;
> }
>
> switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
> case GC_DISPLAY_CLOCK_333_320_MHZ:
> - cdclk_state->cdclk = 320000;
> + cdclk_config->cdclk = 320000;
> break;
> default:
> case GC_DISPLAY_CLOCK_190_200_MHZ:
> - cdclk_state->cdclk = 200000;
> + cdclk_config->cdclk = 200000;
> break;
> }
> }
> @@ -250,7 +250,7 @@ static unsigned int intel_hpll_vco(struct
> drm_i915_private *dev_priv)
> }
>
> static void g33_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
> @@ -261,7 +261,7 @@ static void g33_get_cdclk(struct drm_i915_private
> *dev_priv,
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_state->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(dev_priv);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> @@ -270,7 +270,7 @@ static void g33_get_cdclk(struct drm_i915_private
> *dev_priv,
> if (cdclk_sel >= ARRAY_SIZE(div_3200))
> goto fail;
>
> - switch (cdclk_state->vco) {
> + switch (cdclk_config->vco) {
> case 3200000:
> div_table = div_3200;
> break;
> @@ -287,18 +287,18 @@ static void g33_get_cdclk(struct
> drm_i915_private *dev_priv,
> goto fail;
> }
>
> - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
> - div_table[cdclk_sel]);
> + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
> + div_table[cdclk_sel]);
> return;
>
> fail:
> DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz,
> CFGC=0x%08x\n",
> - cdclk_state->vco, tmp);
> - cdclk_state->cdclk = 190476;
> + cdclk_config->vco, tmp);
> + cdclk_config->cdclk = 190476;
> }
>
> static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u16 gcfgc = 0;
> @@ -307,31 +307,31 @@ static void pnv_get_cdclk(struct
> drm_i915_private *dev_priv,
>
> switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
> case GC_DISPLAY_CLOCK_267_MHZ_PNV:
> - cdclk_state->cdclk = 266667;
> + cdclk_config->cdclk = 266667;
> break;
> case GC_DISPLAY_CLOCK_333_MHZ_PNV:
> - cdclk_state->cdclk = 333333;
> + cdclk_config->cdclk = 333333;
> break;
> case GC_DISPLAY_CLOCK_444_MHZ_PNV:
> - cdclk_state->cdclk = 444444;
> + cdclk_config->cdclk = 444444;
> break;
> case GC_DISPLAY_CLOCK_200_MHZ_PNV:
> - cdclk_state->cdclk = 200000;
> + cdclk_config->cdclk = 200000;
> break;
> default:
> DRM_ERROR("Unknown pnv display core clock 0x%04x\n",
> gcfgc);
> /* fall through */
> case GC_DISPLAY_CLOCK_133_MHZ_PNV:
> - cdclk_state->cdclk = 133333;
> + cdclk_config->cdclk = 133333;
> break;
> case GC_DISPLAY_CLOCK_167_MHZ_PNV:
> - cdclk_state->cdclk = 166667;
> + cdclk_config->cdclk = 166667;
> break;
> }
> }
>
> static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> static const u8 div_3200[] = { 16, 10, 8 };
> @@ -341,7 +341,7 @@ static void i965gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_state->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(dev_priv);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> @@ -350,7 +350,7 @@ static void i965gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> if (cdclk_sel >= ARRAY_SIZE(div_3200))
> goto fail;
>
> - switch (cdclk_state->vco) {
> + switch (cdclk_config->vco) {
> case 3200000:
> div_table = div_3200;
> break;
> @@ -364,62 +364,62 @@ static void i965gm_get_cdclk(struct
> drm_i915_private *dev_priv,
> goto fail;
> }
>
> - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
> - div_table[cdclk_sel]);
> + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
> + div_table[cdclk_sel]);
> return;
>
> fail:
> DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz,
> CFGC=0x%04x\n",
> - cdclk_state->vco, tmp);
> - cdclk_state->cdclk = 200000;
> + cdclk_config->vco, tmp);
> + cdclk_config->cdclk = 200000;
> }
>
> static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_state->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(dev_priv);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> cdclk_sel = (tmp >> 12) & 0x1;
>
> - switch (cdclk_state->vco) {
> + switch (cdclk_config->vco) {
> case 2666667:
> case 4000000:
> case 5333333:
> - cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
> + cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
> break;
> case 3200000:
> - cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
> + cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
> break;
> default:
> DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u,
> CFGC=0x%04x\n",
> - cdclk_state->vco, tmp);
> - cdclk_state->cdclk = 222222;
> + cdclk_config->vco, tmp);
> + cdclk_config->cdclk = 222222;
> break;
> }
> }
>
> static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 lcpll = I915_READ(LCPLL_CTL);
> u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> - cdclk_state->cdclk = 800000;
> + cdclk_config->cdclk = 800000;
> else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> else if (freq == LCPLL_CLK_FREQ_450)
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> else if (IS_HSW_ULT(dev_priv))
> - cdclk_state->cdclk = 337500;
> + cdclk_config->cdclk = 337500;
> else
> - cdclk_state->cdclk = 540000;
> + cdclk_config->cdclk = 540000;
> }
>
> static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int
> min_cdclk)
> @@ -462,17 +462,17 @@ static u8 vlv_calc_voltage_level(struct
> drm_i915_private *dev_priv, int cdclk)
> }
>
> static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 val;
>
> vlv_iosf_sb_get(dev_priv,
> BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
>
> - cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
> - cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
> - CCK_DISPLAY_CLOCK_CONTRO
> L,
> - cdclk_state->vco);
> + cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
> + cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
> + CCK_DISPLAY_CLOCK_CONTR
> OL,
> + cdclk_config->vco);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
>
> @@ -480,10 +480,10 @@ static void vlv_get_cdclk(struct
> drm_i915_private *dev_priv,
> BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
>
> if (IS_VALLEYVIEW(dev_priv))
> - cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK)
> >>
> + cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK)
> >>
> DSPFREQGUAR_SHIFT;
> else
> - cdclk_state->voltage_level = (val &
> DSPFREQGUAR_MASK_CHV) >>
> + cdclk_config->voltage_level = (val &
> DSPFREQGUAR_MASK_CHV) >>
> DSPFREQGUAR_SHIFT_CHV;
> }
>
> @@ -524,11 +524,11 @@ static void vlv_program_pfi_credits(struct
> drm_i915_private *dev_priv)
> }
>
> static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - int cdclk = cdclk_state->cdclk;
> - u32 val, cmd = cdclk_state->voltage_level;
> + int cdclk = cdclk_config->cdclk;
> + u32 val, cmd = cdclk_config->voltage_level;
> intel_wakeref_t wakeref;
>
> switch (cdclk) {
> @@ -611,11 +611,11 @@ static void vlv_set_cdclk(struct
> drm_i915_private *dev_priv,
> }
>
> static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - int cdclk = cdclk_state->cdclk;
> - u32 val, cmd = cdclk_state->voltage_level;
> + int cdclk = cdclk_config->cdclk;
> + u32 val, cmd = cdclk_config->voltage_level;
> intel_wakeref_t wakeref;
>
> switch (cdclk) {
> @@ -685,37 +685,37 @@ static u8 bdw_calc_voltage_level(int cdclk)
> }
>
> static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 lcpll = I915_READ(LCPLL_CTL);
> u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> - cdclk_state->cdclk = 800000;
> + cdclk_config->cdclk = 800000;
> else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> else if (freq == LCPLL_CLK_FREQ_450)
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> else if (freq == LCPLL_CLK_FREQ_54O_BDW)
> - cdclk_state->cdclk = 540000;
> + cdclk_config->cdclk = 540000;
> else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> - cdclk_state->cdclk = 337500;
> + cdclk_config->cdclk = 337500;
> else
> - cdclk_state->cdclk = 675000;
> + cdclk_config->cdclk = 675000;
>
> /*
> * Can't read this out :( Let's assume it's
> * at least what the CDCLK frequency requires.
> */
> - cdclk_state->voltage_level =
> - bdw_calc_voltage_level(cdclk_state->cdclk);
> + cdclk_config->voltage_level =
> + bdw_calc_voltage_level(cdclk_config->cdclk);
> }
>
> static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - int cdclk = cdclk_state->cdclk;
> + int cdclk = cdclk_config->cdclk;
> u32 val;
> int ret;
>
> @@ -778,7 +778,7 @@ static void bdw_set_cdclk(struct drm_i915_private
> *dev_priv,
> DRM_ERROR("Switching back to LCPLL failed\n");
>
> sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> - cdclk_state->voltage_level);
> + cdclk_config->voltage_level);
>
> I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>
> @@ -821,12 +821,12 @@ static u8 skl_calc_voltage_level(int cdclk)
> }
>
> static void skl_dpll0_update(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 val;
>
> - cdclk_state->ref = 24000;
> - cdclk_state->vco = 0;
> + cdclk_config->ref = 24000;
> + cdclk_config->vco = 0;
>
> val = I915_READ(LCPLL1_CTL);
> if ((val & LCPLL_PLL_ENABLE) == 0)
> @@ -848,11 +848,11 @@ static void skl_dpll0_update(struct
> drm_i915_private *dev_priv,
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
> SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
> SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
> SKL_DPLL0):
> - cdclk_state->vco = 8100000;
> + cdclk_config->vco = 8100000;
> break;
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0):
> case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0):
> - cdclk_state->vco = 8640000;
> + cdclk_config->vco = 8640000;
> break;
> default:
> MISSING_CASE(val &
> DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> @@ -861,32 +861,32 @@ static void skl_dpll0_update(struct
> drm_i915_private *dev_priv,
> }
>
> static void skl_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 cdctl;
>
> - skl_dpll0_update(dev_priv, cdclk_state);
> + skl_dpll0_update(dev_priv, cdclk_config);
>
> - cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> + cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
>
> - if (cdclk_state->vco == 0)
> + if (cdclk_config->vco == 0)
> goto out;
>
> cdctl = I915_READ(CDCLK_CTL);
>
> - if (cdclk_state->vco == 8640000) {
> + if (cdclk_config->vco == 8640000) {
> switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> case CDCLK_FREQ_450_432:
> - cdclk_state->cdclk = 432000;
> + cdclk_config->cdclk = 432000;
> break;
> case CDCLK_FREQ_337_308:
> - cdclk_state->cdclk = 308571;
> + cdclk_config->cdclk = 308571;
> break;
> case CDCLK_FREQ_540:
> - cdclk_state->cdclk = 540000;
> + cdclk_config->cdclk = 540000;
> break;
> case CDCLK_FREQ_675_617:
> - cdclk_state->cdclk = 617143;
> + cdclk_config->cdclk = 617143;
> break;
> default:
> MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
> @@ -895,16 +895,16 @@ static void skl_get_cdclk(struct
> drm_i915_private *dev_priv,
> } else {
> switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> case CDCLK_FREQ_450_432:
> - cdclk_state->cdclk = 450000;
> + cdclk_config->cdclk = 450000;
> break;
> case CDCLK_FREQ_337_308:
> - cdclk_state->cdclk = 337500;
> + cdclk_config->cdclk = 337500;
> break;
> case CDCLK_FREQ_540:
> - cdclk_state->cdclk = 540000;
> + cdclk_config->cdclk = 540000;
> break;
> case CDCLK_FREQ_675_617:
> - cdclk_state->cdclk = 675000;
> + cdclk_config->cdclk = 675000;
> break;
> default:
> MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
> @@ -917,8 +917,8 @@ static void skl_get_cdclk(struct drm_i915_private
> *dev_priv,
> * Can't read this out :( Let's assume it's
> * at least what the CDCLK frequency requires.
> */
> - cdclk_state->voltage_level =
> - skl_calc_voltage_level(cdclk_state->cdclk);
> + cdclk_config->voltage_level =
> + skl_calc_voltage_level(cdclk_config->cdclk);
> }
>
> /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
> @@ -989,11 +989,11 @@ static void skl_dpll0_disable(struct
> drm_i915_private *dev_priv)
> }
>
> static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - int cdclk = cdclk_state->cdclk;
> - int vco = cdclk_state->vco;
> + int cdclk = cdclk_config->cdclk;
> + int vco = cdclk_config->vco;
> u32 freq_select, cdclk_ctl;
> int ret;
>
> @@ -1075,7 +1075,7 @@ static void skl_set_cdclk(struct
> drm_i915_private *dev_priv,
>
> /* inform PCU of the change */
> sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_state->voltage_level);
> + cdclk_config->voltage_level);
>
> intel_update_cdclk(dev_priv);
> }
> @@ -1093,7 +1093,7 @@ static void skl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> goto sanitize;
>
> intel_update_cdclk(dev_priv);
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
>
> /* Is PLL enabled and locked ? */
> if (dev_priv->cdclk.hw.vco == 0 ||
> @@ -1124,7 +1124,7 @@ static void skl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
>
> static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - struct intel_cdclk_state cdclk_state;
> + struct intel_cdclk_config cdclk_config;
>
> skl_sanitize_cdclk(dev_priv);
>
> @@ -1140,26 +1140,26 @@ static void skl_init_cdclk(struct
> drm_i915_private *dev_priv)
> return;
> }
>
> - cdclk_state = dev_priv->cdclk.hw;
> + cdclk_config = dev_priv->cdclk.hw;
>
> - cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
> - if (cdclk_state.vco == 0)
> - cdclk_state.vco = 8100000;
> - cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
> - cdclk_state.voltage_level =
> skl_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
> + if (cdclk_config.vco == 0)
> + cdclk_config.vco = 8100000;
> + cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
> + cdclk_config.voltage_level =
> skl_calc_voltage_level(cdclk_config.cdclk);
>
> - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> {
> - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> - cdclk_state.cdclk = cdclk_state.bypass;
> - cdclk_state.vco = 0;
> - cdclk_state.voltage_level =
> skl_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_config.cdclk = cdclk_config.bypass;
> + cdclk_config.vco = 0;
> + cdclk_config.voltage_level =
> skl_calc_voltage_level(cdclk_config.cdclk);
>
> - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> @@ -1284,16 +1284,16 @@ static u8 ehl_calc_voltage_level(int cdclk)
> }
>
> static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> - cdclk_state->ref = 24000;
> + cdclk_config->ref = 24000;
> else
> - cdclk_state->ref = 19200;
> + cdclk_config->ref = 19200;
> }
>
> static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 dssm = I915_READ(SKL_DSSM) &
> ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
>
> @@ -1302,28 +1302,28 @@ static void icl_readout_refclk(struct
> drm_i915_private *dev_priv,
> MISSING_CASE(dssm);
> /* fall through */
> case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> - cdclk_state->ref = 24000;
> + cdclk_config->ref = 24000;
> break;
> case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> - cdclk_state->ref = 19200;
> + cdclk_config->ref = 19200;
> break;
> case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> - cdclk_state->ref = 38400;
> + cdclk_config->ref = 38400;
> break;
> }
> }
>
> static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 val, ratio;
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_readout_refclk(dev_priv, cdclk_state);
> + icl_readout_refclk(dev_priv, cdclk_config);
> else if (IS_CANNONLAKE(dev_priv))
> - cnl_readout_refclk(dev_priv, cdclk_state);
> + cnl_readout_refclk(dev_priv, cdclk_config);
> else
> - cdclk_state->ref = 19200;
> + cdclk_config->ref = 19200;
>
> val = I915_READ(BXT_DE_PLL_ENABLE);
> if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> @@ -1332,7 +1332,7 @@ static void bxt_de_pll_readout(struct
> drm_i915_private *dev_priv,
> * CDCLK PLL is disabled, the VCO/ratio doesn't matter,
> but
> * setting it to zero is a way to signal that.
> */
> - cdclk_state->vco = 0;
> + cdclk_config->vco = 0;
> return;
> }
>
> @@ -1345,26 +1345,26 @@ static void bxt_de_pll_readout(struct
> drm_i915_private *dev_priv,
> else
> ratio = I915_READ(BXT_DE_PLL_CTL) &
> BXT_DE_PLL_RATIO_MASK;
>
> - cdclk_state->vco = ratio * cdclk_state->ref;
> + cdclk_config->vco = ratio * cdclk_config->ref;
> }
>
> static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state)
> + struct intel_cdclk_config *cdclk_config)
> {
> u32 divider;
> int div;
>
> - bxt_de_pll_readout(dev_priv, cdclk_state);
> + bxt_de_pll_readout(dev_priv, cdclk_config);
>
> if (INTEL_GEN(dev_priv) >= 12)
> - cdclk_state->bypass = cdclk_state->ref / 2;
> + cdclk_config->bypass = cdclk_config->ref / 2;
> else if (INTEL_GEN(dev_priv) >= 11)
> - cdclk_state->bypass = 50000;
> + cdclk_config->bypass = 50000;
> else
> - cdclk_state->bypass = cdclk_state->ref;
> + cdclk_config->bypass = cdclk_config->ref;
>
> - if (cdclk_state->vco == 0) {
> - cdclk_state->cdclk = cdclk_state->bypass;
> + if (cdclk_config->vco == 0) {
> + cdclk_config->cdclk = cdclk_config->bypass;
> goto out;
> }
>
> @@ -1391,15 +1391,15 @@ static void bxt_get_cdclk(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
> div);
>
> out:
> /*
> * Can't read this out :( Let's assume it's
> * at least what the CDCLK frequency requires.
> */
> - cdclk_state->voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_state-
> >cdclk);
> + cdclk_config->voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk_config-
> >cdclk);
> }
>
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1488,11 +1488,11 @@ static u32 bxt_cdclk_cd2x_pipe(struct
> drm_i915_private *dev_priv, enum pipe pipe
> }
>
> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - int cdclk = cdclk_state->cdclk;
> - int vco = cdclk_state->vco;
> + int cdclk = cdclk_config->cdclk;
> + int vco = cdclk_config->vco;
> u32 val, divider;
> int ret;
>
> @@ -1573,7 +1573,7 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
>
> if (INTEL_GEN(dev_priv) >= 10) {
> ret = sandybridge_pcode_write(dev_priv,
> SKL_PCODE_CDCLK_CONTROL,
> - cdclk_state-
> >voltage_level);
> + cdclk_config-
> >voltage_level);
> } else {
> /*
> * The timeout isn't specified, the 2ms used here is
> based on
> @@ -1583,7 +1583,7 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> */
> ret = sandybridge_pcode_write_timeout(dev_priv,
> HSW_PCODE_DE_WRIT
> E_FREQ_REQ,
> - cdclk_state-
> >voltage_level,
> + cdclk_config-
> >voltage_level,
> 150, 2);
> }
>
> @@ -1600,7 +1600,7 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> * Can't read out the voltage level :(
> * Let's just assume everything is as expected.
> */
> - dev_priv->cdclk.hw.voltage_level = cdclk_state-
> >voltage_level;
> + dev_priv->cdclk.hw.voltage_level = cdclk_config-
> >voltage_level;
> }
>
> static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> @@ -1609,7 +1609,7 @@ static void bxt_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> int cdclk, vco;
>
> intel_update_cdclk(dev_priv);
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
>
> if (dev_priv->cdclk.hw.vco == 0 ||
> dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> @@ -1683,7 +1683,7 @@ static void bxt_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
>
> static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - struct intel_cdclk_state cdclk_state;
> + struct intel_cdclk_config cdclk_config;
>
> bxt_sanitize_cdclk(dev_priv);
>
> @@ -1691,31 +1691,31 @@ static void bxt_init_cdclk(struct
> drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco != 0)
> return;
>
> - cdclk_state = dev_priv->cdclk.hw;
> + cdclk_config = dev_priv->cdclk.hw;
>
> /*
> * FIXME:
> * - The initial CDCLK needs to be read from VBT.
> * Need to make this change after VBT has changes for BXT.
> */
> - cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
> - cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
> cdclk_state.cdclk);
> - cdclk_state.voltage_level =
> - dev_priv-
> >display.calc_voltage_level(cdclk_state.cdclk);
> + cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
> + cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv,
> cdclk_config.cdclk);
> + cdclk_config.voltage_level =
> + dev_priv-
> >display.calc_voltage_level(cdclk_config.cdclk);
>
> - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> {
> - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> - cdclk_state.cdclk = cdclk_state.bypass;
> - cdclk_state.vco = 0;
> - cdclk_state.voltage_level =
> - dev_priv-
> >display.calc_voltage_level(cdclk_state.cdclk);
> + cdclk_config.cdclk = cdclk_config.bypass;
> + cdclk_config.vco = 0;
> + cdclk_config.voltage_level =
> + dev_priv-
> >display.calc_voltage_level(cdclk_config.cdclk);
>
> - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> /**
> @@ -1751,15 +1751,17 @@ void intel_cdclk_uninit(struct
> drm_i915_private *i915)
> }
>
> /**
> - * intel_cdclk_needs_modeset - Determine if two CDCLK states require
> a modeset on all pipes
> - * @a: first CDCLK state
> - * @b: second CDCLK state
> + * intel_cdclk_needs_modeset - Determine if changong between the
> CDCLK
> + * configurations requires a modeset on
> all pipes
> + * @a: first CDCLK configuration
> + * @b: second CDCLK configuration
> *
> * Returns:
> - * True if the CDCLK states require pipes to be off during
> reprogramming, false if not.
> + * True if changing between the two CDCLK configurations
> + * requires all pipes to be off, false if not.
> */
> -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
> - const struct intel_cdclk_state *b)
> +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> {
> return a->cdclk != b->cdclk ||
> a->vco != b->vco ||
> @@ -1767,17 +1769,19 @@ bool intel_cdclk_needs_modeset(const struct
> intel_cdclk_state *a,
> }
>
> /**
> - * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need
> a cd2x divider update
> - * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
> - * @a: first CDCLK state
> - * @b: second CDCLK state
> + * intel_cdclk_can_cd2x_update - Determine if changing between the
> two CDCLK
> + * configurations requires only a cd2x
> divider update
> + * @dev_priv: i915 device
> + * @a: first CDCLK configuration
> + * @b: second CDCLK configuration
> *
> * Returns:
> - * True if the CDCLK states require just a cd2x divider update,
> false if not.
> + * True if changing between the two CDCLK configurations
> + * can be done with just a cd2x divider update, false if not.
> */
> static bool intel_cdclk_can_cd2x_update(struct drm_i915_private
> *dev_priv,
> - const struct intel_cdclk_state
> *a,
> - const struct intel_cdclk_state
> *b)
> + const struct intel_cdclk_config
> *a,
> + const struct intel_cdclk_config
> *b)
> {
> /* Older hw doesn't have the capability */
> if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
> @@ -1789,15 +1793,15 @@ static bool
> intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> }
>
> /**
> - * intel_cdclk_changed - Determine if two CDCLK states are different
> - * @a: first CDCLK state
> - * @b: second CDCLK state
> + * intel_cdclk_changed - Determine if two CDCLK configurations are
> different
> + * @a: first CDCLK configuration
> + * @b: second CDCLK configuration
> *
> * Returns:
> - * True if the CDCLK states don't match, false if they do.
> + * True if the CDCLK configurations don't match, false if they do.
> */
> -static bool intel_cdclk_changed(const struct intel_cdclk_state *a,
> - const struct intel_cdclk_state *b)
> +static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> {
> return intel_cdclk_needs_modeset(a, b) ||
> a->voltage_level != b->voltage_level;
> @@ -1843,59 +1847,59 @@ void intel_cdclk_swap_state(struct
> intel_atomic_state *state)
> swap(state->cdclk.actual, dev_priv->cdclk.actual);
> }
>
> -void intel_dump_cdclk_state(const struct intel_cdclk_state
> *cdclk_state,
> - const char *context)
> +void intel_dump_cdclk_config(const struct intel_cdclk_config
> *cdclk_config,
> + const char *context)
> {
> DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d
> kHz, voltage level %d\n",
> - context, cdclk_state->cdclk, cdclk_state->vco,
> - cdclk_state->ref, cdclk_state->bypass,
> - cdclk_state->voltage_level);
> + context, cdclk_config->cdclk, cdclk_config-
> >vco,
> + cdclk_config->ref, cdclk_config->bypass,
> + cdclk_config->voltage_level);
> }
>
> /**
> - * intel_set_cdclk - Push the CDCLK state to the hardware
> + * intel_set_cdclk - Push the CDCLK configuration to the hardware
> * @dev_priv: i915 device
> - * @cdclk_state: new CDCLK state
> + * @cdclk_config: new CDCLK configuration
> * @pipe: pipe with which to synchronize the update
> *
> * Program the hardware based on the passed in CDCLK state,
> * if necessary.
> */
> static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state
> *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe)
> {
> - if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
> + if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
> return;
>
> if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
> return;
>
> - intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
> + intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
>
> - dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
> + dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
>
> - if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
> + if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw,
> cdclk_config),
> "cdclk state doesn't match!\n")) {
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw
> state]");
> - intel_dump_cdclk_state(cdclk_state, "[sw state]");
> + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw
> state]");
> + intel_dump_cdclk_config(cdclk_config, "[sw state]");
> }
> }
>
> /**
> - * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the
> hardware
> + * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration
> to the hardware
> * @dev_priv: i915 device
> - * @old_state: old CDCLK state
> - * @new_state: new CDCLK state
> + * @old_state: old CDCLK configuration
> + * @new_state: new CDCLK configuration
> * @pipe: pipe with which to synchronize the update
> *
> * Program the hardware before updating the HW plane state based on
> the passed
> - * in CDCLK state, if necessary.
> + * in CDCLK configuration, if necessary.
> */
> void
> intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state
> *old_state,
> - const struct intel_cdclk_state
> *new_state,
> + const struct intel_cdclk_config
> *old_state,
> + const struct intel_cdclk_config
> *new_state,
> enum pipe pipe)
> {
> if (pipe == INVALID_PIPE || old_state->cdclk <= new_state-
> >cdclk)
> @@ -1903,19 +1907,19 @@ intel_set_cdclk_pre_plane_update(struct
> drm_i915_private *dev_priv,
> }
>
> /**
> - * intel_set_cdclk_post_plane_update - Push the CDCLK state to the
> hardware
> + * intel_set_cdclk_post_plane_update - Push the CDCLK configuration
> to the hardware
> * @dev_priv: i915 device
> - * @old_state: old CDCLK state
> - * @new_state: new CDCLK state
> + * @old_state: old CDCLK configuration
> + * @new_state: new CDCLK configuration
> * @pipe: pipe with which to synchronize the update
> *
> * Program the hardware after updating the HW plane state based on
> the passed
> - * in CDCLK state, if necessary.
> + * in CDCLK configuration, if necessary.
> */
> void
> intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state
> *old_state,
> - const struct intel_cdclk_state
> *new_state,
> + const struct intel_cdclk_config
> *old_state,
> + const struct intel_cdclk_config
> *new_state,
> enum pipe pipe)
> {
> if (pipe != INVALID_PIPE && old_state->cdclk > new_state-
> >cdclk)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 3f3773c582ae..712cdaea4fef 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -12,7 +12,7 @@
>
> struct drm_i915_private;
> struct intel_atomic_state;
> -struct intel_cdclk_state;
> +struct intel_cdclk_config;
> struct intel_crtc_state;
>
> struct intel_cdclk_vals {
> @@ -29,22 +29,22 @@ void intel_init_cdclk_hooks(struct
> drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_rawclk(struct drm_i915_private *dev_priv);
> -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
> - const struct intel_cdclk_state *b);
> +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b);
> void intel_cdclk_clear_state(struct intel_atomic_state *state);
> void intel_cdclk_swap_state(struct intel_atomic_state *state);
> void
> intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state
> *old_state,
> - const struct intel_cdclk_state
> *new_state,
> + const struct intel_cdclk_config
> *old_state,
> + const struct intel_cdclk_config
> *new_state,
> enum pipe pipe);
> void
> intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state
> *old_state,
> - const struct intel_cdclk_state
> *new_state,
> + const struct intel_cdclk_config
> *old_state,
> + const struct intel_cdclk_config
> *new_state,
> enum pipe pipe);
> -void intel_dump_cdclk_state(const struct intel_cdclk_state
> *cdclk_state,
> - const char *context);
> +void intel_dump_cdclk_config(const struct intel_cdclk_config
> *cdclk_config,
> + const char *context);
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
>
> #endif /* __INTEL_CDCLK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f3f9fe94ed41..de2ab44b9150 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17359,7 +17359,7 @@ void intel_init_display_hooks(struct
> drm_i915_private *dev_priv)
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> intel_update_cdclk(i915);
> - intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
> + intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 21561acfa3ac..2dc00d4b115b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1037,7 +1037,7 @@ static void gen9_assert_dbuf_enabled(struct
> drm_i915_private *dev_priv)
>
> static void gen9_disable_dc_states(struct drm_i915_private
> *dev_priv)
> {
> - struct intel_cdclk_state cdclk_state = {};
> + struct intel_cdclk_config cdclk_config = {};
>
> if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
> tgl_disable_dc3co(dev_priv);
> @@ -1046,9 +1046,9 @@ static void gen9_disable_dc_states(struct
> drm_i915_private *dev_priv)
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
> + dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
> /* Can't read out voltage_level so can't use
> intel_cdclk_changed() */
> - WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> &cdclk_state));
> + WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> &cdclk_config));
>
> gen9_assert_dbuf_enabled(dev_priv);
>
> @@ -4659,7 +4659,7 @@ static void hsw_restore_lcpll(struct
> drm_i915_private *dev_priv)
> intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> intel_update_cdclk(dev_priv);
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a6b95a8ab323..485b26d05e90 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -463,17 +463,17 @@ struct intel_atomic_state {
>
> struct {
> /*
> - * Logical state of cdclk (used for all scaling,
> watermark,
> - * etc. calculations and checks). This is computed as
> if all
> - * enabled crtcs were active.
> + * Logical configuration of cdclk (used for all
> scaling,
> + * watermark, etc. calculations and checks). This is
> + * computed as if all enabled crtcs were active.
> */
> - struct intel_cdclk_state logical;
> + struct intel_cdclk_config logical;
>
> /*
> - * Actual state of cdclk, can be different from the
> logical
> - * state only when all crtc's are DPMS off.
> + * Actual configuration of cdclk, can be different from
> the
> + * logical configuration only when all crtc's are DPMS
> off.
> */
> - struct intel_cdclk_state actual;
> + struct intel_cdclk_config actual;
>
> int force_min_cdclk;
> bool force_min_cdclk_changed;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 650f42bd9cfb..49276ce2819f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -255,18 +255,18 @@ struct sdvo_device_mapping {
> struct intel_connector;
> struct intel_encoder;
> struct intel_atomic_state;
> +struct intel_cdclk_config;
> struct intel_crtc_state;
> struct intel_initial_plane_config;
> struct intel_crtc;
> struct intel_limit;
> struct dpll;
> -struct intel_cdclk_state;
>
> struct drm_i915_display_funcs {
> void (*get_cdclk)(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state *cdclk_state);
> + struct intel_cdclk_config *cdclk_config);
> void (*set_cdclk)(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> + const struct intel_cdclk_config
> *cdclk_config,
> enum pipe pipe);
> int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane);
> @@ -880,7 +880,7 @@ struct intel_wm_config {
> bool sprites_scaled;
> };
>
> -struct intel_cdclk_state {
> +struct intel_cdclk_config {
> unsigned int cdclk, vco, ref, bypass;
> u8 voltage_level;
> };
> @@ -1011,17 +1011,17 @@ struct drm_i915_private {
> */
> struct {
> /*
> - * The current logical cdclk state.
> + * The current logical cdclk configuration.
> * See intel_atomic_state.cdclk.logical
> */
> - struct intel_cdclk_state logical;
> + struct intel_cdclk_config logical;
> /*
> - * The current actual cdclk state.
> + * The current actual cdclk configuration.
> * See intel_atomic_state.cdclk.actual
> */
> - struct intel_cdclk_state actual;
> - /* The current hardware cdclk state */
> - struct intel_cdclk_state hw;
> + struct intel_cdclk_config actual;
> + /* The current hardware cdclk configuration */
> + struct intel_cdclk_config hw;
>
> /* cdclk, divider, and ratio table from bspec */
> const struct intel_cdclk_vals *table;
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
@ 2020-01-22 18:51 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 18:51 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move all the old vs. new state shenanigans
> into intel_set_cdclk_{pre,post}_plane_update() so that the caller
> doesn't need to know any of it.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++------
> ----
> drivers/gpu/drm/i915/display/intel_cdclk.h | 12 +-----
> drivers/gpu/drm/i915/display/intel_display.c | 10 +----
> 3 files changed, 26 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 2a5491eb8af3..a2b1401dcfbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1887,41 +1887,41 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
> }
>
> /**
> - * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration
> to the hardware
> - * @dev_priv: i915 device
> - * @old_state: old CDCLK configuration
> - * @new_state: new CDCLK configuration
> - * @pipe: pipe with which to synchronize the update
> + * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the
> hardware
> + * @state: intel atomic state
> *
> - * Program the hardware before updating the HW plane state based on
> the passed
> - * in CDCLK configuration, if necessary.
> + * Program the hardware before updating the HW plane state based on
> the
> + * new CDCLK state, if necessary.
> */
> void
> -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config
> *old_state,
> - const struct intel_cdclk_config
> *new_state,
> - enum pipe pipe)
> +intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + /* called after intel_cdclk_swap_state()! */
> + const struct intel_cdclk_config *old_state = &state-
> >cdclk.actual;
> + const struct intel_cdclk_config *new_state = &dev_priv-
> >cdclk.actual;
> + enum pipe pipe = state->cdclk.pipe;
> +
> if (pipe == INVALID_PIPE || old_state->cdclk <= new_state-
> >cdclk)
> intel_set_cdclk(dev_priv, new_state, pipe);
> }
>
> /**
> - * intel_set_cdclk_post_plane_update - Push the CDCLK configuration
> to the hardware
> - * @dev_priv: i915 device
> - * @old_state: old CDCLK configuration
> - * @new_state: new CDCLK configuration
> - * @pipe: pipe with which to synchronize the update
> + * intel_set_cdclk_post_plane_update - Push the CDCLK state to the
> hardware
> + * @state: intel atomic state
> *
> - * Program the hardware after updating the HW plane state based on
> the passed
> - * in CDCLK configuration, if necessary.
> + * Program the hardware before updating the HW plane state based on
> the
> + * new CDCLK state, if necessary.
> */
> void
> -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config
> *old_state,
> - const struct intel_cdclk_config
> *new_state,
> - enum pipe pipe)
> +intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + /* called after intel_cdclk_swap_state()! */
> + const struct intel_cdclk_config *old_state = &state-
> >cdclk.actual;
> + const struct intel_cdclk_config *new_state = &dev_priv-
> >cdclk.actual;
> + enum pipe pipe = state->cdclk.pipe;
> +
> if (pipe != INVALID_PIPE && old_state->cdclk > new_state-
> >cdclk)
> intel_set_cdclk(dev_priv, new_state, pipe);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 712cdaea4fef..a3fb7b8e8d31 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -33,16 +33,8 @@ bool intel_cdclk_needs_modeset(const struct
> intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> void intel_cdclk_clear_state(struct intel_atomic_state *state);
> void intel_cdclk_swap_state(struct intel_atomic_state *state);
> -void
> -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config
> *old_state,
> - const struct intel_cdclk_config
> *new_state,
> - enum pipe pipe);
> -void
> -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config
> *old_state,
> - const struct intel_cdclk_config
> *new_state,
> - enum pipe pipe);
> +void intel_set_cdclk_pre_plane_update(struct intel_atomic_state
> *state);
> +void intel_set_cdclk_post_plane_update(struct intel_atomic_state
> *state);
> void intel_dump_cdclk_config(const struct intel_cdclk_config
> *cdclk_config,
> const char *context);
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index de2ab44b9150..25b0eab019cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15411,10 +15411,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev,
> &state->base);
>
> - intel_set_cdclk_pre_plane_update(dev_priv,
> - &state->cdclk.actual,
> - &dev_priv-
> >cdclk.actual,
> - state->cdclk.pipe);
> + intel_set_cdclk_pre_plane_update(state);
>
> /*
> * SKL workaround: bspec recommends we disable the SAGV
> when we
> @@ -15450,10 +15447,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> if (state->modeset) {
> intel_encoders_update_complete(state);
>
> - intel_set_cdclk_post_plane_update(dev_priv,
> - &state->cdclk.actual,
> - &dev_priv-
> >cdclk.actual,
> - state->cdclk.pipe);
> + intel_set_cdclk_post_plane_update(state);
> }
>
> /* FIXME: We should call drm_atomic_helper_commit_hw_done()
> here
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 13/17] drm/i915: Introduce better global state handling
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
@ 2020-01-22 19:00 ` Souza, Jose
2020-01-22 19:11 ` Ville Syrjälä
2020-01-27 15:02 ` Imre Deak
1 sibling, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2020-01-22 19:00 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our current global state handling is pretty ad-hoc. Let's try to
> make it better by imitating the standard drm core private object
> approach.
>
> The reason why we don't want to directly use the private objects
> is locking; Each private object has its own lock so if we
> introduce any global private objects we get serialized by that
> single lock across all pipes. The global state apporoach instead
> uses a read/write lock type of approach where each individual
> crtc lock counts as a read lock, and grabbing all the crtc locks
> allows one write access.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 15 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> .../gpu/drm/i915/display/intel_global_state.c | 223
> ++++++++++++++++++
> .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 10 files changed, 342 insertions(+), 12 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 3c88d7d8c764..787ffe669810 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -190,6 +190,7 @@ i915-y += \
> display/intel_fbc.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> + display/intel_global_state.o \
> display/intel_hdcp.o \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 1c13423d4945..45842ebcdebd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -37,6 +37,7 @@
> #include "intel_atomic.h"
> #include "intel_cdclk.h"
> #include "intel_display_types.h"
> +#include "intel_global_state.h"
> #include "intel_hdcp.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> @@ -500,6 +501,7 @@ void intel_atomic_state_free(struct
> drm_atomic_state *_state)
> struct intel_atomic_state *state =
> to_intel_atomic_state(_state);
>
> drm_atomic_state_default_release(&state->base);
> + kfree(state->global_objs);
>
> i915_sw_fence_fini(&state->commit_ready);
>
> @@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct
> drm_atomic_state *s)
> struct intel_atomic_state *state = to_intel_atomic_state(s);
>
> drm_atomic_state_default_clear(&state->base);
> + intel_atomic_clear_global_state(state);
>
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> @@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct
> drm_atomic_state *state,
> return to_intel_crtc_state(crtc_state);
> }
>
> -int intel_atomic_lock_global_state(struct intel_atomic_state *state)
> +int _intel_atomic_lock_global_state(struct intel_atomic_state
> *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct
> intel_atomic_state *state)
> return 0;
> }
>
> -int intel_atomic_serialize_global_state(struct intel_atomic_state
> *state)
> +int _intel_atomic_serialize_global_state(struct intel_atomic_state
> *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 88133eea0a17..11146292b06f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct
> drm_i915_private *dev_priv,
> struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state);
>
> -int intel_atomic_lock_global_state(struct intel_atomic_state
> *state);
> +int _intel_atomic_lock_global_state(struct intel_atomic_state
> *state);
>
> -int intel_atomic_serialize_global_state(struct intel_atomic_state
> *state);
> +int _intel_atomic_serialize_global_state(struct intel_atomic_state
> *state);
>
> #endif /* __INTEL_ATOMIC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 32e722128638..12626fd94d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -820,7 +820,7 @@ static void glk_force_audio_cdclk(struct
> drm_i915_private *dev_priv,
> enable ? 2 * 96000 : 0;
>
> /* Protects dev_priv->cdclk.force_min_cdclk */
> - ret =
> intel_atomic_lock_global_state(to_intel_atomic_state(state));
> + ret =
> _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> if (!ret)
> ret = drm_atomic_commit(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 701a63c3ca38..3b7932ae2a77 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2063,7 +2063,7 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
>
> cdclk_state->min_cdclk[i] = min_cdclk;
>
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
I believe that we can get rid of intel_atomic_lock_global_state and
intel_atomic_serialize_global_state() please take a look at
https://patchwork.freedesktop.org/series/72242/ there is one test
failing it you think this is something that can be used I will take a
look to the test failure.
> if (ret)
> return ret;
> }
> @@ -2111,7 +2111,7 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
>
> cdclk_state->min_voltage_level[i] = min_voltage_level;
>
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
> @@ -2386,12 +2386,12 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> * Also serialize commits across all crtcs
> * if the actual hw needs to be poked.
> */
> - ret = intel_atomic_serialize_global_state(state);
> + ret = _intel_atomic_serialize_global_state(state);
> if (ret)
> return ret;
> } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> &new_cdclk_state->logical)) {
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3b725764bdcd..70eb6eaab095 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14381,7 +14381,7 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state)
> }
>
> if (state->active_pipe_changes) {
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
> @@ -15652,6 +15652,8 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
> if (!ret)
> ret = drm_atomic_helper_swap_state(&state->base, true);
> + if (!ret)
> + intel_atomic_swap_global_state(state);
>
> if (ret) {
> i915_sw_fence_commit(&state->commit_ready);
> @@ -17518,6 +17520,7 @@ static void intel_mode_config_init(struct
> drm_i915_private *i915)
> struct drm_mode_config *mode_config = &i915->drm.mode_config;
>
> drm_mode_config_init(&i915->drm);
> + INIT_LIST_HEAD(&i915->global_obj_list);
>
> mode_config->min_width = 0;
> mode_config->min_height = 0;
> @@ -17559,6 +17562,12 @@ static void intel_mode_config_init(struct
> drm_i915_private *i915)
> }
> }
>
> +static void intel_mode_config_cleanup(struct drm_i915_private *i915)
> +{
> + intel_atomic_global_obj_cleanup(i915);
> + drm_mode_config_cleanup(&i915->drm);
> +}
> +
> int intel_modeset_init(struct drm_i915_private *i915)
> {
> struct drm_device *dev = &i915->drm;
> @@ -17598,7 +17607,7 @@ int intel_modeset_init(struct
> drm_i915_private *i915)
> for_each_pipe(i915, pipe) {
> ret = intel_crtc_init(i915, pipe);
> if (ret) {
> - drm_mode_config_cleanup(dev);
> + intel_mode_config_cleanup(i915);
> return ret;
> }
> }
> @@ -18551,7 +18560,7 @@ void intel_modeset_driver_remove(struct
> drm_i915_private *i915)
>
> intel_hdcp_component_fini(i915);
>
> - drm_mode_config_cleanup(&i915->drm);
> + intel_mode_config_cleanup(i915);
>
> intel_overlay_cleanup(i915);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b31ed828fa8f..628c4a56a9e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -46,6 +46,7 @@
> #include "i915_drv.h"
>
> struct drm_printer;
> +struct __intel_global_objs_state;
>
> /*
> * Display related stuff
> @@ -461,6 +462,9 @@ struct intel_atomic_state {
>
> intel_wakeref_t wakeref;
>
> + struct __intel_global_objs_state *global_objs;
> + int num_global_objs;
> +
> struct intel_cdclk_state cdclk_state;
>
> bool dpll_set, modeset;
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c
> b/drivers/gpu/drm/i915/display/intel_global_state.c
> new file mode 100644
> index 000000000000..a0cc894c3868
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include <linux/string.h>
> +
> +#include "i915_drv.h"
> +#include "intel_atomic.h"
> +#include "intel_display_types.h"
> +#include "intel_global_state.h"
> +
> +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> + struct intel_global_obj *obj,
> + struct intel_global_state *state,
> + const struct intel_global_state_funcs
> *funcs)
> +{
> + memset(obj, 0, sizeof(*obj));
> +
> + obj->state = state;
> + obj->funcs = funcs;
> + list_add_tail(&obj->head, &dev_priv->global_obj_list);
> +}
> +
> +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> *dev_priv)
> +{
> + struct intel_global_obj *obj, *next;
> +
> + list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list,
> head) {
> + list_del(&obj->head);
> + obj->funcs->atomic_destroy_state(obj, obj->state);
> + }
> +}
> +
> +static void assert_global_state_write_locked(struct drm_i915_private
> *dev_priv)
> +{
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc)
> + drm_modeset_lock_assert_held(&crtc->base.mutex);
> +}
> +
> +static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx
> *ctx,
> + struct drm_modeset_lock *lock)
> +{
> + struct drm_modeset_lock *l;
> +
> + list_for_each_entry(l, &ctx->locked, head) {
> + if (lock == l)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static void assert_global_state_read_locked(struct
> intel_atomic_state *state)
> +{
> + struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + if (modeset_lock_is_held(ctx, &crtc->base.mutex))
> + return;
> + }
> +
> + WARN(1, "Global state not read locked\n");
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj)
> +{
> + int index, num_objs, i;
> + size_t size;
> + struct __intel_global_objs_state *arr;
> + struct intel_global_state *obj_state;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].state;
> +
> + assert_global_state_read_locked(state);
> +
> + num_objs = state->num_global_objs + 1;
> + size = sizeof(*state->global_objs) * num_objs;
> + arr = krealloc(state->global_objs, size, GFP_KERNEL);
> + if (!arr)
> + return ERR_PTR(-ENOMEM);
> +
> + state->global_objs = arr;
> + index = state->num_global_objs;
> + memset(&state->global_objs[index], 0, sizeof(*state-
> >global_objs));
> +
> + obj_state = obj->funcs->atomic_duplicate_state(obj);
> + if (!obj_state)
> + return ERR_PTR(-ENOMEM);
> +
> + obj_state->changed = false;
> +
> + state->global_objs[index].state = obj_state;
> + state->global_objs[index].old_state = obj->state;
> + state->global_objs[index].new_state = obj_state;
> + state->global_objs[index].ptr = obj;
> + obj_state->state = state;
> +
> + state->num_global_objs = num_objs;
> +
> + DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
> + obj, obj_state, state);
> +
> + return obj_state;
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].old_state;
> +
> + return NULL;
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].new_state;
> +
> + return NULL;
> +}
> +
> +void intel_atomic_swap_global_state(struct intel_atomic_state
> *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *old_obj_state, *new_obj_state;
> + struct intel_global_obj *obj;
> + int i;
> +
> + for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
> + new_obj_state, i) {
> + WARN_ON(obj->state != old_obj_state);
> +
> + /*
> + * If the new state wasn't modified (and properly
> + * locked for write access) we throw it away.
> + */
> + if (!new_obj_state->changed)
> + continue;
> +
> + assert_global_state_write_locked(dev_priv);
> +
> + old_obj_state->state = state;
> + new_obj_state->state = NULL;
> +
> + state->global_objs[i].state = old_obj_state;
> + obj->state = new_obj_state;
> + }
> +}
> +
> +void intel_atomic_clear_global_state(struct intel_atomic_state
> *state)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++) {
> + struct intel_global_obj *obj = state-
> >global_objs[i].ptr;
> +
> + obj->funcs->atomic_destroy_state(obj,
> + state-
> >global_objs[i].state);
> + state->global_objs[i].ptr = NULL;
> + state->global_objs[i].state = NULL;
> + state->global_objs[i].old_state = NULL;
> + state->global_objs[i].new_state = NULL;
> + }
> + state->num_global_objs = 0;
> +}
> +
> +int intel_atomic_lock_global_state(struct intel_global_state
> *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + int ret;
> +
> + ret = drm_modeset_lock(&crtc->base.mutex,
> + state->base.acquire_ctx);
> + if (ret)
> + return ret;
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
> +
> +int intel_atomic_serialize_global_state(struct intel_global_state
> *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base,
> crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h
> b/drivers/gpu/drm/i915/display/intel_global_state.h
> new file mode 100644
> index 000000000000..e6163a469029
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GLOBAL_STATE_H__
> +#define __INTEL_GLOBAL_STATE_H__
> +
> +#include <linux/list.h>
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_global_obj;
> +struct intel_global_state;
> +
> +struct intel_global_state_funcs {
> + struct intel_global_state *(*atomic_duplicate_state)(struct
> intel_global_obj *obj);
> + void (*atomic_destroy_state)(struct intel_global_obj *obj,
> + struct intel_global_state *state);
> +};
> +
> +struct intel_global_obj {
> + struct list_head head;
> + struct intel_global_state *state;
> + const struct intel_global_state_funcs *funcs;
> +};
> +
> +#define intel_for_each_global_obj(obj, dev_priv) \
> + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
> +
> +#define for_each_new_global_obj_in_state(__state, obj,
> new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_old_global_obj_in_state(__state, obj,
> new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].old_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_oldnew_global_obj_in_state(__state, obj,
> old_obj_state, new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (old_obj_state) = (__state)-
> >global_objs[__i].old_state, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +struct intel_global_state {
> + struct intel_atomic_state *state;
> + bool changed;
> +};
> +
> +struct __intel_global_objs_state {
> + struct intel_global_obj *ptr;
> + struct intel_global_state *state, *old_state, *new_state;
> +};
> +
> +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> + struct intel_global_obj *obj,
> + struct intel_global_state *state,
> + const struct intel_global_state_funcs
> *funcs);
> +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> *dev_priv);
> +
> +struct intel_global_state *
> +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj);
> +
> +void intel_atomic_swap_global_state(struct intel_atomic_state
> *state);
> +void intel_atomic_clear_global_state(struct intel_atomic_state
> *state);
> +int intel_atomic_lock_global_state(struct intel_global_state
> *obj_state);
> +int intel_atomic_serialize_global_state(struct intel_global_state
> *obj_state);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 1787bfdd057f..b558e68b4dbd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -71,6 +71,7 @@
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> +#include "display/intel_global_state.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
>
> @@ -1100,6 +1101,8 @@ struct drm_i915_private {
> */
> struct mutex dpll_lock;
>
> + struct list_head global_obj_list;
> +
> /*
> * For reading active_pipes, cdclk_state holding any crtc
> * lock is sufficient, for writing must hold all of them.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 13/17] drm/i915: Introduce better global state handling
2020-01-22 19:00 ` Souza, Jose
@ 2020-01-22 19:11 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2020-01-22 19:11 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Jan 22, 2020 at 07:00:27PM +0000, Souza, Jose wrote:
> On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Our current global state handling is pretty ad-hoc. Let's try to
> > make it better by imitating the standard drm core private object
> > approach.
> >
> > The reason why we don't want to directly use the private objects
> > is locking; Each private object has its own lock so if we
> > introduce any global private objects we get serialized by that
> > single lock across all pipes. The global state apporoach instead
> > uses a read/write lock type of approach where each individual
> > crtc lock counts as a read lock, and grabbing all the crtc locks
> > allows one write access.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
> > drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
> > drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 15 +-
> > .../drm/i915/display/intel_display_types.h | 4 +
> > .../gpu/drm/i915/display/intel_global_state.c | 223
> > ++++++++++++++++++
> > .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 10 files changed, 342 insertions(+), 12 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile
> > index 3c88d7d8c764..787ffe669810 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -190,6 +190,7 @@ i915-y += \
> > display/intel_fbc.o \
> > display/intel_fifo_underrun.o \
> > display/intel_frontbuffer.o \
> > + display/intel_global_state.o \
> > display/intel_hdcp.o \
> > display/intel_hotplug.o \
> > display/intel_lpe_audio.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 1c13423d4945..45842ebcdebd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -37,6 +37,7 @@
> > #include "intel_atomic.h"
> > #include "intel_cdclk.h"
> > #include "intel_display_types.h"
> > +#include "intel_global_state.h"
> > #include "intel_hdcp.h"
> > #include "intel_psr.h"
> > #include "intel_sprite.h"
> > @@ -500,6 +501,7 @@ void intel_atomic_state_free(struct
> > drm_atomic_state *_state)
> > struct intel_atomic_state *state =
> > to_intel_atomic_state(_state);
> >
> > drm_atomic_state_default_release(&state->base);
> > + kfree(state->global_objs);
> >
> > i915_sw_fence_fini(&state->commit_ready);
> >
> > @@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct
> > drm_atomic_state *s)
> > struct intel_atomic_state *state = to_intel_atomic_state(s);
> >
> > drm_atomic_state_default_clear(&state->base);
> > + intel_atomic_clear_global_state(state);
> >
> > state->dpll_set = state->modeset = false;
> > state->global_state_changed = false;
> > @@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct
> > drm_atomic_state *state,
> > return to_intel_crtc_state(crtc_state);
> > }
> >
> > -int intel_atomic_lock_global_state(struct intel_atomic_state *state)
> > +int _intel_atomic_lock_global_state(struct intel_atomic_state
> > *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc *crtc;
> > @@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct
> > intel_atomic_state *state)
> > return 0;
> > }
> >
> > -int intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state)
> > +int _intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc *crtc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 88133eea0a17..11146292b06f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct
> > drm_i915_private *dev_priv,
> > struct intel_crtc *intel_crtc,
> > struct intel_crtc_state *crtc_state);
> >
> > -int intel_atomic_lock_global_state(struct intel_atomic_state
> > *state);
> > +int _intel_atomic_lock_global_state(struct intel_atomic_state
> > *state);
> >
> > -int intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state);
> > +int _intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state);
> >
> > #endif /* __INTEL_ATOMIC_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 32e722128638..12626fd94d29 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -820,7 +820,7 @@ static void glk_force_audio_cdclk(struct
> > drm_i915_private *dev_priv,
> > enable ? 2 * 96000 : 0;
> >
> > /* Protects dev_priv->cdclk.force_min_cdclk */
> > - ret =
> > intel_atomic_lock_global_state(to_intel_atomic_state(state));
> > + ret =
> > _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> > if (!ret)
> > ret = drm_atomic_commit(state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 701a63c3ca38..3b7932ae2a77 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2063,7 +2063,7 @@ static int intel_compute_min_cdclk(struct
> > intel_atomic_state *state)
> >
> > cdclk_state->min_cdclk[i] = min_cdclk;
> >
> > - ret = intel_atomic_lock_global_state(state);
> > + ret = _intel_atomic_lock_global_state(state);
>
> I believe that we can get rid of intel_atomic_lock_global_state and
> intel_atomic_serialize_global_state() please take a look at
> https://patchwork.freedesktop.org/series/72242/ there is one test
> failing it you think this is something that can be used I will take a
> look to the test failure.
IMO no. The global state has to properly protected (and changes to the
hardware state still need proper serialization in many cases). And
we want to make different things less coupled, not more. Hence we want
to get rid of that annoying "all kinds of random things depend on
state->modeset" mess.
>
> > if (ret)
> > return ret;
> > }
> > @@ -2111,7 +2111,7 @@ static int bxt_compute_min_voltage_level(struct
> > intel_atomic_state *state)
> >
> > cdclk_state->min_voltage_level[i] = min_voltage_level;
> >
> > - ret = intel_atomic_lock_global_state(state);
> > + ret = _intel_atomic_lock_global_state(state);
> > if (ret)
> > return ret;
> > }
> > @@ -2386,12 +2386,12 @@ int intel_modeset_calc_cdclk(struct
> > intel_atomic_state *state)
> > * Also serialize commits across all crtcs
> > * if the actual hw needs to be poked.
> > */
> > - ret = intel_atomic_serialize_global_state(state);
> > + ret = _intel_atomic_serialize_global_state(state);
> > if (ret)
> > return ret;
> > } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> > &new_cdclk_state->logical)) {
> > - ret = intel_atomic_lock_global_state(state);
> > + ret = _intel_atomic_lock_global_state(state);
> > if (ret)
> > return ret;
> > } else {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 3b725764bdcd..70eb6eaab095 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14381,7 +14381,7 @@ static int intel_modeset_checks(struct
> > intel_atomic_state *state)
> > }
> >
> > if (state->active_pipe_changes) {
> > - ret = intel_atomic_lock_global_state(state);
> > + ret = _intel_atomic_lock_global_state(state);
> > if (ret)
> > return ret;
> > }
> > @@ -15652,6 +15652,8 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
> > if (!ret)
> > ret = drm_atomic_helper_swap_state(&state->base, true);
> > + if (!ret)
> > + intel_atomic_swap_global_state(state);
> >
> > if (ret) {
> > i915_sw_fence_commit(&state->commit_ready);
> > @@ -17518,6 +17520,7 @@ static void intel_mode_config_init(struct
> > drm_i915_private *i915)
> > struct drm_mode_config *mode_config = &i915->drm.mode_config;
> >
> > drm_mode_config_init(&i915->drm);
> > + INIT_LIST_HEAD(&i915->global_obj_list);
> >
> > mode_config->min_width = 0;
> > mode_config->min_height = 0;
> > @@ -17559,6 +17562,12 @@ static void intel_mode_config_init(struct
> > drm_i915_private *i915)
> > }
> > }
> >
> > +static void intel_mode_config_cleanup(struct drm_i915_private *i915)
> > +{
> > + intel_atomic_global_obj_cleanup(i915);
> > + drm_mode_config_cleanup(&i915->drm);
> > +}
> > +
> > int intel_modeset_init(struct drm_i915_private *i915)
> > {
> > struct drm_device *dev = &i915->drm;
> > @@ -17598,7 +17607,7 @@ int intel_modeset_init(struct
> > drm_i915_private *i915)
> > for_each_pipe(i915, pipe) {
> > ret = intel_crtc_init(i915, pipe);
> > if (ret) {
> > - drm_mode_config_cleanup(dev);
> > + intel_mode_config_cleanup(i915);
> > return ret;
> > }
> > }
> > @@ -18551,7 +18560,7 @@ void intel_modeset_driver_remove(struct
> > drm_i915_private *i915)
> >
> > intel_hdcp_component_fini(i915);
> >
> > - drm_mode_config_cleanup(&i915->drm);
> > + intel_mode_config_cleanup(i915);
> >
> > intel_overlay_cleanup(i915);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b31ed828fa8f..628c4a56a9e9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -46,6 +46,7 @@
> > #include "i915_drv.h"
> >
> > struct drm_printer;
> > +struct __intel_global_objs_state;
> >
> > /*
> > * Display related stuff
> > @@ -461,6 +462,9 @@ struct intel_atomic_state {
> >
> > intel_wakeref_t wakeref;
> >
> > + struct __intel_global_objs_state *global_objs;
> > + int num_global_objs;
> > +
> > struct intel_cdclk_state cdclk_state;
> >
> > bool dpll_set, modeset;
> > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c
> > b/drivers/gpu/drm/i915/display/intel_global_state.c
> > new file mode 100644
> > index 000000000000..a0cc894c3868
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_global_state.c
> > @@ -0,0 +1,223 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2020 Intel Corporation
> > + */
> > +
> > +#include <linux/string.h>
> > +
> > +#include "i915_drv.h"
> > +#include "intel_atomic.h"
> > +#include "intel_display_types.h"
> > +#include "intel_global_state.h"
> > +
> > +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> > + struct intel_global_obj *obj,
> > + struct intel_global_state *state,
> > + const struct intel_global_state_funcs
> > *funcs)
> > +{
> > + memset(obj, 0, sizeof(*obj));
> > +
> > + obj->state = state;
> > + obj->funcs = funcs;
> > + list_add_tail(&obj->head, &dev_priv->global_obj_list);
> > +}
> > +
> > +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> > *dev_priv)
> > +{
> > + struct intel_global_obj *obj, *next;
> > +
> > + list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list,
> > head) {
> > + list_del(&obj->head);
> > + obj->funcs->atomic_destroy_state(obj, obj->state);
> > + }
> > +}
> > +
> > +static void assert_global_state_write_locked(struct drm_i915_private
> > *dev_priv)
> > +{
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc)
> > + drm_modeset_lock_assert_held(&crtc->base.mutex);
> > +}
> > +
> > +static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx
> > *ctx,
> > + struct drm_modeset_lock *lock)
> > +{
> > + struct drm_modeset_lock *l;
> > +
> > + list_for_each_entry(l, &ctx->locked, head) {
> > + if (lock == l)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > +static void assert_global_state_read_locked(struct
> > intel_atomic_state *state)
> > +{
> > + struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + if (modeset_lock_is_held(ctx, &crtc->base.mutex))
> > + return;
> > + }
> > +
> > + WARN(1, "Global state not read locked\n");
> > +}
> > +
> > +struct intel_global_state *
> > +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> > + struct intel_global_obj *obj)
> > +{
> > + int index, num_objs, i;
> > + size_t size;
> > + struct __intel_global_objs_state *arr;
> > + struct intel_global_state *obj_state;
> > +
> > + for (i = 0; i < state->num_global_objs; i++)
> > + if (obj == state->global_objs[i].ptr)
> > + return state->global_objs[i].state;
> > +
> > + assert_global_state_read_locked(state);
> > +
> > + num_objs = state->num_global_objs + 1;
> > + size = sizeof(*state->global_objs) * num_objs;
> > + arr = krealloc(state->global_objs, size, GFP_KERNEL);
> > + if (!arr)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + state->global_objs = arr;
> > + index = state->num_global_objs;
> > + memset(&state->global_objs[index], 0, sizeof(*state-
> > >global_objs));
> > +
> > + obj_state = obj->funcs->atomic_duplicate_state(obj);
> > + if (!obj_state)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + obj_state->changed = false;
> > +
> > + state->global_objs[index].state = obj_state;
> > + state->global_objs[index].old_state = obj->state;
> > + state->global_objs[index].new_state = obj_state;
> > + state->global_objs[index].ptr = obj;
> > + obj_state->state = state;
> > +
> > + state->num_global_objs = num_objs;
> > +
> > + DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
> > + obj, obj_state, state);
> > +
> > + return obj_state;
> > +}
> > +
> > +struct intel_global_state *
> > +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < state->num_global_objs; i++)
> > + if (obj == state->global_objs[i].ptr)
> > + return state->global_objs[i].old_state;
> > +
> > + return NULL;
> > +}
> > +
> > +struct intel_global_state *
> > +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < state->num_global_objs; i++)
> > + if (obj == state->global_objs[i].ptr)
> > + return state->global_objs[i].new_state;
> > +
> > + return NULL;
> > +}
> > +
> > +void intel_atomic_swap_global_state(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *old_obj_state, *new_obj_state;
> > + struct intel_global_obj *obj;
> > + int i;
> > +
> > + for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
> > + new_obj_state, i) {
> > + WARN_ON(obj->state != old_obj_state);
> > +
> > + /*
> > + * If the new state wasn't modified (and properly
> > + * locked for write access) we throw it away.
> > + */
> > + if (!new_obj_state->changed)
> > + continue;
> > +
> > + assert_global_state_write_locked(dev_priv);
> > +
> > + old_obj_state->state = state;
> > + new_obj_state->state = NULL;
> > +
> > + state->global_objs[i].state = old_obj_state;
> > + obj->state = new_obj_state;
> > + }
> > +}
> > +
> > +void intel_atomic_clear_global_state(struct intel_atomic_state
> > *state)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < state->num_global_objs; i++) {
> > + struct intel_global_obj *obj = state-
> > >global_objs[i].ptr;
> > +
> > + obj->funcs->atomic_destroy_state(obj,
> > + state-
> > >global_objs[i].state);
> > + state->global_objs[i].ptr = NULL;
> > + state->global_objs[i].state = NULL;
> > + state->global_objs[i].old_state = NULL;
> > + state->global_objs[i].new_state = NULL;
> > + }
> > + state->num_global_objs = 0;
> > +}
> > +
> > +int intel_atomic_lock_global_state(struct intel_global_state
> > *obj_state)
> > +{
> > + struct intel_atomic_state *state = obj_state->state;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + int ret;
> > +
> > + ret = drm_modeset_lock(&crtc->base.mutex,
> > + state->base.acquire_ctx);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + obj_state->changed = true;
> > +
> > + return 0;
> > +}
> > +
> > +int intel_atomic_serialize_global_state(struct intel_global_state
> > *obj_state)
> > +{
> > + struct intel_atomic_state *state = obj_state->state;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + struct intel_crtc_state *crtc_state;
> > +
> > + crtc_state = intel_atomic_get_crtc_state(&state->base,
> > crtc);
> > + if (IS_ERR(crtc_state))
> > + return PTR_ERR(crtc_state);
> > + }
> > +
> > + obj_state->changed = true;
> > +
> > + return 0;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h
> > b/drivers/gpu/drm/i915/display/intel_global_state.h
> > new file mode 100644
> > index 000000000000..e6163a469029
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> > @@ -0,0 +1,87 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2020 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_GLOBAL_STATE_H__
> > +#define __INTEL_GLOBAL_STATE_H__
> > +
> > +#include <linux/list.h>
> > +
> > +struct drm_i915_private;
> > +struct intel_atomic_state;
> > +struct intel_global_obj;
> > +struct intel_global_state;
> > +
> > +struct intel_global_state_funcs {
> > + struct intel_global_state *(*atomic_duplicate_state)(struct
> > intel_global_obj *obj);
> > + void (*atomic_destroy_state)(struct intel_global_obj *obj,
> > + struct intel_global_state *state);
> > +};
> > +
> > +struct intel_global_obj {
> > + struct list_head head;
> > + struct intel_global_state *state;
> > + const struct intel_global_state_funcs *funcs;
> > +};
> > +
> > +#define intel_for_each_global_obj(obj, dev_priv) \
> > + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
> > +
> > +#define for_each_new_global_obj_in_state(__state, obj,
> > new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].new_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +#define for_each_old_global_obj_in_state(__state, obj,
> > new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].old_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +#define for_each_oldnew_global_obj_in_state(__state, obj,
> > old_obj_state, new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (old_obj_state) = (__state)-
> > >global_objs[__i].old_state, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].new_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +struct intel_global_state {
> > + struct intel_atomic_state *state;
> > + bool changed;
> > +};
> > +
> > +struct __intel_global_objs_state {
> > + struct intel_global_obj *ptr;
> > + struct intel_global_state *state, *old_state, *new_state;
> > +};
> > +
> > +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> > + struct intel_global_obj *obj,
> > + struct intel_global_state *state,
> > + const struct intel_global_state_funcs
> > *funcs);
> > +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> > *dev_priv);
> > +
> > +struct intel_global_state *
> > +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> > + struct intel_global_obj *obj);
> > +struct intel_global_state *
> > +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj);
> > +struct intel_global_state *
> > +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj);
> > +
> > +void intel_atomic_swap_global_state(struct intel_atomic_state
> > *state);
> > +void intel_atomic_clear_global_state(struct intel_atomic_state
> > *state);
> > +int intel_atomic_lock_global_state(struct intel_global_state
> > *obj_state);
> > +int intel_atomic_serialize_global_state(struct intel_global_state
> > *obj_state);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1787bfdd057f..b558e68b4dbd 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -71,6 +71,7 @@
> > #include "display/intel_dpll_mgr.h"
> > #include "display/intel_dsb.h"
> > #include "display/intel_frontbuffer.h"
> > +#include "display/intel_global_state.h"
> > #include "display/intel_gmbus.h"
> > #include "display/intel_opregion.h"
> >
> > @@ -1100,6 +1101,8 @@ struct drm_i915_private {
> > */
> > struct mutex dpll_lock;
> >
> > + struct list_head global_obj_list;
> > +
> > /*
> > * For reading active_pipes, cdclk_state holding any crtc
> > * lock is sufficient, for writing must hold all of them.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Global state rework (rev2)
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
` (22 preceding siblings ...)
2020-01-21 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-01-23 0:02 ` Patchwork
23 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-01-23 0:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Global state rework (rev2)
URL : https://patchwork.freedesktop.org/series/72301/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7786_full -> Patchwork_16191_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16191_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16191_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16191_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@5x-modeset-transitions-fencing:
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-tglb8/igt@kms_atomic_transition@5x-modeset-transitions-fencing.html
Known issues
------------
Here are the changes found in Patchwork_16191_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#109276] / [fdo#112080]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb5/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#679])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-glk5/igt@gem_ctx_persistence@bcs0-mixed-process.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-glk7/igt@gem_ctx_persistence@bcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110841])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@pi-userfault-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#677])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#112146]) +4 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-apl: [PASS][12] -> [INCOMPLETE][13] ([CI#80] / [fdo#103927])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl1/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl3/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
- shard-apl: [PASS][14] -> [TIMEOUT][15] ([fdo#112271] / [i915#530])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
- shard-skl: [PASS][16] -> [TIMEOUT][17] ([fdo#112271] / [i915#530]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-hsw: [PASS][18] -> [TIMEOUT][19] ([fdo#112271] / [i915#530]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-hsw7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][20] -> [TIMEOUT][21] ([fdo#112271] / [i915#530]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([fdo#103665] / [i915#530]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl6/igt@gem_persistent_relocs@forked-thrashing.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl1/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][24] -> [FAIL][25] ([i915#644])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#644])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl9/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][28] -> [INCOMPLETE][29] ([i915#69])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl10/igt@gem_softpin@noreloc-s3.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl5/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rps@waitboost:
- shard-tglb: [PASS][30] -> [FAIL][31] ([i915#413])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-tglb7/igt@i915_pm_rps@waitboost.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-tglb4/igt@i915_pm_rps@waitboost.html
* igt@i915_selftest@mock_requests:
- shard-kbl: [PASS][32] -> [INCOMPLETE][33] ([fdo#103665])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl4/igt@i915_selftest@mock_requests.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl3/igt@i915_selftest@mock_requests.html
- shard-iclb: [PASS][34] -> [INCOMPLETE][35] ([i915#140])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb1/igt@i915_selftest@mock_requests.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb5/igt@i915_selftest@mock_requests.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl7/igt@i915_suspend@debugfs-reader.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [PASS][38] -> [DMESG-WARN][39] ([i915#109])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl10/igt@kms_color@pipe-b-ctm-0-25.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl4/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][42] -> [FAIL][43] ([i915#72])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][44] -> [FAIL][45] ([fdo#108145] / [i915#265])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][46] -> [SKIP][47] ([fdo#109642] / [fdo#111068])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][50] -> [FAIL][51] ([i915#31])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl4/igt@kms_setmode@basic.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl2/igt@kms_setmode@basic.html
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#31])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl7/igt@kms_setmode@basic.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl4/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#112080]) +11 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb1/igt@perf_pmu@busy-no-semaphores-vcs1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb7/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109276]) +17 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][58] ([fdo#112080]) -> [PASS][59] +9 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb5/igt@gem_busy@busy-vcs1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb1/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [SKIP][60] ([fdo#109276] / [fdo#112080]) -> [PASS][61] +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb3/igt@gem_ctx_isolation@vcs1-clean.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html
* igt@gem_ctx_persistence@processes:
- shard-skl: [FAIL][62] ([i915#570]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl1/igt@gem_ctx_persistence@processes.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl8/igt@gem_ctx_persistence@processes.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][64] ([i915#140]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb1/igt@gem_exec_balancer@hang.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb6/igt@gem_exec_balancer@hang.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][66] ([i915#677]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb6/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][68] ([fdo#109276]) -> [PASS][69] +18 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][70] ([fdo#112146]) -> [PASS][71] +5 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-kbl: [TIMEOUT][72] ([fdo#112271] / [i915#530]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-tglb: [TIMEOUT][74] ([fdo#112126] / [fdo#112271] / [i915#530]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-tglb8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-tglb6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrash-inactive:
- shard-glk: [TIMEOUT][76] ([fdo#112271] / [i915#530]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-glk6/igt@gem_persistent_relocs@forked-thrash-inactive.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-glk9/igt@gem_persistent_relocs@forked-thrash-inactive.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-hsw: [INCOMPLETE][78] ([i915#530] / [i915#61]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-hsw1/igt@gem_persistent_relocs@forked-thrashing.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-hsw2/igt@gem_persistent_relocs@forked-thrashing.html
* igt@i915_selftest@mock_requests:
- shard-snb: [INCOMPLETE][80] ([i915#82]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-snb4/igt@i915_selftest@mock_requests.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-snb5/igt@i915_selftest@mock_requests.html
- shard-apl: [INCOMPLETE][82] ([fdo#103927]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl6/igt@i915_selftest@mock_requests.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl4/igt@i915_selftest@mock_requests.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][86] ([i915#79]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][88] ([i915#221]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl6/igt@kms_flip@flip-vs-suspend.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [FAIL][90] ([i915#34]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-tglb: [FAIL][92] ([i915#49]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: [FAIL][94] ([i915#49]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][98] ([fdo#108145]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [SKIP][100] ([fdo#109441]) -> [PASS][101] +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb1/igt@kms_psr@psr2_primary_render.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb2/igt@kms_psr@psr2_primary_render.html
* igt@kms_sequence@get-forked-busy:
- shard-snb: [SKIP][102] ([fdo#109271]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-snb2/igt@kms_sequence@get-forked-busy.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-snb1/igt@kms_sequence@get-forked-busy.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [FAIL][104] ([IGT#28]) -> [SKIP][105] ([fdo#109276] / [fdo#112080])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-snb: [INCOMPLETE][106] ([i915#82]) -> [SKIP][107] ([fdo#109271])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7786/shard-snb2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/shard-snb5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7786 -> Patchwork_16191
CI-20190529: 20190529
CI_DRM_7786: 72275204176397fc718218335edabb840f520024 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5376: 5cf58d947a02379d2885d6dd4f8bb487cfc3eed2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16191: c3282508b4ed1464aba5645604bf41750f53c96d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16191/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
@ 2020-01-24 12:24 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-24 12:24 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_cdclk_needs_cd2x_update() is named rather confusingly.
> We don't have to do a cd2x update, rather we are allowed to
> do one (as opposed to a full PLL reprogramming with its heavy
> handed modeset). So let's rename the function to
> intel_cdclk_can_cd2x_update().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f7f886dcd6ae..9d4cf412b65d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1767,7 +1767,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
> }
>
> /**
> - * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
> + * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need a cd2x divider update
> * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
> * @a: first CDCLK state
> * @b: second CDCLK state
> @@ -1775,9 +1775,9 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
> * Returns:
> * True if the CDCLK states require just a cd2x divider update, false if not.
> */
> -static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *a,
> - const struct intel_cdclk_state *b)
> +static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *a,
> + const struct intel_cdclk_state *b)
> {
> /* Older hw doesn't have the capability */
> if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
> @@ -2393,9 +2393,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> }
>
> if (is_power_of_2(state->active_pipes) &&
> - intel_cdclk_needs_cd2x_update(dev_priv,
> - &dev_priv->cdclk.actual,
> - &state->cdclk.actual)) {
> + intel_cdclk_can_cd2x_update(dev_priv,
> + &dev_priv->cdclk.actual,
> + &state->cdclk.actual)) {
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
>
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
@ 2020-01-24 15:06 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-24 15:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To make life less confusing let's swap() the entire cdclk state
> rather than swapping some parts, copying other parts, and leaving
> the rest just as is.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---------------
> 1 file changed, 3 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f8e70a668b74..002044e80868 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1835,19 +1835,7 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> - /* FIXME maybe swap() these too */
> - memcpy(dev_priv->cdclk_state.min_cdclk,
> - state->cdclk_state.min_cdclk,
> - sizeof(state->cdclk_state.min_cdclk));
> - memcpy(dev_priv->cdclk_state.min_voltage_level,
> - state->cdclk_state.min_voltage_level,
> - sizeof(state->cdclk_state.min_voltage_level));
> -
> - dev_priv->cdclk_state.force_min_cdclk =
> - state->cdclk_state.force_min_cdclk;
> -
> - swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical);
> - swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual);
> + swap(state->cdclk_state, dev_priv->cdclk_state);
> }
>
> void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> @@ -1903,7 +1891,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> /* called after intel_cdclk_swap_state()! */
> const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> - enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
> + enum pipe pipe = new_cdclk_state->pipe;
>
> if (pipe == INVALID_PIPE ||
> old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
> @@ -1924,7 +1912,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> /* called after intel_cdclk_swap_state()! */
> const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> - enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
> + enum pipe pipe = new_cdclk_state->pipe;
>
> if (pipe != INVALID_PIPE &&
> old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
@ 2020-01-24 15:08 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-24 15:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give the cdclk init/uninit functions a _hw suffix to make
> it clear they are about initializing the actual hardware.
> I'll be wanting to to add a intel_cdclk_init() which is
> purely initializing software structures.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++----------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++--
> .../drm/i915/display/intel_display_power.c | 16 ++++++-------
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 002044e80868..701a63c3ca38 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> -static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config;
>
> @@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> @@ -1681,7 +1681,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> -static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config;
>
> @@ -1706,7 +1706,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> @@ -1719,7 +1719,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> }
>
> /**
> - * intel_cdclk_init - Initialize CDCLK
> + * intel_cdclk_init_hw - Initialize CDCLK hardware
> * @i915: i915 device
> *
> * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
> @@ -1727,27 +1727,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> * during the display core initialization sequence, after which the DMC will
> * take care of turning CDCLK off/on as needed.
> */
> -void intel_cdclk_init(struct drm_i915_private *i915)
> +void intel_cdclk_init_hw(struct drm_i915_private *i915)
> {
> if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> - bxt_init_cdclk(i915);
> + bxt_cdclk_init_hw(i915);
> else if (IS_GEN9_BC(i915))
> - skl_init_cdclk(i915);
> + skl_cdclk_init_hw(i915);
> }
>
> /**
> - * intel_cdclk_uninit - Uninitialize CDCLK
> + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
> * @i915: i915 device
> *
> * Uninitialize CDCLK. This is done only during the display core
> * uninitialization sequence.
> */
> -void intel_cdclk_uninit(struct drm_i915_private *i915)
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> {
> if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
> - bxt_uninit_cdclk(i915);
> + bxt_cdclk_uninit_hw(i915);
> else if (IS_GEN9_BC(i915))
> - skl_uninit_cdclk(i915);
> + skl_cdclk_uninit_hw(i915);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index a3fb7b8e8d31..4b965db07720 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -23,8 +23,8 @@ struct intel_cdclk_vals {
> };
>
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -void intel_cdclk_init(struct drm_i915_private *i915);
> -void intel_cdclk_uninit(struct drm_i915_private *i915);
> +void intel_cdclk_init_hw(struct drm_i915_private *i915);
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2dc00d4b115b..3412c56bea6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4763,7 +4763,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -4780,7 +4780,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> @@ -4824,7 +4824,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -4841,7 +4841,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
>
> @@ -4883,7 +4883,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> mutex_unlock(&power_domains->lock);
>
> /* 5. Enable CD clock */
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
> @@ -4905,7 +4905,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> gen9_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> @@ -4997,7 +4997,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> mutex_unlock(&power_domains->lock);
>
> /* 4. Enable CDCLK. */
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> /* 5. Enable DBUF. */
> icl_dbuf_enable(dev_priv);
> @@ -5026,7 +5026,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> icl_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
@ 2020-01-24 15:19 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-24 15:19 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:22PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_atomic_state_free() next to its counterpart.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Some exported functions in this file are missing documentation.
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_atomic.h | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 11 -----------
> 3 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 1269f63ea006..1c13423d4945 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -495,6 +495,17 @@ intel_atomic_state_alloc(struct drm_device *dev)
> return &state->base;
> }
>
> +void intel_atomic_state_free(struct drm_atomic_state *_state)
> +{
> + struct intel_atomic_state *state = to_intel_atomic_state(_state);
> +
> + drm_atomic_state_default_release(&state->base);
> +
> + i915_sw_fence_fini(&state->commit_ready);
> +
> + kfree(state);
> +}
> +
> void intel_atomic_state_clear(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 74c749dbfb4f..88133eea0a17 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -45,6 +45,7 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> +void intel_atomic_state_free(struct drm_atomic_state *state);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> struct intel_crtc_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 63efb8f9c669..3b725764bdcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17116,17 +17116,6 @@ intel_user_framebuffer_create(struct drm_device *dev,
> return fb;
> }
>
> -static void intel_atomic_state_free(struct drm_atomic_state *state)
> -{
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> -
> - drm_atomic_state_default_release(state);
> -
> - i915_sw_fence_fini(&intel_state->commit_ready);
> -
> - kfree(state);
> -}
> -
> static enum drm_mode_status
> intel_mode_valid(struct drm_device *dev,
> const struct drm_display_mode *mode)
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 13/17] drm/i915: Introduce better global state handling
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
2020-01-22 19:00 ` Souza, Jose
@ 2020-01-27 15:02 ` Imre Deak
1 sibling, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-27 15:02 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our current global state handling is pretty ad-hoc. Let's try to
> make it better by imitating the standard drm core private object
> approach.
>
> The reason why we don't want to directly use the private objects
> is locking; Each private object has its own lock so if we
> introduce any global private objects we get serialized by that
> single lock across all pipes. The global state apporoach instead
> uses a read/write lock type of approach where each individual
> crtc lock counts as a read lock, and grabbing all the crtc locks
> allows one write access.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Didn't spot any issues:
Reviewed-by: Imre Deak <imre.deak@intel.com>
Would be good to explain somewhere the difference between only locking
vs. serializing the state.
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 15 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> .../gpu/drm/i915/display/intel_global_state.c | 223 ++++++++++++++++++
> .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 10 files changed, 342 insertions(+), 12 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3c88d7d8c764..787ffe669810 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -190,6 +190,7 @@ i915-y += \
> display/intel_fbc.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> + display/intel_global_state.o \
> display/intel_hdcp.o \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 1c13423d4945..45842ebcdebd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -37,6 +37,7 @@
> #include "intel_atomic.h"
> #include "intel_cdclk.h"
> #include "intel_display_types.h"
> +#include "intel_global_state.h"
> #include "intel_hdcp.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> @@ -500,6 +501,7 @@ void intel_atomic_state_free(struct drm_atomic_state *_state)
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
>
> drm_atomic_state_default_release(&state->base);
> + kfree(state->global_objs);
>
> i915_sw_fence_fini(&state->commit_ready);
>
> @@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> struct intel_atomic_state *state = to_intel_atomic_state(s);
>
> drm_atomic_state_default_clear(&state->base);
> + intel_atomic_clear_global_state(state);
>
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> @@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> return to_intel_crtc_state(crtc_state);
> }
>
> -int intel_atomic_lock_global_state(struct intel_atomic_state *state)
> +int _intel_atomic_lock_global_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct intel_atomic_state *state)
> return 0;
> }
>
> -int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 88133eea0a17..11146292b06f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state);
>
> -int intel_atomic_lock_global_state(struct intel_atomic_state *state);
> +int _intel_atomic_lock_global_state(struct intel_atomic_state *state);
>
> -int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state);
>
> #endif /* __INTEL_ATOMIC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 32e722128638..12626fd94d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -820,7 +820,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> enable ? 2 * 96000 : 0;
>
> /* Protects dev_priv->cdclk.force_min_cdclk */
> - ret = intel_atomic_lock_global_state(to_intel_atomic_state(state));
> + ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> if (!ret)
> ret = drm_atomic_commit(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 701a63c3ca38..3b7932ae2a77 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2063,7 +2063,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>
> cdclk_state->min_cdclk[i] = min_cdclk;
>
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
> @@ -2111,7 +2111,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>
> cdclk_state->min_voltage_level[i] = min_voltage_level;
>
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
> @@ -2386,12 +2386,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> * Also serialize commits across all crtcs
> * if the actual hw needs to be poked.
> */
> - ret = intel_atomic_serialize_global_state(state);
> + ret = _intel_atomic_serialize_global_state(state);
> if (ret)
> return ret;
> } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> &new_cdclk_state->logical)) {
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3b725764bdcd..70eb6eaab095 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14381,7 +14381,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
> }
>
> if (state->active_pipe_changes) {
> - ret = intel_atomic_lock_global_state(state);
> + ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> }
> @@ -15652,6 +15652,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
> if (!ret)
> ret = drm_atomic_helper_swap_state(&state->base, true);
> + if (!ret)
> + intel_atomic_swap_global_state(state);
>
> if (ret) {
> i915_sw_fence_commit(&state->commit_ready);
> @@ -17518,6 +17520,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
> struct drm_mode_config *mode_config = &i915->drm.mode_config;
>
> drm_mode_config_init(&i915->drm);
> + INIT_LIST_HEAD(&i915->global_obj_list);
>
> mode_config->min_width = 0;
> mode_config->min_height = 0;
> @@ -17559,6 +17562,12 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
> }
> }
>
> +static void intel_mode_config_cleanup(struct drm_i915_private *i915)
> +{
> + intel_atomic_global_obj_cleanup(i915);
> + drm_mode_config_cleanup(&i915->drm);
> +}
> +
> int intel_modeset_init(struct drm_i915_private *i915)
> {
> struct drm_device *dev = &i915->drm;
> @@ -17598,7 +17607,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
> for_each_pipe(i915, pipe) {
> ret = intel_crtc_init(i915, pipe);
> if (ret) {
> - drm_mode_config_cleanup(dev);
> + intel_mode_config_cleanup(i915);
> return ret;
> }
> }
> @@ -18551,7 +18560,7 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
>
> intel_hdcp_component_fini(i915);
>
> - drm_mode_config_cleanup(&i915->drm);
> + intel_mode_config_cleanup(i915);
>
> intel_overlay_cleanup(i915);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b31ed828fa8f..628c4a56a9e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -46,6 +46,7 @@
> #include "i915_drv.h"
>
> struct drm_printer;
> +struct __intel_global_objs_state;
>
> /*
> * Display related stuff
> @@ -461,6 +462,9 @@ struct intel_atomic_state {
>
> intel_wakeref_t wakeref;
>
> + struct __intel_global_objs_state *global_objs;
> + int num_global_objs;
> +
> struct intel_cdclk_state cdclk_state;
>
> bool dpll_set, modeset;
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c
> new file mode 100644
> index 000000000000..a0cc894c3868
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include <linux/string.h>
> +
> +#include "i915_drv.h"
> +#include "intel_atomic.h"
> +#include "intel_display_types.h"
> +#include "intel_global_state.h"
> +
> +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> + struct intel_global_obj *obj,
> + struct intel_global_state *state,
> + const struct intel_global_state_funcs *funcs)
> +{
> + memset(obj, 0, sizeof(*obj));
> +
> + obj->state = state;
> + obj->funcs = funcs;
> + list_add_tail(&obj->head, &dev_priv->global_obj_list);
> +}
> +
> +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv)
> +{
> + struct intel_global_obj *obj, *next;
> +
> + list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) {
> + list_del(&obj->head);
> + obj->funcs->atomic_destroy_state(obj, obj->state);
> + }
> +}
> +
> +static void assert_global_state_write_locked(struct drm_i915_private *dev_priv)
> +{
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc)
> + drm_modeset_lock_assert_held(&crtc->base.mutex);
> +}
> +
> +static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx,
> + struct drm_modeset_lock *lock)
> +{
> + struct drm_modeset_lock *l;
> +
> + list_for_each_entry(l, &ctx->locked, head) {
> + if (lock == l)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static void assert_global_state_read_locked(struct intel_atomic_state *state)
> +{
> + struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + if (modeset_lock_is_held(ctx, &crtc->base.mutex))
> + return;
> + }
> +
> + WARN(1, "Global state not read locked\n");
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj)
> +{
> + int index, num_objs, i;
> + size_t size;
> + struct __intel_global_objs_state *arr;
> + struct intel_global_state *obj_state;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].state;
> +
> + assert_global_state_read_locked(state);
> +
> + num_objs = state->num_global_objs + 1;
> + size = sizeof(*state->global_objs) * num_objs;
> + arr = krealloc(state->global_objs, size, GFP_KERNEL);
> + if (!arr)
> + return ERR_PTR(-ENOMEM);
> +
> + state->global_objs = arr;
> + index = state->num_global_objs;
> + memset(&state->global_objs[index], 0, sizeof(*state->global_objs));
> +
> + obj_state = obj->funcs->atomic_duplicate_state(obj);
> + if (!obj_state)
> + return ERR_PTR(-ENOMEM);
> +
> + obj_state->changed = false;
> +
> + state->global_objs[index].state = obj_state;
> + state->global_objs[index].old_state = obj->state;
> + state->global_objs[index].new_state = obj_state;
> + state->global_objs[index].ptr = obj;
> + obj_state->state = state;
> +
> + state->num_global_objs = num_objs;
> +
> + DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
> + obj, obj_state, state);
> +
> + return obj_state;
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].old_state;
> +
> + return NULL;
> +}
> +
> +struct intel_global_state *
> +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++)
> + if (obj == state->global_objs[i].ptr)
> + return state->global_objs[i].new_state;
> +
> + return NULL;
> +}
> +
> +void intel_atomic_swap_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *old_obj_state, *new_obj_state;
> + struct intel_global_obj *obj;
> + int i;
> +
> + for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
> + new_obj_state, i) {
> + WARN_ON(obj->state != old_obj_state);
> +
> + /*
> + * If the new state wasn't modified (and properly
> + * locked for write access) we throw it away.
> + */
> + if (!new_obj_state->changed)
> + continue;
> +
> + assert_global_state_write_locked(dev_priv);
> +
> + old_obj_state->state = state;
> + new_obj_state->state = NULL;
> +
> + state->global_objs[i].state = old_obj_state;
> + obj->state = new_obj_state;
> + }
> +}
> +
> +void intel_atomic_clear_global_state(struct intel_atomic_state *state)
> +{
> + int i;
> +
> + for (i = 0; i < state->num_global_objs; i++) {
> + struct intel_global_obj *obj = state->global_objs[i].ptr;
> +
> + obj->funcs->atomic_destroy_state(obj,
> + state->global_objs[i].state);
> + state->global_objs[i].ptr = NULL;
> + state->global_objs[i].state = NULL;
> + state->global_objs[i].old_state = NULL;
> + state->global_objs[i].new_state = NULL;
> + }
> + state->num_global_objs = 0;
> +}
> +
> +int intel_atomic_lock_global_state(struct intel_global_state *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + int ret;
> +
> + ret = drm_modeset_lock(&crtc->base.mutex,
> + state->base.acquire_ctx);
> + if (ret)
> + return ret;
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
> +
> +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
> new file mode 100644
> index 000000000000..e6163a469029
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GLOBAL_STATE_H__
> +#define __INTEL_GLOBAL_STATE_H__
> +
> +#include <linux/list.h>
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_global_obj;
> +struct intel_global_state;
> +
> +struct intel_global_state_funcs {
> + struct intel_global_state *(*atomic_duplicate_state)(struct intel_global_obj *obj);
> + void (*atomic_destroy_state)(struct intel_global_obj *obj,
> + struct intel_global_state *state);
> +};
> +
> +struct intel_global_obj {
> + struct list_head head;
> + struct intel_global_state *state;
> + const struct intel_global_state_funcs *funcs;
> +};
> +
> +#define intel_for_each_global_obj(obj, dev_priv) \
> + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
> +
> +#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (old_obj_state) = (__state)->global_objs[__i].old_state, \
> + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +struct intel_global_state {
> + struct intel_atomic_state *state;
> + bool changed;
> +};
> +
> +struct __intel_global_objs_state {
> + struct intel_global_obj *ptr;
> + struct intel_global_state *state, *old_state, *new_state;
> +};
> +
> +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> + struct intel_global_obj *obj,
> + struct intel_global_state *state,
> + const struct intel_global_state_funcs *funcs);
> +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv);
> +
> +struct intel_global_state *
> +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj);
> +
> +void intel_atomic_swap_global_state(struct intel_atomic_state *state);
> +void intel_atomic_clear_global_state(struct intel_atomic_state *state);
> +int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
> +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1787bfdd057f..b558e68b4dbd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -71,6 +71,7 @@
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> +#include "display/intel_global_state.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
>
> @@ -1100,6 +1101,8 @@ struct drm_i915_private {
> */
> struct mutex dpll_lock;
>
> + struct list_head global_obj_list;
> +
> /*
> * For reading active_pipes, cdclk_state holding any crtc
> * lock is sufficient, for writing must hold all of them.
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
@ 2020-01-27 15:21 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-27 15:21 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:25PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we have the more formal global state thing let's
> use if for memory bandwidth tracking. No real difference
> to the current private object usage since we already
> tried to avoid taking the single serializing lock needlessly.
> But since we're going to roll the global state out to more
> things probably a good idea to unify the approaches a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 31 +++++++++-----------
> drivers/gpu/drm/i915/display/intel_bw.h | 4 +--
> drivers/gpu/drm/i915/display/intel_display.c | 2 --
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 4 files changed, 17 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index b228671d5a5d..316abcf3e6a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -374,10 +374,9 @@ static struct intel_bw_state *
> intel_atomic_get_bw_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct drm_private_state *bw_state;
> + struct intel_global_state *bw_state;
>
> - bw_state = drm_atomic_get_private_obj_state(&state->base,
> - &dev_priv->bw_obj);
> + bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj);
> if (IS_ERR(bw_state))
> return ERR_CAST(bw_state);
>
> @@ -392,7 +391,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> - int i;
> + int i, ret;
>
> /* FIXME earlier gens need some checks too */
> if (INTEL_GEN(dev_priv) < 11)
> @@ -433,6 +432,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> if (!bw_state)
> return 0;
>
> + ret = intel_atomic_lock_global_state(&bw_state->base);
> + if (ret)
> + return ret;
> +
So getting the state already read locked it and the above will write
lock it. For clarity the above func could be named accordingly. Either
way:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> @@ -449,7 +452,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> return 0;
> }
>
> -static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj)
> +static struct intel_global_state *
> +intel_bw_duplicate_state(struct intel_global_obj *obj)
> {
> struct intel_bw_state *state;
>
> @@ -457,18 +461,16 @@ static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj
> if (!state)
> return NULL;
>
> - __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
> -
> return &state->base;
> }
>
> -static void intel_bw_destroy_state(struct drm_private_obj *obj,
> - struct drm_private_state *state)
> +static void intel_bw_destroy_state(struct intel_global_obj *obj,
> + struct intel_global_state *state)
> {
> kfree(state);
> }
>
> -static const struct drm_private_state_funcs intel_bw_funcs = {
> +static const struct intel_global_state_funcs intel_bw_funcs = {
> .atomic_duplicate_state = intel_bw_duplicate_state,
> .atomic_destroy_state = intel_bw_destroy_state,
> };
> @@ -481,13 +483,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
> if (!state)
> return -ENOMEM;
>
> - drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj,
> - &state->base, &intel_bw_funcs);
> + intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj,
> + &state->base, &intel_bw_funcs);
>
> return 0;
> }
> -
> -void intel_bw_cleanup(struct drm_i915_private *dev_priv)
> -{
> - drm_atomic_private_obj_fini(&dev_priv->bw_obj);
> -}
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 20b9ad241802..a8aa7624c5aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -9,13 +9,14 @@
> #include <drm/drm_atomic.h>
>
> #include "intel_display.h"
> +#include "intel_global_state.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc_state;
>
> struct intel_bw_state {
> - struct drm_private_state base;
> + struct intel_global_state base;
>
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> @@ -25,7 +26,6 @@ struct intel_bw_state {
>
> void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> int intel_bw_init(struct drm_i915_private *dev_priv);
> -void intel_bw_cleanup(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70eb6eaab095..f5396c5c00c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18566,8 +18566,6 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
>
> intel_gmbus_teardown(i915);
>
> - intel_bw_cleanup(i915);
> -
> destroy_workqueue(i915->flip_wq);
> destroy_workqueue(i915->modeset_wq);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b558e68b4dbd..63cda89a4e62 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1251,7 +1251,7 @@ struct drm_i915_private {
> u8 num_planes;
> } max_bw[6];
>
> - struct drm_private_obj bw_obj;
> + struct intel_global_obj bw_obj;
>
> struct intel_runtime_pm runtime_pm;
>
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes()
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
@ 2020-01-27 15:25 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-27 15:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:26PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract a small helper to compute the active pipes bitmask
> based on the old bitmask + the crtcs in the atomic state.
> I want to decouple the cdclk state entirely from the current
> global state so I want to track the active pipes also inside
> the (to be introduced) full cdclk state.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_display.h | 3 ++
> 2 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f5396c5c00c6..dc767efffd9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14359,26 +14359,32 @@ static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
> return 0;
> }
>
> +u8 intel_calc_active_pipes(struct intel_atomic_state *state,
> + u8 active_pipes)
> +{
> + const struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + if (crtc_state->hw.active)
> + active_pipes |= BIT(crtc->pipe);
> + else
> + active_pipes &= ~BIT(crtc->pipe);
> + }
> +
> + return active_pipes;
> +}
> +
> static int intel_modeset_checks(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> - struct intel_crtc *crtc;
> - int ret, i;
> + int ret;
>
> state->modeset = true;
> - state->active_pipes = dev_priv->active_pipes;
> + state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes);
>
> - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> - new_crtc_state, i) {
> - if (new_crtc_state->hw.active)
> - state->active_pipes |= BIT(crtc->pipe);
> - else
> - state->active_pipes &= ~BIT(crtc->pipe);
> -
> - if (old_crtc_state->hw.active != new_crtc_state->hw.active)
> - state->active_pipe_changes |= BIT(crtc->pipe);
> - }
> + state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes;
>
> if (state->active_pipe_changes) {
> ret = _intel_atomic_lock_global_state(state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 028aab728514..e2de0d9d22bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -44,6 +44,7 @@ struct drm_modeset_acquire_ctx;
> struct drm_plane;
> struct drm_plane_state;
> struct i915_ggtt_view;
> +struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_digital_port;
> @@ -469,6 +470,8 @@ enum phy_fia {
> ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
> (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
>
> +u8 intel_calc_active_pipes(struct intel_atomic_state *state,
> + u8 active_pipes);
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH v2 16/17] drm/i915: Convert cdclk to global state
2020-01-21 14:03 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2020-01-27 17:03 ` Imre Deak
2020-01-27 17:15 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Imre Deak @ 2020-01-27 17:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Jan 21, 2020 at 04:03:53PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's convert cdclk_state to be a proper global state. That allows
> us to use the regular atomic old vs. new state accessor, hopefully
> making the code less confusing.
>
> We do have to deal with a few more error cases in case the cdclk
> state duplication fails. But so be it.
>
> v2: Fix new plane min_cdclk vs. old crtc min_cdclk check
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
> .../gpu/drm/i915/display/intel_atomic_plane.c | 68 ++++---
> .../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 39 +++-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 192 ++++++++++--------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 45 +++-
> drivers/gpu/drm/i915/display/intel_display.c | 122 +++++++----
> .../drm/i915/display/intel_display_types.h | 3 -
> drivers/gpu/drm/i915/i915_drv.h | 45 +---
> 9 files changed, 316 insertions(+), 204 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 45842ebcdebd..b51ddf9a250f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -518,7 +518,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> state->active_pipes = 0;
> - intel_cdclk_clear_state(state);
> }
>
> struct intel_crtc_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 563caec1d201..230d0e4f6169 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -37,6 +37,7 @@
>
> #include "i915_trace.h"
> #include "intel_atomic_plane.h"
> +#include "intel_cdclk.h"
> #include "intel_display_types.h"
> #include "intel_pm.h"
> #include "intel_sprite.h"
> @@ -155,44 +156,61 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> return cpp * crtc_state->pixel_rate;
> }
>
> -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> - struct intel_plane *plane)
> +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> + struct intel_plane *plane,
> + bool *need_cdclk_calc)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - const struct intel_cdclk_state *cdclk_state =
> - &dev_priv->cdclk_state;
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
> - struct intel_crtc_state *crtc_state;
> + const struct intel_cdclk_state *cdclk_state;
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
>
> if (!plane_state->uapi.visible || !plane->min_cdclk)
> - return false;
> + return 0;
> +
> + new_crtc_state->min_cdclk[plane->id] =
> + plane->min_cdclk(new_crtc_state, plane_state);
>
> - crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> + /*
> + * No need to check against the cdclk state if
> + * the min cdclk for the plane doesn't increase.
> + *
> + * Ie. we only ever increase the cdclk due to plane
> + * requirements. This can reduce back and forth
> + * display blinking due to constant cdclk changes.
> + */
> + if (new_crtc_state->min_cdclk[plane->id] <=
> + old_crtc_state->min_cdclk[plane->id])
> + return 0;
>
> - crtc_state->min_cdclk[plane->id] =
> - plane->min_cdclk(crtc_state, plane_state);
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
>
> /*
> - * Does the cdclk need to be bumbed up?
> + * No need to recalculate the cdclk state if
> + * the min cdclk for the pipe doesn't increase.
> *
> - * Note: we obviously need to be called before the new
> - * cdclk frequency is calculated so state->cdclk.logical
> - * hasn't been populated yet. Hence we look at the old
> - * cdclk state under dev_priv->cdclk.logical. This is
> - * safe as long we hold at least one crtc mutex (which
> - * must be true since we have crtc_state).
> + * Ie. we only ever increase the cdclk due to plane
> + * requirements. This can reduce back and forth
> + * display blinking due to constant cdclk changes.
> */
> - if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
> - DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
> - plane->base.base.id, plane->base.name,
> - crtc_state->min_cdclk[plane->id],
> - cdclk_state->logical.cdclk);
> - return true;
> - }
> + if (new_crtc_state->min_cdclk[plane->id] <=
> + cdclk_state->min_cdclk[crtc->pipe])
> + return 0;
> +
> + DRM_DEBUG_KMS("[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
> + plane->base.base.id, plane->base.name,
> + new_crtc_state->min_cdclk[plane->id],
> + crtc->base.base.id, crtc->base.name,
> + cdclk_state->min_cdclk[crtc->pipe]);
> + *need_cdclk_calc = true;
>
> - return false;
> + return 0;
> }
>
> static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 5cedafdddb55..2bcf15e34728 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *old_plane_state,
> struct intel_plane_state *plane_state);
> -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> - struct intel_plane *plane);
> +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> + struct intel_plane *plane,
> + bool *need_cdclk_calc);
>
> #endif /* __INTEL_ATOMIC_PLANE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 12626fd94d29..9debac75eaec 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -30,6 +30,7 @@
> #include "i915_drv.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> +#include "intel_cdclk.h"
> #include "intel_display_types.h"
> #include "intel_lpe_audio.h"
>
> @@ -800,6 +801,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
> + bool enable)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state;
> + struct intel_crtc *crtc;
> + int ret;
> +
> + /* need to hold at least one crtc lock for the global state */
> + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> + ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
> + if (ret)
> + return ret;
Nit: couldn't intel_atomic_lock_global_state() be moved earlier instead
of the above?
Reviewed-by: Imre Deak <imre.deak@intel.com>
> +
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
> +
> + cdclk_state->force_min_cdclk_changed = true;
> + cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
> +
> + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> + if (ret)
> + return ret;
> +
> + return drm_atomic_commit(&state->base);
> +}
> +
> static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> bool enable)
> {
> @@ -815,15 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> state->acquire_ctx = &ctx;
>
> retry:
> - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
> - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
> - enable ? 2 * 96000 : 0;
> -
> - /* Protects dev_priv->cdclk.force_min_cdclk */
> - ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> - if (!ret)
> - ret = drm_atomic_commit(state);
> -
> + ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
> if (ret == -EDEADLK) {
> drm_atomic_state_clear(state);
> drm_modeset_backoff(&ctx);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3b7932ae2a77..e14bda2bec71 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1807,37 +1807,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> a->voltage_level != b->voltage_level;
> }
>
> -/**
> - * intel_cdclk_clear_state - clear the cdclk state
> - * @state: atomic state
> - *
> - * Clear the cdclk state for ww_mutex backoff.
> - */
> -void intel_cdclk_clear_state(struct intel_atomic_state *state)
> -{
> - memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
> - state->cdclk_state.pipe = INVALID_PIPE;
> -}
> -
> -/**
> - * intel_cdclk_swap_state - make atomic CDCLK configuration effective
> - * @state: atomic state
> - *
> - * This is the CDCLK version of drm_atomic_helper_swap_state() since the
> - * helper does not handle driver-specific global state.
> - *
> - * Similarly to the atomic helpers this function does a complete swap,
> - * i.e. it also puts the old state into @state. This is used by the commit
> - * code to determine how CDCLK has changed (for instance did it increase or
> - * decrease).
> - */
> -void intel_cdclk_swap_state(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -
> - swap(state->cdclk_state, dev_priv->cdclk_state);
> -}
> -
> void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> const char *context)
> {
> @@ -1888,14 +1857,22 @@ void
> intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - /* called after intel_cdclk_swap_state()! */
> - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> + const struct intel_cdclk_state *old_cdclk_state =
> + intel_atomic_get_old_cdclk_state(state);
> + const struct intel_cdclk_state *new_cdclk_state =
> + intel_atomic_get_new_cdclk_state(state);
> enum pipe pipe = new_cdclk_state->pipe;
>
> + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> + &new_cdclk_state->actual))
> + return;
> +
> if (pipe == INVALID_PIPE ||
> - old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
> + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> + WARN_ON(!new_cdclk_state->base.changed);
> +
> intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> + }
> }
>
> /**
> @@ -1909,14 +1886,22 @@ void
> intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - /* called after intel_cdclk_swap_state()! */
> - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> + const struct intel_cdclk_state *old_cdclk_state =
> + intel_atomic_get_old_cdclk_state(state);
> + const struct intel_cdclk_state *new_cdclk_state =
> + intel_atomic_get_new_cdclk_state(state);
> enum pipe pipe = new_cdclk_state->pipe;
>
> + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> + &new_cdclk_state->actual))
> + return;
> +
> if (pipe != INVALID_PIPE &&
> - old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
> + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
> + WARN_ON(!new_cdclk_state->base.changed);
> +
> intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> + }
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> @@ -2042,10 +2027,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> return min_cdclk;
> }
>
> -static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> +static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> + struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> @@ -2063,7 +2048,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>
> cdclk_state->min_cdclk[i] = min_cdclk;
>
> - ret = _intel_atomic_lock_global_state(state);
> + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> if (ret)
> return ret;
> }
> @@ -2088,10 +2073,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> * future platforms this code will need to be
> * adjusted.
> */
> -static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> +static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
> {
> + struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> u8 min_voltage_level;
> @@ -2111,7 +2096,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>
> cdclk_state->min_voltage_level[i] = min_voltage_level;
>
> - ret = _intel_atomic_lock_global_state(state);
> + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> if (ret)
> return ret;
> }
> @@ -2124,13 +2109,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> return min_voltage_level;
> }
>
> -static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> +static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> + struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, cdclk;
>
> - min_cdclk = intel_compute_min_cdclk(state);
> + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> @@ -2153,12 +2138,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> +static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> + struct intel_atomic_state *state = cdclk_state->base.state;
> int min_cdclk, cdclk;
>
> - min_cdclk = intel_compute_min_cdclk(state);
> + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> @@ -2185,10 +2170,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int skl_dpll0_vco(struct intel_atomic_state *state)
> +static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
> {
> + struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int vco, i;
> @@ -2222,16 +2207,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
> return vco;
> }
>
> -static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> +static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> + struct intel_atomic_state *state = cdclk_state->base.state;
> int min_cdclk, cdclk, vco;
>
> - min_cdclk = intel_compute_min_cdclk(state);
> + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> - vco = skl_dpll0_vco(state);
> + vco = skl_dpll0_vco(cdclk_state);
>
> /*
> * FIXME should also account for plane ratio
> @@ -2258,17 +2243,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> +static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> + struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> int min_cdclk, min_voltage_level, cdclk, vco;
>
> - min_cdclk = intel_compute_min_cdclk(state);
> + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> - min_voltage_level = bxt_compute_min_voltage_level(state);
> + min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
> if (min_voltage_level < 0)
> return min_voltage_level;
>
> @@ -2335,7 +2320,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> +static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> int min_cdclk;
>
> @@ -2344,54 +2329,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> * check that the required minimum frequency doesn't exceed
> * the actual cdclk frequency.
> */
> - min_cdclk = intel_compute_min_cdclk(state);
> + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> return 0;
> }
>
> +static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
> +{
> + struct intel_cdclk_state *cdclk_state;
> +
> + cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
> + if (!cdclk_state)
> + return NULL;
> +
> + cdclk_state->force_min_cdclk_changed = false;
> + cdclk_state->pipe = INVALID_PIPE;
> +
> + return &cdclk_state->base;
> +}
> +
> +static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
> + struct intel_global_state *state)
> +{
> + kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_cdclk_funcs = {
> + .atomic_duplicate_state = intel_cdclk_duplicate_state,
> + .atomic_destroy_state = intel_cdclk_destroy_state,
> +};
> +
> +struct intel_cdclk_state *
> +intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *cdclk_state;
> +
> + cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
> + if (IS_ERR(cdclk_state))
> + return ERR_CAST(cdclk_state);
> +
> + return to_intel_cdclk_state(cdclk_state);
> +}
> +
> +int intel_cdclk_init(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state *cdclk_state;
> +
> + cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
> + if (!cdclk_state)
> + return -ENOMEM;
> +
> + intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
> + &cdclk_state->base, &intel_cdclk_funcs);
> +
> + return 0;
> +}
> +
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
> - struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
> + const struct intel_cdclk_state *old_cdclk_state;
> + struct intel_cdclk_state *new_cdclk_state;
> enum pipe pipe;
> int ret;
>
> - memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
> - sizeof(new_cdclk_state->min_cdclk));
> - memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
> - sizeof(new_cdclk_state->min_voltage_level));
> + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(new_cdclk_state))
> + return PTR_ERR(new_cdclk_state);
>
> - /* keep the current setting */
> - if (!new_cdclk_state->force_min_cdclk_changed)
> - new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
> + old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
>
> - new_cdclk_state->logical = old_cdclk_state->logical;
> - new_cdclk_state->actual = old_cdclk_state->actual;
> -
> - ret = dev_priv->display.modeset_calc_cdclk(state);
> + ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> if (ret)
> return ret;
>
> - /*
> - * Writes to dev_priv->cdclk.{actual,logical} must protected
> - * by holding all the crtc mutexes even if we don't end up
> - * touching the hardware
> - */
> if (intel_cdclk_changed(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> /*
> * Also serialize commits across all crtcs
> * if the actual hw needs to be poked.
> */
> - ret = _intel_atomic_serialize_global_state(state);
> + ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
> if (ret)
> return ret;
> } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> &new_cdclk_state->logical)) {
> - ret = _intel_atomic_lock_global_state(state);
> + ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
> if (ret)
> return ret;
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 4b965db07720..195fca70bfcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -8,11 +8,12 @@
>
> #include <linux/types.h>
>
> +#include "i915_drv.h"
> #include "intel_display.h"
> +#include "intel_global_state.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
> -struct intel_cdclk_config;
> struct intel_crtc_state;
>
> struct intel_cdclk_vals {
> @@ -22,6 +23,35 @@ struct intel_cdclk_vals {
> u8 ratio;
> };
>
> +struct intel_cdclk_state {
> + struct intel_global_state base;
> +
> + /*
> + * Logical configuration of cdclk (used for all scaling,
> + * watermark, etc. calculations and checks). This is
> + * computed as if all enabled crtcs were active.
> + */
> + struct intel_cdclk_config logical;
> +
> + /*
> + * Actual configuration of cdclk, can be different from the
> + * logical configuration only when all crtc's are DPMS off.
> + */
> + struct intel_cdclk_config actual;
> +
> + /* minimum acceptable cdclk for each pipe */
> + int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage level for each pipe */
> + u8 min_voltage_level[I915_MAX_PIPES];
> +
> + /* pipe to which cd2x update is synchronized */
> + enum pipe pipe;
> +
> + /* forced minimum cdclk for glk+ audio w/a */
> + int force_min_cdclk;
> + bool force_min_cdclk_changed;
> +};
> +
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> void intel_cdclk_init_hw(struct drm_i915_private *i915);
> void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> @@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> -void intel_cdclk_clear_state(struct intel_atomic_state *state);
> -void intel_cdclk_swap_state(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> const char *context);
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
>
> +struct intel_cdclk_state *
> +intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
> +
> +#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
> +#define intel_atomic_get_old_cdclk_state(state) \
> + to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> +#define intel_atomic_get_new_cdclk_state(state) \
> + to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> +
> +int intel_cdclk_init(struct drm_i915_private *dev_priv);
> +
> #endif /* __INTEL_CDCLK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dc767efffd9a..dca100546be8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7482,7 +7482,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> struct intel_bw_state *bw_state =
> to_intel_bw_state(dev_priv->bw_obj.state);
> struct intel_cdclk_state *cdclk_state =
> - &dev_priv->cdclk_state;
> + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum intel_display_power_domain domain;
> @@ -7780,17 +7780,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> return true;
> }
>
> -static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> +static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_atomic_state *intel_state =
> + struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->uapi.state);
> - const struct intel_cdclk_state *cdclk_state =
> - &intel_state->cdclk_state;
> +
> + crtc_state->ips_enabled = false;
>
> if (!hsw_crtc_state_ips_capable(crtc_state))
> - return false;
> + return 0;
>
> /*
> * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> @@ -7799,18 +7799,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> * completely disable it.
> */
> if (crtc_state->crc_enabled)
> - return false;
> + return 0;
>
> /* IPS should be fine as long as at least one plane is enabled. */
> if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
> - return false;
> + return 0;
>
> - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> - if (IS_BROADWELL(dev_priv) &&
> - crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> - return false;
> + if (IS_BROADWELL(dev_priv)) {
> + const struct intel_cdclk_state *cdclk_state;
>
> - return true;
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
> +
> + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> + if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> + return 0;
> + }
> +
> + crtc_state->ips_enabled = true;
> +
> + return 0;
> }
>
> static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> @@ -12543,14 +12552,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> adjusted_mode->crtc_clock);
> }
>
> -static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
> +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_cdclk_state *cdclk_state)
> {
> - const struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->uapi.state);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> - const struct intel_cdclk_state *cdclk_state =
> - &state->cdclk_state;
>
> if (!crtc_state->hw.enable)
> return 0;
> @@ -12580,6 +12586,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
> return linetime_wm;
> }
>
> +static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_cdclk_state *cdclk_state;
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + crtc_state->linetime = skl_linetime_wm(crtc_state);
> + else
> + crtc_state->linetime = hsw_linetime_wm(crtc_state);
> +
> + if (!hsw_crtc_supports_ips(crtc))
> + return 0;
> +
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
> +
> + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
> + cdclk_state);
> +
> + return 0;
> +}
> +
> static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -12615,7 +12647,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> return ret;
> }
>
> - ret = 0;
> if (dev_priv->display.compute_pipe_wm) {
> ret = dev_priv->display.compute_pipe_wm(crtc_state);
> if (ret) {
> @@ -12646,20 +12677,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> if (!ret)
> ret = intel_atomic_setup_scalers(dev_priv, crtc,
> crtc_state);
> + if (ret)
> + return ret;
> }
>
> - if (HAS_IPS(dev_priv))
> - crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
> + if (HAS_IPS(dev_priv)) {
> + ret = hsw_compute_ips_config(crtc_state);
> + if (ret)
> + return ret;
> + }
> +
> + if (INTEL_GEN(dev_priv) >= 9 ||
> + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> + ret = hsw_compute_linetime_wm(state, crtc);
> + if (ret)
> + return ret;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> - crtc_state->linetime = skl_linetime_wm(crtc_state);
> - } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> - crtc_state->linetime = hsw_linetime_wm(crtc_state);
> - if (hsw_crtc_supports_ips(crtc))
> - crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
> }
>
> - return ret;
> + return 0;
> }
>
> static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> @@ -14478,7 +14514,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
> }
>
> static int intel_atomic_check_planes(struct intel_atomic_state *state,
> - bool *need_modeset)
> + bool *need_cdclk_calc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> @@ -14532,8 +14568,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
> * affected planes are part of the state. We can now
> * compute the minimum cdclk for each plane.
> */
> - for_each_new_intel_plane_in_state(state, plane, plane_state, i)
> - *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> @@ -14654,6 +14693,7 @@ static int intel_atomic_check(struct drm_device *dev,
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
> struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> + struct intel_cdclk_state *new_cdclk_state;
> struct intel_crtc *crtc;
> int ret, i;
> bool any_ms = false;
> @@ -14766,18 +14806,18 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> - any_ms |= state->cdclk_state.force_min_cdclk_changed;
> -
> ret = intel_atomic_check_planes(state, &any_ms);
> if (ret)
> goto fail;
>
> + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
> + any_ms = true;
> +
> if (any_ms) {
> ret = intel_modeset_checks(state);
> if (ret)
> goto fail;
> - } else {
> - state->cdclk_state.logical = dev_priv->cdclk_state.logical;
> }
>
> ret = intel_atomic_check_crtcs(state);
> @@ -15676,8 +15716,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> assert_global_state_locked(dev_priv);
>
> dev_priv->active_pipes = state->active_pipes;
> -
> - intel_cdclk_swap_state(state);
> }
>
> drm_atomic_state_get(&state->base);
> @@ -17356,7 +17394,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> struct intel_cdclk_state *cdclk_state =
> - &i915->cdclk_state;
> + to_intel_cdclk_state(i915->cdclk.obj.state);
>
> intel_update_cdclk(i915);
> intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
> @@ -17587,6 +17625,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
>
> intel_mode_config_init(i915);
>
> + ret = intel_cdclk_init(i915);
> + if (ret)
> + return ret;
> +
> ret = intel_bw_init(i915);
> if (ret)
> return ret;
> @@ -18071,6 +18113,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
> static void intel_modeset_readout_hw_state(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_cdclk_state *cdclk_state =
> + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> enum pipe pipe;
> struct intel_crtc *crtc;
> struct intel_encoder *encoder;
> @@ -18190,8 +18234,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> for_each_intel_crtc(dev, crtc) {
> struct intel_bw_state *bw_state =
> to_intel_bw_state(dev_priv->bw_obj.state);
> - struct intel_cdclk_state *cdclk_state =
> - &dev_priv->cdclk_state;
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> struct intel_plane *plane;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 628c4a56a9e9..524b6d5235ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -465,8 +465,6 @@ struct intel_atomic_state {
> struct __intel_global_objs_state *global_objs;
> int num_global_objs;
>
> - struct intel_cdclk_state cdclk_state;
> -
> bool dpll_set, modeset;
>
> /*
> @@ -493,7 +491,6 @@ struct intel_atomic_state {
>
> /*
> * active_pipes
> - * cdclk_state
> */
> bool global_state_changed;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 63cda89a4e62..2e6b149478c1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -65,7 +65,6 @@
> #include "i915_utils.h"
>
> #include "display/intel_bios.h"
> -#include "display/intel_cdclk.h"
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> #include "display/intel_dpll_mgr.h"
> @@ -258,7 +257,8 @@ struct intel_connector;
> struct intel_encoder;
> struct intel_atomic_state;
> struct intel_cdclk_config;
> -struct intel_crtc_state;
> +struct intel_cdclk_state;
> +struct intel_cdclk_vals;
> struct intel_initial_plane_config;
> struct intel_crtc;
> struct intel_limit;
> @@ -282,7 +282,7 @@ struct drm_i915_display_funcs {
> struct intel_crtc *crtc);
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> void (*update_wm)(struct intel_crtc *crtc);
> - int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> + int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
> u8 (*calc_voltage_level)(int cdclk);
> /* Returns the active state of the crtc, and if the crtc is active,
> * fills out the pipe-config with the hw state. */
> @@ -891,33 +891,6 @@ struct i915_selftest_stash {
> atomic_t counter;
> };
>
> -struct intel_cdclk_state {
> - /*
> - * Logical configuration of cdclk (used for all scaling,
> - * watermark, etc. calculations and checks). This is
> - * computed as if all enabled crtcs were active.
> - */
> - struct intel_cdclk_config logical;
> -
> - /*
> - * Actual configuration of cdclk, can be different from the
> - * logical configuration only when all crtc's are DPMS off.
> - */
> - struct intel_cdclk_config actual;
> -
> - /* minimum acceptable cdclk for each pipe */
> - int min_cdclk[I915_MAX_PIPES];
> - /* minimum acceptable voltage level for each pipe */
> - u8 min_voltage_level[I915_MAX_PIPES];
> -
> - /* pipe to which cd2x update is synchronized */
> - enum pipe pipe;
> -
> - /* forced minimum cdclk for glk+ audio w/a */
> - int force_min_cdclk;
> - bool force_min_cdclk_changed;
> -};
> -
> struct drm_i915_private {
> struct drm_device drm;
>
> @@ -1034,18 +1007,14 @@ struct drm_i915_private {
> unsigned int fdi_pll_freq;
> unsigned int czclk_freq;
>
> - /*
> - * For reading holding any crtc lock is sufficient,
> - * for writing must hold all of them.
> - */
> - struct intel_cdclk_state cdclk_state;
> -
> struct {
> /* The current hardware cdclk configuration */
> struct intel_cdclk_config hw;
>
> /* cdclk, divider, and ratio table from bspec */
> const struct intel_cdclk_vals *table;
> +
> + struct intel_global_obj obj;
> } cdclk;
>
> /**
> @@ -1104,8 +1073,8 @@ struct drm_i915_private {
> struct list_head global_obj_list;
>
> /*
> - * For reading active_pipes, cdclk_state holding any crtc
> - * lock is sufficient, for writing must hold all of them.
> + * For reading active_pipes holding any crtc lock is
> + * sufficient, for writing must hold all of them.
> */
> u8 active_pipes;
>
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
@ 2020-01-27 17:11 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-27 17:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Jan 20, 2020 at 07:47:28PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's add a copy of the active_pipes bitmask into the cdclk_state.
> While this is duplicating a bit of information we may already
> have elsewhere, I think it's worth it to decopule the cdclk stuff
> from whatever else wants to use that bitmask. Also we want to get
> rid of all the old ad-hoc global state which is what the current
> bitmask is, so this removes one obstacle.
>
> The one extra thing we have to remember is write locking the cdclk
> state whenever the bitmask changes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 20 +++++++++++---------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +++
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++++---
> 3 files changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index e14bda2bec71..f8e4510f4bd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2125,7 +2125,7 @@ static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> cdclk_state->logical.voltage_level =
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> - if (!state->active_pipes) {
> + if (!cdclk_state->active_pipes) {
> cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
>
> cdclk_state->actual.cdclk = cdclk;
> @@ -2140,7 +2140,6 @@ static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
>
> static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> - struct intel_atomic_state *state = cdclk_state->base.state;
> int min_cdclk, cdclk;
>
> min_cdclk = intel_compute_min_cdclk(cdclk_state);
> @@ -2157,7 +2156,7 @@ static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> cdclk_state->logical.voltage_level =
> bdw_calc_voltage_level(cdclk);
>
> - if (!state->active_pipes) {
> + if (!cdclk_state->active_pipes) {
> cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
>
> cdclk_state->actual.cdclk = cdclk;
> @@ -2209,7 +2208,6 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
>
> static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> - struct intel_atomic_state *state = cdclk_state->base.state;
> int min_cdclk, cdclk, vco;
>
> min_cdclk = intel_compute_min_cdclk(cdclk_state);
> @@ -2229,7 +2227,7 @@ static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> cdclk_state->logical.voltage_level =
> skl_calc_voltage_level(cdclk);
>
> - if (!state->active_pipes) {
> + if (!cdclk_state->active_pipes) {
> cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
>
> cdclk_state->actual.vco = vco;
> @@ -2266,7 +2264,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> max_t(int, min_voltage_level,
> dev_priv->display.calc_voltage_level(cdclk));
>
> - if (!state->active_pipes) {
> + if (!cdclk_state->active_pipes) {
> cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> @@ -2402,6 +2400,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
>
> + new_cdclk_state->active_pipes =
> + intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
> +
> ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> if (ret)
> return ret;
> @@ -2415,7 +2416,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
> if (ret)
> return ret;
> - } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> + } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
> + intel_cdclk_changed(&old_cdclk_state->logical,
> &new_cdclk_state->logical)) {
> ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
> if (ret)
> @@ -2424,14 +2426,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> return 0;
> }
>
> - if (is_power_of_2(state->active_pipes) &&
> + if (is_power_of_2(new_cdclk_state->active_pipes) &&
> intel_cdclk_can_cd2x_update(dev_priv,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
>
> - pipe = ilog2(state->active_pipes);
> + pipe = ilog2(new_cdclk_state->active_pipes);
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>
> crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 195fca70bfcb..df21dbdcc575 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -50,6 +50,9 @@ struct intel_cdclk_state {
> /* forced minimum cdclk for glk+ audio w/a */
> int force_min_cdclk;
> bool force_min_cdclk_changed;
> +
> + /* bitmask of active pipes */
> + u8 active_pipes;
> };
>
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dca100546be8..27878c484307 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7551,6 +7551,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> dev_priv->active_pipes &= ~BIT(pipe);
> cdclk_state->min_cdclk[pipe] = 0;
> cdclk_state->min_voltage_level[pipe] = 0;
> + cdclk_state->active_pipes &= ~BIT(pipe);
>
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> @@ -18120,10 +18121,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_encoder *encoder;
> struct intel_connector *connector;
> struct drm_connector_list_iter conn_iter;
> + u8 active_pipes = 0;
> int i;
>
> - dev_priv->active_pipes = 0;
> -
> for_each_intel_crtc(dev, crtc) {
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> @@ -18139,13 +18139,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> crtc->active = crtc_state->hw.active;
>
> if (crtc_state->hw.active)
> - dev_priv->active_pipes |= BIT(crtc->pipe);
> + active_pipes |= BIT(crtc->pipe);
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
> crtc->base.base.id, crtc->base.name,
> enableddisabled(crtc_state->hw.active));
> }
>
> + dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
> +
> readout_plane_state(dev_priv);
>
> for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH v2 16/17] drm/i915: Convert cdclk to global state
2020-01-27 17:03 ` Imre Deak
@ 2020-01-27 17:15 ` Ville Syrjälä
2020-01-27 17:54 ` Imre Deak
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjälä @ 2020-01-27 17:15 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jan 27, 2020 at 07:03:01PM +0200, Imre Deak wrote:
> On Tue, Jan 21, 2020 at 04:03:53PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Let's convert cdclk_state to be a proper global state. That allows
> > us to use the regular atomic old vs. new state accessor, hopefully
> > making the code less confusing.
> >
> > We do have to deal with a few more error cases in case the cdclk
> > state duplication fails. But so be it.
> >
> > v2: Fix new plane min_cdclk vs. old crtc min_cdclk check
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 68 ++++---
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
> > drivers/gpu/drm/i915/display/intel_audio.c | 39 +++-
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 192 ++++++++++--------
> > drivers/gpu/drm/i915/display/intel_cdclk.h | 45 +++-
> > drivers/gpu/drm/i915/display/intel_display.c | 122 +++++++----
> > .../drm/i915/display/intel_display_types.h | 3 -
> > drivers/gpu/drm/i915/i915_drv.h | 45 +---
> > 9 files changed, 316 insertions(+), 204 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 45842ebcdebd..b51ddf9a250f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -518,7 +518,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> > state->dpll_set = state->modeset = false;
> > state->global_state_changed = false;
> > state->active_pipes = 0;
> > - intel_cdclk_clear_state(state);
> > }
> >
> > struct intel_crtc_state *
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 563caec1d201..230d0e4f6169 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -37,6 +37,7 @@
> >
> > #include "i915_trace.h"
> > #include "intel_atomic_plane.h"
> > +#include "intel_cdclk.h"
> > #include "intel_display_types.h"
> > #include "intel_pm.h"
> > #include "intel_sprite.h"
> > @@ -155,44 +156,61 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> > return cpp * crtc_state->pixel_rate;
> > }
> >
> > -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > - struct intel_plane *plane)
> > +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > + struct intel_plane *plane,
> > + bool *need_cdclk_calc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > - const struct intel_cdclk_state *cdclk_state =
> > - &dev_priv->cdclk_state;
> > const struct intel_plane_state *plane_state =
> > intel_atomic_get_new_plane_state(state, plane);
> > struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
> > - struct intel_crtc_state *crtc_state;
> > + const struct intel_cdclk_state *cdclk_state;
> > + struct intel_crtc_state *new_crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> >
> > if (!plane_state->uapi.visible || !plane->min_cdclk)
> > - return false;
> > + return 0;
> > +
> > + new_crtc_state->min_cdclk[plane->id] =
> > + plane->min_cdclk(new_crtc_state, plane_state);
> >
> > - crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > + /*
> > + * No need to check against the cdclk state if
> > + * the min cdclk for the plane doesn't increase.
> > + *
> > + * Ie. we only ever increase the cdclk due to plane
> > + * requirements. This can reduce back and forth
> > + * display blinking due to constant cdclk changes.
> > + */
> > + if (new_crtc_state->min_cdclk[plane->id] <=
> > + old_crtc_state->min_cdclk[plane->id])
> > + return 0;
> >
> > - crtc_state->min_cdclk[plane->id] =
> > - plane->min_cdclk(crtc_state, plane_state);
> > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(cdclk_state))
> > + return PTR_ERR(cdclk_state);
> >
> > /*
> > - * Does the cdclk need to be bumbed up?
> > + * No need to recalculate the cdclk state if
> > + * the min cdclk for the pipe doesn't increase.
> > *
> > - * Note: we obviously need to be called before the new
> > - * cdclk frequency is calculated so state->cdclk.logical
> > - * hasn't been populated yet. Hence we look at the old
> > - * cdclk state under dev_priv->cdclk.logical. This is
> > - * safe as long we hold at least one crtc mutex (which
> > - * must be true since we have crtc_state).
> > + * Ie. we only ever increase the cdclk due to plane
> > + * requirements. This can reduce back and forth
> > + * display blinking due to constant cdclk changes.
> > */
> > - if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
> > - DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
> > - plane->base.base.id, plane->base.name,
> > - crtc_state->min_cdclk[plane->id],
> > - cdclk_state->logical.cdclk);
> > - return true;
> > - }
> > + if (new_crtc_state->min_cdclk[plane->id] <=
> > + cdclk_state->min_cdclk[crtc->pipe])
> > + return 0;
> > +
> > + DRM_DEBUG_KMS("[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
> > + plane->base.base.id, plane->base.name,
> > + new_crtc_state->min_cdclk[plane->id],
> > + crtc->base.base.id, crtc->base.name,
> > + cdclk_state->min_cdclk[crtc->pipe]);
> > + *need_cdclk_calc = true;
> >
> > - return false;
> > + return 0;
> > }
> >
> > static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index 5cedafdddb55..2bcf15e34728 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > @@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> > struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *old_plane_state,
> > struct intel_plane_state *plane_state);
> > -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > - struct intel_plane *plane);
> > +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > + struct intel_plane *plane,
> > + bool *need_cdclk_calc);
> >
> > #endif /* __INTEL_ATOMIC_PLANE_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 12626fd94d29..9debac75eaec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -30,6 +30,7 @@
> > #include "i915_drv.h"
> > #include "intel_atomic.h"
> > #include "intel_audio.h"
> > +#include "intel_cdclk.h"
> > #include "intel_display_types.h"
> > #include "intel_lpe_audio.h"
> >
> > @@ -800,6 +801,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
> > + bool enable)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_cdclk_state *cdclk_state;
> > + struct intel_crtc *crtc;
> > + int ret;
> > +
> > + /* need to hold at least one crtc lock for the global state */
> > + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > + ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
> > + if (ret)
> > + return ret;
>
> Nit: couldn't intel_atomic_lock_global_state() be moved earlier instead
> of the above?
Chicken vs. egg. We don't have the state yet to write lock it,
and we're not allowed to get it without holding a read lock.
Well, I suppose technically we could get it without holding a
read lock in this specific case, but I didn't want encourage
that kind of abuse and so attempting it would trigger a WARN.
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> > +
> > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(cdclk_state))
> > + return PTR_ERR(cdclk_state);
> > +
> > + cdclk_state->force_min_cdclk_changed = true;
> > + cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
> > +
> > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > + if (ret)
> > + return ret;
> > +
> > + return drm_atomic_commit(&state->base);
> > +}
> > +
> > static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> > bool enable)
> > {
> > @@ -815,15 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> > state->acquire_ctx = &ctx;
> >
> > retry:
> > - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
> > - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
> > - enable ? 2 * 96000 : 0;
> > -
> > - /* Protects dev_priv->cdclk.force_min_cdclk */
> > - ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> > - if (!ret)
> > - ret = drm_atomic_commit(state);
> > -
> > + ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
> > if (ret == -EDEADLK) {
> > drm_atomic_state_clear(state);
> > drm_modeset_backoff(&ctx);
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 3b7932ae2a77..e14bda2bec71 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1807,37 +1807,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> > a->voltage_level != b->voltage_level;
> > }
> >
> > -/**
> > - * intel_cdclk_clear_state - clear the cdclk state
> > - * @state: atomic state
> > - *
> > - * Clear the cdclk state for ww_mutex backoff.
> > - */
> > -void intel_cdclk_clear_state(struct intel_atomic_state *state)
> > -{
> > - memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
> > - state->cdclk_state.pipe = INVALID_PIPE;
> > -}
> > -
> > -/**
> > - * intel_cdclk_swap_state - make atomic CDCLK configuration effective
> > - * @state: atomic state
> > - *
> > - * This is the CDCLK version of drm_atomic_helper_swap_state() since the
> > - * helper does not handle driver-specific global state.
> > - *
> > - * Similarly to the atomic helpers this function does a complete swap,
> > - * i.e. it also puts the old state into @state. This is used by the commit
> > - * code to determine how CDCLK has changed (for instance did it increase or
> > - * decrease).
> > - */
> > -void intel_cdclk_swap_state(struct intel_atomic_state *state)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > -
> > - swap(state->cdclk_state, dev_priv->cdclk_state);
> > -}
> > -
> > void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> > const char *context)
> > {
> > @@ -1888,14 +1857,22 @@ void
> > intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - /* called after intel_cdclk_swap_state()! */
> > - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> > - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> > + const struct intel_cdclk_state *old_cdclk_state =
> > + intel_atomic_get_old_cdclk_state(state);
> > + const struct intel_cdclk_state *new_cdclk_state =
> > + intel_atomic_get_new_cdclk_state(state);
> > enum pipe pipe = new_cdclk_state->pipe;
> >
> > + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> > + &new_cdclk_state->actual))
> > + return;
> > +
> > if (pipe == INVALID_PIPE ||
> > - old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
> > + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> > + WARN_ON(!new_cdclk_state->base.changed);
> > +
> > intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> > + }
> > }
> >
> > /**
> > @@ -1909,14 +1886,22 @@ void
> > intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - /* called after intel_cdclk_swap_state()! */
> > - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> > - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> > + const struct intel_cdclk_state *old_cdclk_state =
> > + intel_atomic_get_old_cdclk_state(state);
> > + const struct intel_cdclk_state *new_cdclk_state =
> > + intel_atomic_get_new_cdclk_state(state);
> > enum pipe pipe = new_cdclk_state->pipe;
> >
> > + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> > + &new_cdclk_state->actual))
> > + return;
> > +
> > if (pipe != INVALID_PIPE &&
> > - old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
> > + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
> > + WARN_ON(!new_cdclk_state->base.changed);
> > +
> > intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> > + }
> > }
> >
> > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > @@ -2042,10 +2027,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> > return min_cdclk;
> > }
> >
> > -static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> > +static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *crtc_state;
> > int min_cdclk, i;
> > @@ -2063,7 +2048,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> >
> > cdclk_state->min_cdclk[i] = min_cdclk;
> >
> > - ret = _intel_atomic_lock_global_state(state);
> > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > if (ret)
> > return ret;
> > }
> > @@ -2088,10 +2073,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> > * future platforms this code will need to be
> > * adjusted.
> > */
> > -static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> > +static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
> > {
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *crtc_state;
> > u8 min_voltage_level;
> > @@ -2111,7 +2096,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> >
> > cdclk_state->min_voltage_level[i] = min_voltage_level;
> >
> > - ret = _intel_atomic_lock_global_state(state);
> > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > if (ret)
> > return ret;
> > }
> > @@ -2124,13 +2109,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> > return min_voltage_level;
> > }
> >
> > -static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> > +static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > int min_cdclk, cdclk;
> >
> > - min_cdclk = intel_compute_min_cdclk(state);
> > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > if (min_cdclk < 0)
> > return min_cdclk;
> >
> > @@ -2153,12 +2138,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> > return 0;
> > }
> >
> > -static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> > +static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > int min_cdclk, cdclk;
> >
> > - min_cdclk = intel_compute_min_cdclk(state);
> > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > if (min_cdclk < 0)
> > return min_cdclk;
> >
> > @@ -2185,10 +2170,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> > return 0;
> > }
> >
> > -static int skl_dpll0_vco(struct intel_atomic_state *state)
> > +static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
> > {
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *crtc_state;
> > int vco, i;
> > @@ -2222,16 +2207,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
> > return vco;
> > }
> >
> > -static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> > +static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > int min_cdclk, cdclk, vco;
> >
> > - min_cdclk = intel_compute_min_cdclk(state);
> > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > if (min_cdclk < 0)
> > return min_cdclk;
> >
> > - vco = skl_dpll0_vco(state);
> > + vco = skl_dpll0_vco(cdclk_state);
> >
> > /*
> > * FIXME should also account for plane ratio
> > @@ -2258,17 +2243,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> > return 0;
> > }
> >
> > -static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> > +static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > + struct intel_atomic_state *state = cdclk_state->base.state;
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > int min_cdclk, min_voltage_level, cdclk, vco;
> >
> > - min_cdclk = intel_compute_min_cdclk(state);
> > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > if (min_cdclk < 0)
> > return min_cdclk;
> >
> > - min_voltage_level = bxt_compute_min_voltage_level(state);
> > + min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
> > if (min_voltage_level < 0)
> > return min_voltage_level;
> >
> > @@ -2335,7 +2320,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> > return 0;
> > }
> >
> > -static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> > +static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > {
> > int min_cdclk;
> >
> > @@ -2344,54 +2329,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> > * check that the required minimum frequency doesn't exceed
> > * the actual cdclk frequency.
> > */
> > - min_cdclk = intel_compute_min_cdclk(state);
> > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > if (min_cdclk < 0)
> > return min_cdclk;
> >
> > return 0;
> > }
> >
> > +static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
> > +{
> > + struct intel_cdclk_state *cdclk_state;
> > +
> > + cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
> > + if (!cdclk_state)
> > + return NULL;
> > +
> > + cdclk_state->force_min_cdclk_changed = false;
> > + cdclk_state->pipe = INVALID_PIPE;
> > +
> > + return &cdclk_state->base;
> > +}
> > +
> > +static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
> > + struct intel_global_state *state)
> > +{
> > + kfree(state);
> > +}
> > +
> > +static const struct intel_global_state_funcs intel_cdclk_funcs = {
> > + .atomic_duplicate_state = intel_cdclk_duplicate_state,
> > + .atomic_destroy_state = intel_cdclk_destroy_state,
> > +};
> > +
> > +struct intel_cdclk_state *
> > +intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *cdclk_state;
> > +
> > + cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
> > + if (IS_ERR(cdclk_state))
> > + return ERR_CAST(cdclk_state);
> > +
> > + return to_intel_cdclk_state(cdclk_state);
> > +}
> > +
> > +int intel_cdclk_init(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state *cdclk_state;
> > +
> > + cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
> > + if (!cdclk_state)
> > + return -ENOMEM;
> > +
> > + intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
> > + &cdclk_state->base, &intel_cdclk_funcs);
> > +
> > + return 0;
> > +}
> > +
> > int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
> > - struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
> > + const struct intel_cdclk_state *old_cdclk_state;
> > + struct intel_cdclk_state *new_cdclk_state;
> > enum pipe pipe;
> > int ret;
> >
> > - memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
> > - sizeof(new_cdclk_state->min_cdclk));
> > - memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
> > - sizeof(new_cdclk_state->min_voltage_level));
> > + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(new_cdclk_state))
> > + return PTR_ERR(new_cdclk_state);
> >
> > - /* keep the current setting */
> > - if (!new_cdclk_state->force_min_cdclk_changed)
> > - new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
> > + old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
> >
> > - new_cdclk_state->logical = old_cdclk_state->logical;
> > - new_cdclk_state->actual = old_cdclk_state->actual;
> > -
> > - ret = dev_priv->display.modeset_calc_cdclk(state);
> > + ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> > if (ret)
> > return ret;
> >
> > - /*
> > - * Writes to dev_priv->cdclk.{actual,logical} must protected
> > - * by holding all the crtc mutexes even if we don't end up
> > - * touching the hardware
> > - */
> > if (intel_cdclk_changed(&old_cdclk_state->actual,
> > &new_cdclk_state->actual)) {
> > /*
> > * Also serialize commits across all crtcs
> > * if the actual hw needs to be poked.
> > */
> > - ret = _intel_atomic_serialize_global_state(state);
> > + ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
> > if (ret)
> > return ret;
> > } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> > &new_cdclk_state->logical)) {
> > - ret = _intel_atomic_lock_global_state(state);
> > + ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
> > if (ret)
> > return ret;
> > } else {
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > index 4b965db07720..195fca70bfcb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > @@ -8,11 +8,12 @@
> >
> > #include <linux/types.h>
> >
> > +#include "i915_drv.h"
> > #include "intel_display.h"
> > +#include "intel_global_state.h"
> >
> > struct drm_i915_private;
> > struct intel_atomic_state;
> > -struct intel_cdclk_config;
> > struct intel_crtc_state;
> >
> > struct intel_cdclk_vals {
> > @@ -22,6 +23,35 @@ struct intel_cdclk_vals {
> > u8 ratio;
> > };
> >
> > +struct intel_cdclk_state {
> > + struct intel_global_state base;
> > +
> > + /*
> > + * Logical configuration of cdclk (used for all scaling,
> > + * watermark, etc. calculations and checks). This is
> > + * computed as if all enabled crtcs were active.
> > + */
> > + struct intel_cdclk_config logical;
> > +
> > + /*
> > + * Actual configuration of cdclk, can be different from the
> > + * logical configuration only when all crtc's are DPMS off.
> > + */
> > + struct intel_cdclk_config actual;
> > +
> > + /* minimum acceptable cdclk for each pipe */
> > + int min_cdclk[I915_MAX_PIPES];
> > + /* minimum acceptable voltage level for each pipe */
> > + u8 min_voltage_level[I915_MAX_PIPES];
> > +
> > + /* pipe to which cd2x update is synchronized */
> > + enum pipe pipe;
> > +
> > + /* forced minimum cdclk for glk+ audio w/a */
> > + int force_min_cdclk;
> > + bool force_min_cdclk_changed;
> > +};
> > +
> > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> > void intel_cdclk_init_hw(struct drm_i915_private *i915);
> > void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> > @@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > void intel_update_rawclk(struct drm_i915_private *dev_priv);
> > bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> > const struct intel_cdclk_config *b);
> > -void intel_cdclk_clear_state(struct intel_atomic_state *state);
> > -void intel_cdclk_swap_state(struct intel_atomic_state *state);
> > void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> > void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> > void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> > const char *context);
> > int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
> >
> > +struct intel_cdclk_state *
> > +intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
> > +
> > +#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
> > +#define intel_atomic_get_old_cdclk_state(state) \
> > + to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> > +#define intel_atomic_get_new_cdclk_state(state) \
> > + to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> > +
> > +int intel_cdclk_init(struct drm_i915_private *dev_priv);
> > +
> > #endif /* __INTEL_CDCLK_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index dc767efffd9a..dca100546be8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7482,7 +7482,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> > struct intel_bw_state *bw_state =
> > to_intel_bw_state(dev_priv->bw_obj.state);
> > struct intel_cdclk_state *cdclk_state =
> > - &dev_priv->cdclk_state;
> > + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> > struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> > enum intel_display_power_domain domain;
> > @@ -7780,17 +7780,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > -static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > +static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv =
> > to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_atomic_state *intel_state =
> > + struct intel_atomic_state *state =
> > to_intel_atomic_state(crtc_state->uapi.state);
> > - const struct intel_cdclk_state *cdclk_state =
> > - &intel_state->cdclk_state;
> > +
> > + crtc_state->ips_enabled = false;
> >
> > if (!hsw_crtc_state_ips_capable(crtc_state))
> > - return false;
> > + return 0;
> >
> > /*
> > * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> > @@ -7799,18 +7799,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > * completely disable it.
> > */
> > if (crtc_state->crc_enabled)
> > - return false;
> > + return 0;
> >
> > /* IPS should be fine as long as at least one plane is enabled. */
> > if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
> > - return false;
> > + return 0;
> >
> > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > - if (IS_BROADWELL(dev_priv) &&
> > - crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> > - return false;
> > + if (IS_BROADWELL(dev_priv)) {
> > + const struct intel_cdclk_state *cdclk_state;
> >
> > - return true;
> > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(cdclk_state))
> > + return PTR_ERR(cdclk_state);
> > +
> > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > + if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> > + return 0;
> > + }
> > +
> > + crtc_state->ips_enabled = true;
> > +
> > + return 0;
> > }
> >
> > static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> > @@ -12543,14 +12552,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> > adjusted_mode->crtc_clock);
> > }
> >
> > -static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
> > +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
> > + const struct intel_cdclk_state *cdclk_state)
> > {
> > - const struct intel_atomic_state *state =
> > - to_intel_atomic_state(crtc_state->uapi.state);
> > const struct drm_display_mode *adjusted_mode =
> > &crtc_state->hw.adjusted_mode;
> > - const struct intel_cdclk_state *cdclk_state =
> > - &state->cdclk_state;
> >
> > if (!crtc_state->hw.enable)
> > return 0;
> > @@ -12580,6 +12586,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
> > return linetime_wm;
> > }
> >
> > +static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct intel_cdclk_state *cdclk_state;
> > +
> > + if (INTEL_GEN(dev_priv) >= 9)
> > + crtc_state->linetime = skl_linetime_wm(crtc_state);
> > + else
> > + crtc_state->linetime = hsw_linetime_wm(crtc_state);
> > +
> > + if (!hsw_crtc_supports_ips(crtc))
> > + return 0;
> > +
> > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(cdclk_state))
> > + return PTR_ERR(cdclk_state);
> > +
> > + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
> > + cdclk_state);
> > +
> > + return 0;
> > +}
> > +
> > static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -12615,7 +12647,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > return ret;
> > }
> >
> > - ret = 0;
> > if (dev_priv->display.compute_pipe_wm) {
> > ret = dev_priv->display.compute_pipe_wm(crtc_state);
> > if (ret) {
> > @@ -12646,20 +12677,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > if (!ret)
> > ret = intel_atomic_setup_scalers(dev_priv, crtc,
> > crtc_state);
> > + if (ret)
> > + return ret;
> > }
> >
> > - if (HAS_IPS(dev_priv))
> > - crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
> > + if (HAS_IPS(dev_priv)) {
> > + ret = hsw_compute_ips_config(crtc_state);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (INTEL_GEN(dev_priv) >= 9 ||
> > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > + ret = hsw_compute_linetime_wm(state, crtc);
> > + if (ret)
> > + return ret;
> >
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - crtc_state->linetime = skl_linetime_wm(crtc_state);
> > - } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > - crtc_state->linetime = hsw_linetime_wm(crtc_state);
> > - if (hsw_crtc_supports_ips(crtc))
> > - crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
> > }
> >
> > - return ret;
> > + return 0;
> > }
> >
> > static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> > @@ -14478,7 +14514,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
> > }
> >
> > static int intel_atomic_check_planes(struct intel_atomic_state *state,
> > - bool *need_modeset)
> > + bool *need_cdclk_calc)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > @@ -14532,8 +14568,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
> > * affected planes are part of the state. We can now
> > * compute the minimum cdclk for each plane.
> > */
> > - for_each_new_intel_plane_in_state(state, plane, plane_state, i)
> > - *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
> > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > + ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
> > + if (ret)
> > + return ret;
> > + }
> >
> > return 0;
> > }
> > @@ -14654,6 +14693,7 @@ static int intel_atomic_check(struct drm_device *dev,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_atomic_state *state = to_intel_atomic_state(_state);
> > struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > + struct intel_cdclk_state *new_cdclk_state;
> > struct intel_crtc *crtc;
> > int ret, i;
> > bool any_ms = false;
> > @@ -14766,18 +14806,18 @@ static int intel_atomic_check(struct drm_device *dev,
> > if (ret)
> > goto fail;
> >
> > - any_ms |= state->cdclk_state.force_min_cdclk_changed;
> > -
> > ret = intel_atomic_check_planes(state, &any_ms);
> > if (ret)
> > goto fail;
> >
> > + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> > + if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
> > + any_ms = true;
> > +
> > if (any_ms) {
> > ret = intel_modeset_checks(state);
> > if (ret)
> > goto fail;
> > - } else {
> > - state->cdclk_state.logical = dev_priv->cdclk_state.logical;
> > }
> >
> > ret = intel_atomic_check_crtcs(state);
> > @@ -15676,8 +15716,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > assert_global_state_locked(dev_priv);
> >
> > dev_priv->active_pipes = state->active_pipes;
> > -
> > - intel_cdclk_swap_state(state);
> > }
> >
> > drm_atomic_state_get(&state->base);
> > @@ -17356,7 +17394,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> > void intel_modeset_init_hw(struct drm_i915_private *i915)
> > {
> > struct intel_cdclk_state *cdclk_state =
> > - &i915->cdclk_state;
> > + to_intel_cdclk_state(i915->cdclk.obj.state);
> >
> > intel_update_cdclk(i915);
> > intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
> > @@ -17587,6 +17625,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
> >
> > intel_mode_config_init(i915);
> >
> > + ret = intel_cdclk_init(i915);
> > + if (ret)
> > + return ret;
> > +
> > ret = intel_bw_init(i915);
> > if (ret)
> > return ret;
> > @@ -18071,6 +18113,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
> > static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_cdclk_state *cdclk_state =
> > + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> > enum pipe pipe;
> > struct intel_crtc *crtc;
> > struct intel_encoder *encoder;
> > @@ -18190,8 +18234,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > for_each_intel_crtc(dev, crtc) {
> > struct intel_bw_state *bw_state =
> > to_intel_bw_state(dev_priv->bw_obj.state);
> > - struct intel_cdclk_state *cdclk_state =
> > - &dev_priv->cdclk_state;
> > struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> > struct intel_plane *plane;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 628c4a56a9e9..524b6d5235ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -465,8 +465,6 @@ struct intel_atomic_state {
> > struct __intel_global_objs_state *global_objs;
> > int num_global_objs;
> >
> > - struct intel_cdclk_state cdclk_state;
> > -
> > bool dpll_set, modeset;
> >
> > /*
> > @@ -493,7 +491,6 @@ struct intel_atomic_state {
> >
> > /*
> > * active_pipes
> > - * cdclk_state
> > */
> > bool global_state_changed;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 63cda89a4e62..2e6b149478c1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -65,7 +65,6 @@
> > #include "i915_utils.h"
> >
> > #include "display/intel_bios.h"
> > -#include "display/intel_cdclk.h"
> > #include "display/intel_display.h"
> > #include "display/intel_display_power.h"
> > #include "display/intel_dpll_mgr.h"
> > @@ -258,7 +257,8 @@ struct intel_connector;
> > struct intel_encoder;
> > struct intel_atomic_state;
> > struct intel_cdclk_config;
> > -struct intel_crtc_state;
> > +struct intel_cdclk_state;
> > +struct intel_cdclk_vals;
> > struct intel_initial_plane_config;
> > struct intel_crtc;
> > struct intel_limit;
> > @@ -282,7 +282,7 @@ struct drm_i915_display_funcs {
> > struct intel_crtc *crtc);
> > int (*compute_global_watermarks)(struct intel_atomic_state *state);
> > void (*update_wm)(struct intel_crtc *crtc);
> > - int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> > + int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
> > u8 (*calc_voltage_level)(int cdclk);
> > /* Returns the active state of the crtc, and if the crtc is active,
> > * fills out the pipe-config with the hw state. */
> > @@ -891,33 +891,6 @@ struct i915_selftest_stash {
> > atomic_t counter;
> > };
> >
> > -struct intel_cdclk_state {
> > - /*
> > - * Logical configuration of cdclk (used for all scaling,
> > - * watermark, etc. calculations and checks). This is
> > - * computed as if all enabled crtcs were active.
> > - */
> > - struct intel_cdclk_config logical;
> > -
> > - /*
> > - * Actual configuration of cdclk, can be different from the
> > - * logical configuration only when all crtc's are DPMS off.
> > - */
> > - struct intel_cdclk_config actual;
> > -
> > - /* minimum acceptable cdclk for each pipe */
> > - int min_cdclk[I915_MAX_PIPES];
> > - /* minimum acceptable voltage level for each pipe */
> > - u8 min_voltage_level[I915_MAX_PIPES];
> > -
> > - /* pipe to which cd2x update is synchronized */
> > - enum pipe pipe;
> > -
> > - /* forced minimum cdclk for glk+ audio w/a */
> > - int force_min_cdclk;
> > - bool force_min_cdclk_changed;
> > -};
> > -
> > struct drm_i915_private {
> > struct drm_device drm;
> >
> > @@ -1034,18 +1007,14 @@ struct drm_i915_private {
> > unsigned int fdi_pll_freq;
> > unsigned int czclk_freq;
> >
> > - /*
> > - * For reading holding any crtc lock is sufficient,
> > - * for writing must hold all of them.
> > - */
> > - struct intel_cdclk_state cdclk_state;
> > -
> > struct {
> > /* The current hardware cdclk configuration */
> > struct intel_cdclk_config hw;
> >
> > /* cdclk, divider, and ratio table from bspec */
> > const struct intel_cdclk_vals *table;
> > +
> > + struct intel_global_obj obj;
> > } cdclk;
> >
> > /**
> > @@ -1104,8 +1073,8 @@ struct drm_i915_private {
> > struct list_head global_obj_list;
> >
> > /*
> > - * For reading active_pipes, cdclk_state holding any crtc
> > - * lock is sufficient, for writing must hold all of them.
> > + * For reading active_pipes holding any crtc lock is
> > + * sufficient, for writing must hold all of them.
> > */
> > u8 active_pipes;
> >
> > --
> > 2.24.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH v2 16/17] drm/i915: Convert cdclk to global state
2020-01-27 17:15 ` Ville Syrjälä
@ 2020-01-27 17:54 ` Imre Deak
0 siblings, 0 replies; 48+ messages in thread
From: Imre Deak @ 2020-01-27 17:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jan 27, 2020 at 07:15:06PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 27, 2020 at 07:03:01PM +0200, Imre Deak wrote:
> > On Tue, Jan 21, 2020 at 04:03:53PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Let's convert cdclk_state to be a proper global state. That allows
> > > us to use the regular atomic old vs. new state accessor, hopefully
> > > making the code less confusing.
> > >
> > > We do have to deal with a few more error cases in case the cdclk
> > > state duplication fails. But so be it.
> > >
> > > v2: Fix new plane min_cdclk vs. old crtc min_cdclk check
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
> > > .../gpu/drm/i915/display/intel_atomic_plane.c | 68 ++++---
> > > .../gpu/drm/i915/display/intel_atomic_plane.h | 5 +-
> > > drivers/gpu/drm/i915/display/intel_audio.c | 39 +++-
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 192 ++++++++++--------
> > > drivers/gpu/drm/i915/display/intel_cdclk.h | 45 +++-
> > > drivers/gpu/drm/i915/display/intel_display.c | 122 +++++++----
> > > .../drm/i915/display/intel_display_types.h | 3 -
> > > drivers/gpu/drm/i915/i915_drv.h | 45 +---
> > > 9 files changed, 316 insertions(+), 204 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index 45842ebcdebd..b51ddf9a250f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -518,7 +518,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> > > state->dpll_set = state->modeset = false;
> > > state->global_state_changed = false;
> > > state->active_pipes = 0;
> > > - intel_cdclk_clear_state(state);
> > > }
> > >
> > > struct intel_crtc_state *
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 563caec1d201..230d0e4f6169 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -37,6 +37,7 @@
> > >
> > > #include "i915_trace.h"
> > > #include "intel_atomic_plane.h"
> > > +#include "intel_cdclk.h"
> > > #include "intel_display_types.h"
> > > #include "intel_pm.h"
> > > #include "intel_sprite.h"
> > > @@ -155,44 +156,61 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> > > return cpp * crtc_state->pixel_rate;
> > > }
> > >
> > > -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > > - struct intel_plane *plane)
> > > +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > > + struct intel_plane *plane,
> > > + bool *need_cdclk_calc)
> > > {
> > > - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > - const struct intel_cdclk_state *cdclk_state =
> > > - &dev_priv->cdclk_state;
> > > const struct intel_plane_state *plane_state =
> > > intel_atomic_get_new_plane_state(state, plane);
> > > struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
> > > - struct intel_crtc_state *crtc_state;
> > > + const struct intel_cdclk_state *cdclk_state;
> > > + struct intel_crtc_state *new_crtc_state =
> > > + intel_atomic_get_new_crtc_state(state, crtc);
> > > + const struct intel_crtc_state *old_crtc_state =
> > > + intel_atomic_get_old_crtc_state(state, crtc);
> > >
> > > if (!plane_state->uapi.visible || !plane->min_cdclk)
> > > - return false;
> > > + return 0;
> > > +
> > > + new_crtc_state->min_cdclk[plane->id] =
> > > + plane->min_cdclk(new_crtc_state, plane_state);
> > >
> > > - crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > > + /*
> > > + * No need to check against the cdclk state if
> > > + * the min cdclk for the plane doesn't increase.
> > > + *
> > > + * Ie. we only ever increase the cdclk due to plane
> > > + * requirements. This can reduce back and forth
> > > + * display blinking due to constant cdclk changes.
> > > + */
> > > + if (new_crtc_state->min_cdclk[plane->id] <=
> > > + old_crtc_state->min_cdclk[plane->id])
> > > + return 0;
> > >
> > > - crtc_state->min_cdclk[plane->id] =
> > > - plane->min_cdclk(crtc_state, plane_state);
> > > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > > + if (IS_ERR(cdclk_state))
> > > + return PTR_ERR(cdclk_state);
> > >
> > > /*
> > > - * Does the cdclk need to be bumbed up?
> > > + * No need to recalculate the cdclk state if
> > > + * the min cdclk for the pipe doesn't increase.
> > > *
> > > - * Note: we obviously need to be called before the new
> > > - * cdclk frequency is calculated so state->cdclk.logical
> > > - * hasn't been populated yet. Hence we look at the old
> > > - * cdclk state under dev_priv->cdclk.logical. This is
> > > - * safe as long we hold at least one crtc mutex (which
> > > - * must be true since we have crtc_state).
> > > + * Ie. we only ever increase the cdclk due to plane
> > > + * requirements. This can reduce back and forth
> > > + * display blinking due to constant cdclk changes.
> > > */
> > > - if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
> > > - DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
> > > - plane->base.base.id, plane->base.name,
> > > - crtc_state->min_cdclk[plane->id],
> > > - cdclk_state->logical.cdclk);
> > > - return true;
> > > - }
> > > + if (new_crtc_state->min_cdclk[plane->id] <=
> > > + cdclk_state->min_cdclk[crtc->pipe])
> > > + return 0;
> > > +
> > > + DRM_DEBUG_KMS("[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
> > > + plane->base.base.id, plane->base.name,
> > > + new_crtc_state->min_cdclk[plane->id],
> > > + crtc->base.base.id, crtc->base.name,
> > > + cdclk_state->min_cdclk[crtc->pipe]);
> > > + *need_cdclk_calc = true;
> > >
> > > - return false;
> > > + return 0;
> > > }
> > >
> > > static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > > index 5cedafdddb55..2bcf15e34728 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > > @@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> > > struct intel_crtc_state *crtc_state,
> > > const struct intel_plane_state *old_plane_state,
> > > struct intel_plane_state *plane_state);
> > > -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > > - struct intel_plane *plane);
> > > +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > > + struct intel_plane *plane,
> > > + bool *need_cdclk_calc);
> > >
> > > #endif /* __INTEL_ATOMIC_PLANE_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> > > index 12626fd94d29..9debac75eaec 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > > @@ -30,6 +30,7 @@
> > > #include "i915_drv.h"
> > > #include "intel_atomic.h"
> > > #include "intel_audio.h"
> > > +#include "intel_cdclk.h"
> > > #include "intel_display_types.h"
> > > #include "intel_lpe_audio.h"
> > >
> > > @@ -800,6 +801,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
> > > + bool enable)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + struct intel_cdclk_state *cdclk_state;
> > > + struct intel_crtc *crtc;
> > > + int ret;
> > > +
> > > + /* need to hold at least one crtc lock for the global state */
> > > + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > > + ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
> > > + if (ret)
> > > + return ret;
> >
> > Nit: couldn't intel_atomic_lock_global_state() be moved earlier instead
> > of the above?
>
> Chicken vs. egg. We don't have the state yet to write lock it,
> and we're not allowed to get it without holding a read lock.
> Well, I suppose technically we could get it without holding a
> read lock in this specific case, but I didn't want encourage
> that kind of abuse and so attempting it would trigger a WARN.
Ah right, global state doesn't have its own lock.
>
> >
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > > +
> > > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > > + if (IS_ERR(cdclk_state))
> > > + return PTR_ERR(cdclk_state);
> > > +
> > > + cdclk_state->force_min_cdclk_changed = true;
> > > + cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
> > > +
> > > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return drm_atomic_commit(&state->base);
> > > +}
> > > +
> > > static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> > > bool enable)
> > > {
> > > @@ -815,15 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> > > state->acquire_ctx = &ctx;
> > >
> > > retry:
> > > - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
> > > - to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
> > > - enable ? 2 * 96000 : 0;
> > > -
> > > - /* Protects dev_priv->cdclk.force_min_cdclk */
> > > - ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
> > > - if (!ret)
> > > - ret = drm_atomic_commit(state);
> > > -
> > > + ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
> > > if (ret == -EDEADLK) {
> > > drm_atomic_state_clear(state);
> > > drm_modeset_backoff(&ctx);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index 3b7932ae2a77..e14bda2bec71 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -1807,37 +1807,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> > > a->voltage_level != b->voltage_level;
> > > }
> > >
> > > -/**
> > > - * intel_cdclk_clear_state - clear the cdclk state
> > > - * @state: atomic state
> > > - *
> > > - * Clear the cdclk state for ww_mutex backoff.
> > > - */
> > > -void intel_cdclk_clear_state(struct intel_atomic_state *state)
> > > -{
> > > - memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
> > > - state->cdclk_state.pipe = INVALID_PIPE;
> > > -}
> > > -
> > > -/**
> > > - * intel_cdclk_swap_state - make atomic CDCLK configuration effective
> > > - * @state: atomic state
> > > - *
> > > - * This is the CDCLK version of drm_atomic_helper_swap_state() since the
> > > - * helper does not handle driver-specific global state.
> > > - *
> > > - * Similarly to the atomic helpers this function does a complete swap,
> > > - * i.e. it also puts the old state into @state. This is used by the commit
> > > - * code to determine how CDCLK has changed (for instance did it increase or
> > > - * decrease).
> > > - */
> > > -void intel_cdclk_swap_state(struct intel_atomic_state *state)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > -
> > > - swap(state->cdclk_state, dev_priv->cdclk_state);
> > > -}
> > > -
> > > void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> > > const char *context)
> > > {
> > > @@ -1888,14 +1857,22 @@ void
> > > intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - /* called after intel_cdclk_swap_state()! */
> > > - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> > > - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> > > + const struct intel_cdclk_state *old_cdclk_state =
> > > + intel_atomic_get_old_cdclk_state(state);
> > > + const struct intel_cdclk_state *new_cdclk_state =
> > > + intel_atomic_get_new_cdclk_state(state);
> > > enum pipe pipe = new_cdclk_state->pipe;
> > >
> > > + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> > > + &new_cdclk_state->actual))
> > > + return;
> > > +
> > > if (pipe == INVALID_PIPE ||
> > > - old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
> > > + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> > > + WARN_ON(!new_cdclk_state->base.changed);
> > > +
> > > intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> > > + }
> > > }
> > >
> > > /**
> > > @@ -1909,14 +1886,22 @@ void
> > > intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - /* called after intel_cdclk_swap_state()! */
> > > - const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
> > > - const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
> > > + const struct intel_cdclk_state *old_cdclk_state =
> > > + intel_atomic_get_old_cdclk_state(state);
> > > + const struct intel_cdclk_state *new_cdclk_state =
> > > + intel_atomic_get_new_cdclk_state(state);
> > > enum pipe pipe = new_cdclk_state->pipe;
> > >
> > > + if (!intel_cdclk_changed(&old_cdclk_state->actual,
> > > + &new_cdclk_state->actual))
> > > + return;
> > > +
> > > if (pipe != INVALID_PIPE &&
> > > - old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
> > > + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
> > > + WARN_ON(!new_cdclk_state->base.changed);
> > > +
> > > intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
> > > + }
> > > }
> > >
> > > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > > @@ -2042,10 +2027,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> > > return min_cdclk;
> > > }
> > >
> > > -static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> > > +static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > struct intel_crtc *crtc;
> > > struct intel_crtc_state *crtc_state;
> > > int min_cdclk, i;
> > > @@ -2063,7 +2048,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> > >
> > > cdclk_state->min_cdclk[i] = min_cdclk;
> > >
> > > - ret = _intel_atomic_lock_global_state(state);
> > > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > > if (ret)
> > > return ret;
> > > }
> > > @@ -2088,10 +2073,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> > > * future platforms this code will need to be
> > > * adjusted.
> > > */
> > > -static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> > > +static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
> > > {
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > struct intel_crtc *crtc;
> > > struct intel_crtc_state *crtc_state;
> > > u8 min_voltage_level;
> > > @@ -2111,7 +2096,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> > >
> > > cdclk_state->min_voltage_level[i] = min_voltage_level;
> > >
> > > - ret = _intel_atomic_lock_global_state(state);
> > > + ret = intel_atomic_lock_global_state(&cdclk_state->base);
> > > if (ret)
> > > return ret;
> > > }
> > > @@ -2124,13 +2109,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> > > return min_voltage_level;
> > > }
> > >
> > > -static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > +static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > int min_cdclk, cdclk;
> > >
> > > - min_cdclk = intel_compute_min_cdclk(state);
> > > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > > if (min_cdclk < 0)
> > > return min_cdclk;
> > >
> > > @@ -2153,12 +2138,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > -static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > +static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > int min_cdclk, cdclk;
> > >
> > > - min_cdclk = intel_compute_min_cdclk(state);
> > > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > > if (min_cdclk < 0)
> > > return min_cdclk;
> > >
> > > @@ -2185,10 +2170,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > -static int skl_dpll0_vco(struct intel_atomic_state *state)
> > > +static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
> > > {
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > struct intel_crtc *crtc;
> > > struct intel_crtc_state *crtc_state;
> > > int vco, i;
> > > @@ -2222,16 +2207,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
> > > return vco;
> > > }
> > >
> > > -static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > +static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > int min_cdclk, cdclk, vco;
> > >
> > > - min_cdclk = intel_compute_min_cdclk(state);
> > > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > > if (min_cdclk < 0)
> > > return min_cdclk;
> > >
> > > - vco = skl_dpll0_vco(state);
> > > + vco = skl_dpll0_vco(cdclk_state);
> > >
> > > /*
> > > * FIXME should also account for plane ratio
> > > @@ -2258,17 +2243,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > -static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > +static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > + struct intel_atomic_state *state = cdclk_state->base.state;
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
> > > int min_cdclk, min_voltage_level, cdclk, vco;
> > >
> > > - min_cdclk = intel_compute_min_cdclk(state);
> > > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > > if (min_cdclk < 0)
> > > return min_cdclk;
> > >
> > > - min_voltage_level = bxt_compute_min_voltage_level(state);
> > > + min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
> > > if (min_voltage_level < 0)
> > > return min_voltage_level;
> > >
> > > @@ -2335,7 +2320,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > -static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > +static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> > > {
> > > int min_cdclk;
> > >
> > > @@ -2344,54 +2329,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > * check that the required minimum frequency doesn't exceed
> > > * the actual cdclk frequency.
> > > */
> > > - min_cdclk = intel_compute_min_cdclk(state);
> > > + min_cdclk = intel_compute_min_cdclk(cdclk_state);
> > > if (min_cdclk < 0)
> > > return min_cdclk;
> > >
> > > return 0;
> > > }
> > >
> > > +static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
> > > +{
> > > + struct intel_cdclk_state *cdclk_state;
> > > +
> > > + cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
> > > + if (!cdclk_state)
> > > + return NULL;
> > > +
> > > + cdclk_state->force_min_cdclk_changed = false;
> > > + cdclk_state->pipe = INVALID_PIPE;
> > > +
> > > + return &cdclk_state->base;
> > > +}
> > > +
> > > +static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
> > > + struct intel_global_state *state)
> > > +{
> > > + kfree(state);
> > > +}
> > > +
> > > +static const struct intel_global_state_funcs intel_cdclk_funcs = {
> > > + .atomic_duplicate_state = intel_cdclk_duplicate_state,
> > > + .atomic_destroy_state = intel_cdclk_destroy_state,
> > > +};
> > > +
> > > +struct intel_cdclk_state *
> > > +intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + struct intel_global_state *cdclk_state;
> > > +
> > > + cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
> > > + if (IS_ERR(cdclk_state))
> > > + return ERR_CAST(cdclk_state);
> > > +
> > > + return to_intel_cdclk_state(cdclk_state);
> > > +}
> > > +
> > > +int intel_cdclk_init(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_cdclk_state *cdclk_state;
> > > +
> > > + cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
> > > + if (!cdclk_state)
> > > + return -ENOMEM;
> > > +
> > > + intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
> > > + &cdclk_state->base, &intel_cdclk_funcs);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
> > > - struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
> > > + const struct intel_cdclk_state *old_cdclk_state;
> > > + struct intel_cdclk_state *new_cdclk_state;
> > > enum pipe pipe;
> > > int ret;
> > >
> > > - memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
> > > - sizeof(new_cdclk_state->min_cdclk));
> > > - memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
> > > - sizeof(new_cdclk_state->min_voltage_level));
> > > + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> > > + if (IS_ERR(new_cdclk_state))
> > > + return PTR_ERR(new_cdclk_state);
> > >
> > > - /* keep the current setting */
> > > - if (!new_cdclk_state->force_min_cdclk_changed)
> > > - new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
> > > + old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
> > >
> > > - new_cdclk_state->logical = old_cdclk_state->logical;
> > > - new_cdclk_state->actual = old_cdclk_state->actual;
> > > -
> > > - ret = dev_priv->display.modeset_calc_cdclk(state);
> > > + ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> > > if (ret)
> > > return ret;
> > >
> > > - /*
> > > - * Writes to dev_priv->cdclk.{actual,logical} must protected
> > > - * by holding all the crtc mutexes even if we don't end up
> > > - * touching the hardware
> > > - */
> > > if (intel_cdclk_changed(&old_cdclk_state->actual,
> > > &new_cdclk_state->actual)) {
> > > /*
> > > * Also serialize commits across all crtcs
> > > * if the actual hw needs to be poked.
> > > */
> > > - ret = _intel_atomic_serialize_global_state(state);
> > > + ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
> > > if (ret)
> > > return ret;
> > > } else if (intel_cdclk_changed(&old_cdclk_state->logical,
> > > &new_cdclk_state->logical)) {
> > > - ret = _intel_atomic_lock_global_state(state);
> > > + ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
> > > if (ret)
> > > return ret;
> > > } else {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > index 4b965db07720..195fca70bfcb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > @@ -8,11 +8,12 @@
> > >
> > > #include <linux/types.h>
> > >
> > > +#include "i915_drv.h"
> > > #include "intel_display.h"
> > > +#include "intel_global_state.h"
> > >
> > > struct drm_i915_private;
> > > struct intel_atomic_state;
> > > -struct intel_cdclk_config;
> > > struct intel_crtc_state;
> > >
> > > struct intel_cdclk_vals {
> > > @@ -22,6 +23,35 @@ struct intel_cdclk_vals {
> > > u8 ratio;
> > > };
> > >
> > > +struct intel_cdclk_state {
> > > + struct intel_global_state base;
> > > +
> > > + /*
> > > + * Logical configuration of cdclk (used for all scaling,
> > > + * watermark, etc. calculations and checks). This is
> > > + * computed as if all enabled crtcs were active.
> > > + */
> > > + struct intel_cdclk_config logical;
> > > +
> > > + /*
> > > + * Actual configuration of cdclk, can be different from the
> > > + * logical configuration only when all crtc's are DPMS off.
> > > + */
> > > + struct intel_cdclk_config actual;
> > > +
> > > + /* minimum acceptable cdclk for each pipe */
> > > + int min_cdclk[I915_MAX_PIPES];
> > > + /* minimum acceptable voltage level for each pipe */
> > > + u8 min_voltage_level[I915_MAX_PIPES];
> > > +
> > > + /* pipe to which cd2x update is synchronized */
> > > + enum pipe pipe;
> > > +
> > > + /* forced minimum cdclk for glk+ audio w/a */
> > > + int force_min_cdclk;
> > > + bool force_min_cdclk_changed;
> > > +};
> > > +
> > > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> > > void intel_cdclk_init_hw(struct drm_i915_private *i915);
> > > void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> > > @@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > > void intel_update_rawclk(struct drm_i915_private *dev_priv);
> > > bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> > > const struct intel_cdclk_config *b);
> > > -void intel_cdclk_clear_state(struct intel_atomic_state *state);
> > > -void intel_cdclk_swap_state(struct intel_atomic_state *state);
> > > void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> > > void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> > > void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
> > > const char *context);
> > > int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
> > >
> > > +struct intel_cdclk_state *
> > > +intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
> > > +
> > > +#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
> > > +#define intel_atomic_get_old_cdclk_state(state) \
> > > + to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> > > +#define intel_atomic_get_new_cdclk_state(state) \
> > > + to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
> > > +
> > > +int intel_cdclk_init(struct drm_i915_private *dev_priv);
> > > +
> > > #endif /* __INTEL_CDCLK_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index dc767efffd9a..dca100546be8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7482,7 +7482,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> > > struct intel_bw_state *bw_state =
> > > to_intel_bw_state(dev_priv->bw_obj.state);
> > > struct intel_cdclk_state *cdclk_state =
> > > - &dev_priv->cdclk_state;
> > > + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> > > struct intel_crtc_state *crtc_state =
> > > to_intel_crtc_state(crtc->base.state);
> > > enum intel_display_power_domain domain;
> > > @@ -7780,17 +7780,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> > > return true;
> > > }
> > >
> > > -static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > > +static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *dev_priv =
> > > to_i915(crtc_state->uapi.crtc->dev);
> > > - struct intel_atomic_state *intel_state =
> > > + struct intel_atomic_state *state =
> > > to_intel_atomic_state(crtc_state->uapi.state);
> > > - const struct intel_cdclk_state *cdclk_state =
> > > - &intel_state->cdclk_state;
> > > +
> > > + crtc_state->ips_enabled = false;
> > >
> > > if (!hsw_crtc_state_ips_capable(crtc_state))
> > > - return false;
> > > + return 0;
> > >
> > > /*
> > > * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> > > @@ -7799,18 +7799,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> > > * completely disable it.
> > > */
> > > if (crtc_state->crc_enabled)
> > > - return false;
> > > + return 0;
> > >
> > > /* IPS should be fine as long as at least one plane is enabled. */
> > > if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
> > > - return false;
> > > + return 0;
> > >
> > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > > - if (IS_BROADWELL(dev_priv) &&
> > > - crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> > > - return false;
> > > + if (IS_BROADWELL(dev_priv)) {
> > > + const struct intel_cdclk_state *cdclk_state;
> > >
> > > - return true;
> > > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > > + if (IS_ERR(cdclk_state))
> > > + return PTR_ERR(cdclk_state);
> > > +
> > > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > > + if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> > > + return 0;
> > > + }
> > > +
> > > + crtc_state->ips_enabled = true;
> > > +
> > > + return 0;
> > > }
> > >
> > > static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> > > @@ -12543,14 +12552,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> > > adjusted_mode->crtc_clock);
> > > }
> > >
> > > -static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
> > > +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
> > > + const struct intel_cdclk_state *cdclk_state)
> > > {
> > > - const struct intel_atomic_state *state =
> > > - to_intel_atomic_state(crtc_state->uapi.state);
> > > const struct drm_display_mode *adjusted_mode =
> > > &crtc_state->hw.adjusted_mode;
> > > - const struct intel_cdclk_state *cdclk_state =
> > > - &state->cdclk_state;
> > >
> > > if (!crtc_state->hw.enable)
> > > return 0;
> > > @@ -12580,6 +12586,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
> > > return linetime_wm;
> > > }
> > >
> > > +static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
> > > + struct intel_crtc *crtc)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > + struct intel_crtc_state *crtc_state =
> > > + intel_atomic_get_new_crtc_state(state, crtc);
> > > + const struct intel_cdclk_state *cdclk_state;
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 9)
> > > + crtc_state->linetime = skl_linetime_wm(crtc_state);
> > > + else
> > > + crtc_state->linetime = hsw_linetime_wm(crtc_state);
> > > +
> > > + if (!hsw_crtc_supports_ips(crtc))
> > > + return 0;
> > > +
> > > + cdclk_state = intel_atomic_get_cdclk_state(state);
> > > + if (IS_ERR(cdclk_state))
> > > + return PTR_ERR(cdclk_state);
> > > +
> > > + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
> > > + cdclk_state);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc)
> > > {
> > > @@ -12615,7 +12647,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > > return ret;
> > > }
> > >
> > > - ret = 0;
> > > if (dev_priv->display.compute_pipe_wm) {
> > > ret = dev_priv->display.compute_pipe_wm(crtc_state);
> > > if (ret) {
> > > @@ -12646,20 +12677,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> > > if (!ret)
> > > ret = intel_atomic_setup_scalers(dev_priv, crtc,
> > > crtc_state);
> > > + if (ret)
> > > + return ret;
> > > }
> > >
> > > - if (HAS_IPS(dev_priv))
> > > - crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
> > > + if (HAS_IPS(dev_priv)) {
> > > + ret = hsw_compute_ips_config(crtc_state);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 9 ||
> > > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > > + ret = hsw_compute_linetime_wm(state, crtc);
> > > + if (ret)
> > > + return ret;
> > >
> > > - if (INTEL_GEN(dev_priv) >= 9) {
> > > - crtc_state->linetime = skl_linetime_wm(crtc_state);
> > > - } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > > - crtc_state->linetime = hsw_linetime_wm(crtc_state);
> > > - if (hsw_crtc_supports_ips(crtc))
> > > - crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
> > > }
> > >
> > > - return ret;
> > > + return 0;
> > > }
> > >
> > > static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> > > @@ -14478,7 +14514,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
> > > }
> > >
> > > static int intel_atomic_check_planes(struct intel_atomic_state *state,
> > > - bool *need_modeset)
> > > + bool *need_cdclk_calc)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > > @@ -14532,8 +14568,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
> > > * affected planes are part of the state. We can now
> > > * compute the minimum cdclk for each plane.
> > > */
> > > - for_each_new_intel_plane_in_state(state, plane, plane_state, i)
> > > - *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
> > > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > + ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
> > > + if (ret)
> > > + return ret;
> > > + }
> > >
> > > return 0;
> > > }
> > > @@ -14654,6 +14693,7 @@ static int intel_atomic_check(struct drm_device *dev,
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > struct intel_atomic_state *state = to_intel_atomic_state(_state);
> > > struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > > + struct intel_cdclk_state *new_cdclk_state;
> > > struct intel_crtc *crtc;
> > > int ret, i;
> > > bool any_ms = false;
> > > @@ -14766,18 +14806,18 @@ static int intel_atomic_check(struct drm_device *dev,
> > > if (ret)
> > > goto fail;
> > >
> > > - any_ms |= state->cdclk_state.force_min_cdclk_changed;
> > > -
> > > ret = intel_atomic_check_planes(state, &any_ms);
> > > if (ret)
> > > goto fail;
> > >
> > > + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> > > + if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
> > > + any_ms = true;
> > > +
> > > if (any_ms) {
> > > ret = intel_modeset_checks(state);
> > > if (ret)
> > > goto fail;
> > > - } else {
> > > - state->cdclk_state.logical = dev_priv->cdclk_state.logical;
> > > }
> > >
> > > ret = intel_atomic_check_crtcs(state);
> > > @@ -15676,8 +15716,6 @@ static int intel_atomic_commit(struct drm_device *dev,
> > > assert_global_state_locked(dev_priv);
> > >
> > > dev_priv->active_pipes = state->active_pipes;
> > > -
> > > - intel_cdclk_swap_state(state);
> > > }
> > >
> > > drm_atomic_state_get(&state->base);
> > > @@ -17356,7 +17394,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> > > void intel_modeset_init_hw(struct drm_i915_private *i915)
> > > {
> > > struct intel_cdclk_state *cdclk_state =
> > > - &i915->cdclk_state;
> > > + to_intel_cdclk_state(i915->cdclk.obj.state);
> > >
> > > intel_update_cdclk(i915);
> > > intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
> > > @@ -17587,6 +17625,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
> > >
> > > intel_mode_config_init(i915);
> > >
> > > + ret = intel_cdclk_init(i915);
> > > + if (ret)
> > > + return ret;
> > > +
> > > ret = intel_bw_init(i915);
> > > if (ret)
> > > return ret;
> > > @@ -18071,6 +18113,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
> > > static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_cdclk_state *cdclk_state =
> > > + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> > > enum pipe pipe;
> > > struct intel_crtc *crtc;
> > > struct intel_encoder *encoder;
> > > @@ -18190,8 +18234,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > > for_each_intel_crtc(dev, crtc) {
> > > struct intel_bw_state *bw_state =
> > > to_intel_bw_state(dev_priv->bw_obj.state);
> > > - struct intel_cdclk_state *cdclk_state =
> > > - &dev_priv->cdclk_state;
> > > struct intel_crtc_state *crtc_state =
> > > to_intel_crtc_state(crtc->base.state);
> > > struct intel_plane *plane;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 628c4a56a9e9..524b6d5235ee 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -465,8 +465,6 @@ struct intel_atomic_state {
> > > struct __intel_global_objs_state *global_objs;
> > > int num_global_objs;
> > >
> > > - struct intel_cdclk_state cdclk_state;
> > > -
> > > bool dpll_set, modeset;
> > >
> > > /*
> > > @@ -493,7 +491,6 @@ struct intel_atomic_state {
> > >
> > > /*
> > > * active_pipes
> > > - * cdclk_state
> > > */
> > > bool global_state_changed;
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 63cda89a4e62..2e6b149478c1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -65,7 +65,6 @@
> > > #include "i915_utils.h"
> > >
> > > #include "display/intel_bios.h"
> > > -#include "display/intel_cdclk.h"
> > > #include "display/intel_display.h"
> > > #include "display/intel_display_power.h"
> > > #include "display/intel_dpll_mgr.h"
> > > @@ -258,7 +257,8 @@ struct intel_connector;
> > > struct intel_encoder;
> > > struct intel_atomic_state;
> > > struct intel_cdclk_config;
> > > -struct intel_crtc_state;
> > > +struct intel_cdclk_state;
> > > +struct intel_cdclk_vals;
> > > struct intel_initial_plane_config;
> > > struct intel_crtc;
> > > struct intel_limit;
> > > @@ -282,7 +282,7 @@ struct drm_i915_display_funcs {
> > > struct intel_crtc *crtc);
> > > int (*compute_global_watermarks)(struct intel_atomic_state *state);
> > > void (*update_wm)(struct intel_crtc *crtc);
> > > - int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> > > + int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
> > > u8 (*calc_voltage_level)(int cdclk);
> > > /* Returns the active state of the crtc, and if the crtc is active,
> > > * fills out the pipe-config with the hw state. */
> > > @@ -891,33 +891,6 @@ struct i915_selftest_stash {
> > > atomic_t counter;
> > > };
> > >
> > > -struct intel_cdclk_state {
> > > - /*
> > > - * Logical configuration of cdclk (used for all scaling,
> > > - * watermark, etc. calculations and checks). This is
> > > - * computed as if all enabled crtcs were active.
> > > - */
> > > - struct intel_cdclk_config logical;
> > > -
> > > - /*
> > > - * Actual configuration of cdclk, can be different from the
> > > - * logical configuration only when all crtc's are DPMS off.
> > > - */
> > > - struct intel_cdclk_config actual;
> > > -
> > > - /* minimum acceptable cdclk for each pipe */
> > > - int min_cdclk[I915_MAX_PIPES];
> > > - /* minimum acceptable voltage level for each pipe */
> > > - u8 min_voltage_level[I915_MAX_PIPES];
> > > -
> > > - /* pipe to which cd2x update is synchronized */
> > > - enum pipe pipe;
> > > -
> > > - /* forced minimum cdclk for glk+ audio w/a */
> > > - int force_min_cdclk;
> > > - bool force_min_cdclk_changed;
> > > -};
> > > -
> > > struct drm_i915_private {
> > > struct drm_device drm;
> > >
> > > @@ -1034,18 +1007,14 @@ struct drm_i915_private {
> > > unsigned int fdi_pll_freq;
> > > unsigned int czclk_freq;
> > >
> > > - /*
> > > - * For reading holding any crtc lock is sufficient,
> > > - * for writing must hold all of them.
> > > - */
> > > - struct intel_cdclk_state cdclk_state;
> > > -
> > > struct {
> > > /* The current hardware cdclk configuration */
> > > struct intel_cdclk_config hw;
> > >
> > > /* cdclk, divider, and ratio table from bspec */
> > > const struct intel_cdclk_vals *table;
> > > +
> > > + struct intel_global_obj obj;
> > > } cdclk;
> > >
> > > /**
> > > @@ -1104,8 +1073,8 @@ struct drm_i915_private {
> > > struct list_head global_obj_list;
> > >
> > > /*
> > > - * For reading active_pipes, cdclk_state holding any crtc
> > > - * lock is sufficient, for writing must hold all of them.
> > > + * For reading active_pipes holding any crtc lock is
> > > + * sufficient, for writing must hold all of them.
> > > */
> > > u8 active_pipes;
> > >
> > > --
> > > 2.24.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
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* Re: [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
@ 2020-01-28 14:44 ` Lisovskiy, Stanislav
2020-01-28 15:29 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Lisovskiy, Stanislav @ 2020-01-28 14:44 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our current global state handling is pretty ad-hoc. Let's try to
> make it better by imitating the standard drm core private object
> approach.
>
> The reason why we don't want to directly use the private objects
> is locking; Each private object has its own lock so if we
> introduce any global private objects we get serialized by that
> single lock across all pipes. The global state apporoach instead
> uses a read/write lock type of approach where each individual
> crtc lock counts as a read lock, and grabbing all the crtc locks
> allows one write access.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks like, I would prefer to get your global changes landed first
as you have almost all patches reviewed by now. Once those land,
I will fetch those changes and use new global state handling in
my SAGV patches.
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 15 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> .../gpu/drm/i915/display/intel_global_state.c | 223
> ++++++++++++++++++
> .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 10 files changed, 342 insertions(+), 12 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
>
>
> +
> +int intel_atomic_lock_global_state(struct intel_global_state
> *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + int ret;
> +
> + ret = drm_modeset_lock(&crtc->base.mutex,
> + state->base.acquire_ctx);
> + if (ret)
> + return ret;
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
> +
> +int intel_atomic_serialize_global_state(struct intel_global_state
> *obj_state)
> +{
> + struct intel_atomic_state *state = obj_state->state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base,
> crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + obj_state->changed = true;
> +
> + return 0;
> +}
Just out of curiousity, aren't we supposed to lock global state,
by just grabbing crtcs always? One for read, all for write. I see now
you have two alternate ways of doing this, i.e either call
intel_atomic_lock_global_state or intel_atomic_serialize_global_state.
To me it seems better to have somewhat unified approach for global
state locking, however may be I'm missing something here.
Anyways,
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h
> b/drivers/gpu/drm/i915/display/intel_global_state.h
> new file mode 100644
> index 000000000000..e6163a469029
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GLOBAL_STATE_H__
> +#define __INTEL_GLOBAL_STATE_H__
> +
> +#include <linux/list.h>
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_global_obj;
> +struct intel_global_state;
> +
> +struct intel_global_state_funcs {
> + struct intel_global_state *(*atomic_duplicate_state)(struct
> intel_global_obj *obj);
> + void (*atomic_destroy_state)(struct intel_global_obj *obj,
> + struct intel_global_state *state);
> +};
> +
> +struct intel_global_obj {
> + struct list_head head;
> + struct intel_global_state *state;
> + const struct intel_global_state_funcs *funcs;
> +};
> +
> +#define intel_for_each_global_obj(obj, dev_priv) \
> + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
> +
> +#define for_each_new_global_obj_in_state(__state, obj,
> new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_old_global_obj_in_state(__state, obj,
> new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].old_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +#define for_each_oldnew_global_obj_in_state(__state, obj,
> old_obj_state, new_obj_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->num_global_objs && \
> + ((obj) = (__state)->global_objs[__i].ptr, \
> + (old_obj_state) = (__state)-
> >global_objs[__i].old_state, \
> + (new_obj_state) = (__state)-
> >global_objs[__i].new_state, 1); \
> + (__i)++) \
> + for_each_if(obj)
> +
> +struct intel_global_state {
> + struct intel_atomic_state *state;
> + bool changed;
> +};
> +
> +struct __intel_global_objs_state {
> + struct intel_global_obj *ptr;
> + struct intel_global_state *state, *old_state, *new_state;
> +};
> +
> +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> + struct intel_global_obj *obj,
> + struct intel_global_state *state,
> + const struct intel_global_state_funcs
> *funcs);
> +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> *dev_priv);
> +
> +struct intel_global_state *
> +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj);
> +struct intel_global_state *
> +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> *state,
> + struct intel_global_obj *obj);
> +
> +void intel_atomic_swap_global_state(struct intel_atomic_state
> *state);
> +void intel_atomic_clear_global_state(struct intel_atomic_state
> *state);
> +int intel_atomic_lock_global_state(struct intel_global_state
> *obj_state);
> +int intel_atomic_serialize_global_state(struct intel_global_state
> *obj_state);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 1787bfdd057f..b558e68b4dbd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -71,6 +71,7 @@
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> +#include "display/intel_global_state.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
>
> @@ -1100,6 +1101,8 @@ struct drm_i915_private {
> */
> struct mutex dpll_lock;
>
> + struct list_head global_obj_list;
> +
> /*
> * For reading active_pipes, cdclk_state holding any crtc
> * lock is sufficient, for writing must hold all of them.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling
2020-01-28 14:44 ` Lisovskiy, Stanislav
@ 2020-01-28 15:29 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2020-01-28 15:29 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Tue, Jan 28, 2020 at 02:44:04PM +0000, Lisovskiy, Stanislav wrote:
> On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Our current global state handling is pretty ad-hoc. Let's try to
> > make it better by imitating the standard drm core private object
> > approach.
> >
> > The reason why we don't want to directly use the private objects
> > is locking; Each private object has its own lock so if we
> > introduce any global private objects we get serialized by that
> > single lock across all pipes. The global state apporoach instead
> > uses a read/write lock type of approach where each individual
> > crtc lock counts as a read lock, and grabbing all the crtc locks
> > allows one write access.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Looks like, I would prefer to get your global changes landed first
> as you have almost all patches reviewed by now. Once those land,
> I will fetch those changes and use new global state handling in
> my SAGV patches.
>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
> > drivers/gpu/drm/i915/display/intel_atomic.h | 4 +-
> > drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 15 +-
> > .../drm/i915/display/intel_display_types.h | 4 +
> > .../gpu/drm/i915/display/intel_global_state.c | 223
> > ++++++++++++++++++
> > .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 10 files changed, 342 insertions(+), 12 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h
> >
> >
>
>
> > +
> > +int intel_atomic_lock_global_state(struct intel_global_state
> > *obj_state)
> > +{
> > + struct intel_atomic_state *state = obj_state->state;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + int ret;
> > +
> > + ret = drm_modeset_lock(&crtc->base.mutex,
> > + state->base.acquire_ctx);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + obj_state->changed = true;
> > +
> > + return 0;
> > +}
> > +
> > +int intel_atomic_serialize_global_state(struct intel_global_state
> > *obj_state)
> > +{
> > + struct intel_atomic_state *state = obj_state->state;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc *crtc;
> > +
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + struct intel_crtc_state *crtc_state;
> > +
> > + crtc_state = intel_atomic_get_crtc_state(&state->base,
> > crtc);
> > + if (IS_ERR(crtc_state))
> > + return PTR_ERR(crtc_state);
> > + }
> > +
> > + obj_state->changed = true;
> > +
> > + return 0;
> > +}
>
> Just out of curiousity, aren't we supposed to lock global state,
> by just grabbing crtcs always? One for read, all for write. I see now
> you have two alternate ways of doing this, i.e either call
> intel_atomic_lock_global_state or intel_atomic_serialize_global_state.
> To me it seems better to have somewhat unified approach for global
> state locking, however may be I'm missing something here.
One just locks things which means other nonblocking commits can still
execute in parallel once the locks are dropped. The serialize variant
adds all the crtcs to the state meaning their other commits will get
serialized against the current commit no matter on which wq they
execute. So just an attempt to avoid needless serialization and the
resulting framerate stutters.
>
> Anyways,
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h
> > b/drivers/gpu/drm/i915/display/intel_global_state.h
> > new file mode 100644
> > index 000000000000..e6163a469029
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> > @@ -0,0 +1,87 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2020 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_GLOBAL_STATE_H__
> > +#define __INTEL_GLOBAL_STATE_H__
> > +
> > +#include <linux/list.h>
> > +
> > +struct drm_i915_private;
> > +struct intel_atomic_state;
> > +struct intel_global_obj;
> > +struct intel_global_state;
> > +
> > +struct intel_global_state_funcs {
> > + struct intel_global_state *(*atomic_duplicate_state)(struct
> > intel_global_obj *obj);
> > + void (*atomic_destroy_state)(struct intel_global_obj *obj,
> > + struct intel_global_state *state);
> > +};
> > +
> > +struct intel_global_obj {
> > + struct list_head head;
> > + struct intel_global_state *state;
> > + const struct intel_global_state_funcs *funcs;
> > +};
> > +
> > +#define intel_for_each_global_obj(obj, dev_priv) \
> > + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
> > +
> > +#define for_each_new_global_obj_in_state(__state, obj,
> > new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].new_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +#define for_each_old_global_obj_in_state(__state, obj,
> > new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].old_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +#define for_each_oldnew_global_obj_in_state(__state, obj,
> > old_obj_state, new_obj_state, __i) \
> > + for ((__i) = 0; \
> > + (__i) < (__state)->num_global_objs && \
> > + ((obj) = (__state)->global_objs[__i].ptr, \
> > + (old_obj_state) = (__state)-
> > >global_objs[__i].old_state, \
> > + (new_obj_state) = (__state)-
> > >global_objs[__i].new_state, 1); \
> > + (__i)++) \
> > + for_each_if(obj)
> > +
> > +struct intel_global_state {
> > + struct intel_atomic_state *state;
> > + bool changed;
> > +};
> > +
> > +struct __intel_global_objs_state {
> > + struct intel_global_obj *ptr;
> > + struct intel_global_state *state, *old_state, *new_state;
> > +};
> > +
> > +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
> > + struct intel_global_obj *obj,
> > + struct intel_global_state *state,
> > + const struct intel_global_state_funcs
> > *funcs);
> > +void intel_atomic_global_obj_cleanup(struct drm_i915_private
> > *dev_priv);
> > +
> > +struct intel_global_state *
> > +intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
> > + struct intel_global_obj *obj);
> > +struct intel_global_state *
> > +intel_atomic_get_old_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj);
> > +struct intel_global_state *
> > +intel_atomic_get_new_global_obj_state(struct intel_atomic_state
> > *state,
> > + struct intel_global_obj *obj);
> > +
> > +void intel_atomic_swap_global_state(struct intel_atomic_state
> > *state);
> > +void intel_atomic_clear_global_state(struct intel_atomic_state
> > *state);
> > +int intel_atomic_lock_global_state(struct intel_global_state
> > *obj_state);
> > +int intel_atomic_serialize_global_state(struct intel_global_state
> > *obj_state);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1787bfdd057f..b558e68b4dbd 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -71,6 +71,7 @@
> > #include "display/intel_dpll_mgr.h"
> > #include "display/intel_dsb.h"
> > #include "display/intel_frontbuffer.h"
> > +#include "display/intel_global_state.h"
> > #include "display/intel_gmbus.h"
> > #include "display/intel_opregion.h"
> >
> > @@ -1100,6 +1101,8 @@ struct drm_i915_private {
> > */
> > struct mutex dpll_lock;
> >
> > + struct list_head global_obj_list;
> > +
> > /*
> > * For reading active_pipes, cdclk_state holding any crtc
> > * lock is sufficient, for writing must hold all of them.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
@ 2020-01-29 14:05 ` Lisovskiy, Stanislav
2020-01-31 15:07 ` Ville Syrjälä
1 sibling, 0 replies; 48+ messages in thread
From: Lisovskiy, Stanislav @ 2020-01-29 14:05 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The linetime watermarks really have very little in common with the
> plane watermarks. It looks to be cleaner to simply track them in
> the crtc_state and program them from the normal modeset/fastset
> paths.
>
> The only dark cloud comes from the fact that the register is
> still supposedly single buffered. So in theory it might still
> need some form of two stage programming. Note that even though
> HSW/BDWhave two stage programming we never computed any special
> intermediate values for the linetime watermarks, and on SKL+
> we don't even have the two stage stuff plugged in since everything
> else is double buffered. So let's assume it's all fine and
> continue doing what we've been doing.
>
> Actually on HSW/BDW the value should not even change without
> a full modeset since it doesn't account for pfit downscaling.
> Thus only fastboot might be affected. But on SKL+ the pfit
> scaling factor is take into consideration so the value may
> change during any fastset.
>
> As a bonus we'll plug this thing into the state
> checker/dump now.
>
> v2: Rebase due to bigjoiner prep
> v2: Only compute ips linetime for IPS capable pipes.
> Bspec says the register values is ignored for other
> pipes, but in fact it can't even be written so the
> state checker becomes unhappy if we don't compute
> it as zero.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 95 +++++++++++++-
> .../drm/i915/display/intel_display_types.h | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 117 +---------------
> --
> 4 files changed, 98 insertions(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 76c17341df2b..8dcb86c51aaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6885,6 +6885,16 @@ static void icl_pipe_mbus_enable(struct
> intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
>
> +static void hsw_set_linetime_wm(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + I915_WRITE(WM_LINETIME(crtc->pipe),
> + HSW_LINETIME(crtc_state->linetime) |
> + HSW_IPS_LINETIME(crtc_state->ips_linetime));
> +}
> +
> static void hsw_set_frame_start_delay(const struct intel_crtc_state
> *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -6969,6 +6979,8 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> if (INTEL_GEN(dev_priv) < 9)
> intel_disable_primary_plane(new_crtc_state);
>
> + hsw_set_linetime_wm(new_crtc_state);
> +
> if (INTEL_GEN(dev_priv) >= 11)
> icl_set_pipe_chicken(crtc);
>
> @@ -10947,6 +10959,7 @@ static bool hsw_get_pipe_config(struct
> intel_crtc *crtc,
> enum intel_display_power_domain power_domain;
> u64 power_domain_mask;
> bool active;
> + u32 tmp;
>
> pipe_config->master_transcoder = INVALID_TRANSCODER;
>
> @@ -11010,7 +11023,7 @@ static bool hsw_get_pipe_config(struct
> intel_crtc *crtc,
> pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
>
> if (INTEL_GEN(dev_priv) >= 9) {
> - u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
> + tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
>
> if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
> pipe_config->gamma_enable = true;
> @@ -11023,6 +11036,12 @@ static bool hsw_get_pipe_config(struct
> intel_crtc *crtc,
>
> intel_color_get_config(pipe_config);
>
> + tmp = I915_READ(WM_LINETIME(crtc->pipe));
> + pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
Shouldn't we have also gen >= 9 check here? If let's say
hsw_get_pipe_config was called for non-gen 9, non-hsw and non-bdw case.
I see that hsw_get_pipe_config hook is used also for any platform which
evaluates HAS_DDI check to true in intel_init_display_hooks.
At least I see that everywhere else there is a check for >= gen 9,
when you set pipe_config->linetime.
Stan
> + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + pipe_config->ips_linetime =
> + REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
> +
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> WARN_ON(power_domain_mask & BIT_ULL(power_domain));
>
> @@ -12508,6 +12527,53 @@ static int
> icl_compute_port_sync_crtc_state(struct drm_connector *connector,
> return 0;
> }
>
> +static u16 hsw_linetime_wm(const struct intel_crtc_state
> *crtc_state)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> +
> + if (!crtc_state->hw.enable)
> + return 0;
> +
> + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> + adjusted_mode->crtc_clock);
> +}
> +
> +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state
> *crtc_state)
> +{
> + const struct intel_atomic_state *state =
> + to_intel_atomic_state(crtc_state->uapi.state);
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> +
> + if (!crtc_state->hw.enable)
> + return 0;
> +
> + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> + state->cdclk.logical.cdclk);
> +}
> +
> +static u16 skl_linetime_wm(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + u16 linetime_wm;
> +
> + if (!crtc_state->hw.enable)
> + return 0;
> +
> + linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 *
> 8,
> + crtc_state->pixel_rate);
> +
> + /* Display WA #1135: BXT:ALL GLK:ALL */
> + if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
> + linetime_wm /= 2;
> +
> + return linetime_wm;
> +}
> +
> static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -12579,6 +12645,14 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
> if (HAS_IPS(dev_priv))
> crtc_state->ips_enabled =
> hsw_compute_ips_config(crtc_state);
>
> + if (INTEL_GEN(dev_priv) >= 9) {
> + crtc_state->linetime = skl_linetime_wm(crtc_state);
> + } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> + crtc_state->linetime = hsw_linetime_wm(crtc_state);
> + if (hsw_crtc_supports_ips(crtc))
> + crtc_state->ips_linetime =
> hsw_ips_linetime_wm(crtc_state);
> + }
> +
> return ret;
> }
>
> @@ -12868,6 +12942,9 @@ static void intel_dump_pipe_config(const
> struct intel_crtc_state *pipe_config,
> pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> pipe_config->pixel_rate);
>
> + DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n",
> + pipe_config->linetime, pipe_config-
> >ips_linetime);
> +
> if (INTEL_GEN(dev_priv) >= 9)
> DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x,
> scaler_id: %d\n",
> crtc->num_scalers,
> @@ -13638,10 +13715,12 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
>
> + PIPE_CONF_CHECK_I(linetime);
> + PIPE_CONF_CHECK_I(ips_linetime);
> +
> bp_gamma =
> intel_color_get_gamma_bit_precision(pipe_config);
> if (bp_gamma)
> PIPE_CONF_CHECK_COLOR_LUT(gamma_mode,
> hw.gamma_lut, bp_gamma);
> -
> }
>
> PIPE_CONF_CHECK_BOOL(double_wide);
> @@ -14798,6 +14877,18 @@ static void intel_pipe_fastset(const struct
> intel_crtc_state *old_crtc_state,
> ilk_pfit_disable(old_crtc_state);
> }
>
> + /*
> + * The register is supposedly single buffered so perhaps
> + * not 100% correct to do this here. But SKL+ calculate
> + * this based on the adjust pixel rate so pfit changes do
> + * affect it and so it must be updated for fastsets.
> + * HSW/BDW only really need this here for fastboot, after
> + * that the value should not change without a full modeset.
> + */
> + if (INTEL_GEN(dev_priv) >= 9 ||
> + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + hsw_set_linetime_wm(new_crtc_state);
> +
> if (INTEL_GEN(dev_priv) >= 11)
> icl_set_pipe_chicken(crtc);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index bfe85e180e16..2d8491590501 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -662,8 +662,6 @@ struct intel_crtc_scaler_state {
>
> struct intel_pipe_wm {
> struct intel_wm_level wm[5];
> - u16 linetime;
> - u16 ips_linetime;
> bool fbc_wm_enabled;
> bool pipe_enabled;
> bool sprites_enabled;
> @@ -679,7 +677,6 @@ struct skl_plane_wm {
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> - u32 linetime;
> };
>
> enum vlv_wm_level {
> @@ -1050,6 +1047,10 @@ struct intel_crtc_state {
> struct drm_dsc_config config;
> } dsc;
>
> + /* HSW+ linetime watermarks */
> + u16 linetime;
> + u16 ips_linetime;
> +
> /* Forward Error correction State */
> bool fec_enable;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 077af22b8340..5bd40184ddee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -744,7 +744,6 @@ struct ilk_wm_values {
> u32 wm_pipe[3];
> u32 wm_lp[3];
> u32 wm_lp_spr[3];
> - u32 wm_linetime[3];
> bool enable_fbc_wm;
> enum intel_ddb_partitioning partitioning;
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index a4b66ee1e3d8..edd62367006d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2810,34 +2810,6 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> result->enable = true;
> }
>
> -static u32
> -hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> -{
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> -
> - if (!crtc_state->hw.active)
> - return 0;
> -
> - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> - adjusted_mode->crtc_clock);
> -}
> -
> -static u32
> -hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
> -{
> - const struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->uapi.state);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> -
> - if (!crtc_state->hw.active)
> - return 0;
> -
> - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> - state->cdclk.logical.cdclk);
> -}
> -
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[8])
> {
> @@ -3178,11 +3150,6 @@ static int ilk_compute_pipe_wm(struct
> intel_crtc_state *crtc_state)
> ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
> pristate, sprstate, curstate, &pipe_wm-
> >wm[0]);
>
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - pipe_wm->linetime = hsw_linetime_wm(crtc_state);
> - pipe_wm->ips_linetime =
> hsw_ips_linetime_wm(crtc_state);
> - }
> -
> if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
> return -EINVAL;
>
> @@ -3433,9 +3400,6 @@ static void ilk_compute_wm_results(struct
> drm_i915_private *dev_priv,
>
> if (WARN_ON(!r->enable))
> continue;
> - results->wm_linetime[pipe] =
> - HSW_LINETIME(pipe_wm->linetime) |
> - HSW_IPS_LINETIME(pipe_wm->ips_linetime);
>
> results->wm_pipe[pipe] =
> (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
> @@ -3475,7 +3439,6 @@ ilk_find_best_result(struct drm_i915_private
> *dev_priv,
>
> /* dirty bits used to track which watermarks need changes */
> #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
> -#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
> #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
> #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) |
> WM_DIRTY_LP(3))
> #define WM_DIRTY_FBC (1 << 24)
> @@ -3490,12 +3453,6 @@ static unsigned int
> ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
> int wm_lp;
>
> for_each_pipe(dev_priv, pipe) {
> - if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
> - dirty |= WM_DIRTY_LINETIME(pipe);
> - /* Must disable LP1+ watermarks too */
> - dirty |= WM_DIRTY_LP_ALL;
> - }
> -
> if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
> dirty |= WM_DIRTY_PIPE(pipe);
> /* Must disable LP1+ watermarks too */
> @@ -3587,13 +3544,6 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
> if (dirty & WM_DIRTY_PIPE(PIPE_C))
> I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
>
> - if (dirty & WM_DIRTY_LINETIME(PIPE_A))
> - I915_WRITE(WM_LINETIME(PIPE_A), results-
> >wm_linetime[0]);
> - if (dirty & WM_DIRTY_LINETIME(PIPE_B))
> - I915_WRITE(WM_LINETIME(PIPE_B), results-
> >wm_linetime[1]);
> - if (dirty & WM_DIRTY_LINETIME(PIPE_C))
> - I915_WRITE(WM_LINETIME(PIPE_C), results-
> >wm_linetime[2]);
> -
> if (dirty & WM_DIRTY_DDB) {
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> val = I915_READ(WM_MISC);
> @@ -4847,24 +4797,6 @@ skl_compute_wm_levels(const struct
> intel_crtc_state *crtc_state,
> }
> }
>
> -static u32
> -skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_atomic_state *state = crtc_state->uapi.state;
> - struct drm_i915_private *dev_priv = to_i915(state->dev);
> - uint_fixed_16_16_t linetime_us;
> - u32 linetime_wm;
> -
> - linetime_us = intel_get_linetime_us(crtc_state);
> - linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8,
> linetime_us));
> -
> - /* Display WA #1135: BXT:ALL GLK:ALL */
> - if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
> - linetime_wm /= 2;
> -
> - return linetime_wm;
> -}
> -
> static void skl_compute_transition_wm(const struct intel_crtc_state
> *crtc_state,
> const struct skl_wm_params *wp,
> struct skl_plane_wm *wm)
> @@ -5052,8 +4984,6 @@ static int skl_build_pipe_wm(struct
> intel_crtc_state *crtc_state)
> return ret;
> }
>
> - pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
> -
> return 0;
> }
>
> @@ -5178,7 +5108,7 @@ static bool skl_pipe_wm_equals(struct
> intel_crtc *crtc,
> return false;
> }
>
> - return wm1->linetime == wm2->linetime;
> + return true;
> }
>
> static inline bool skl_ddb_entries_overlap(const struct
> skl_ddb_entry *a,
> @@ -5559,40 +5489,6 @@ skl_compute_wm(struct intel_atomic_state
> *state)
> return 0;
> }
>
> -static void skl_atomic_update_crtc_wm(struct intel_atomic_state
> *state,
> - struct intel_crtc *crtc)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> - const struct skl_pipe_wm *pipe_wm = &crtc_state-
> >wm.skl.optimal;
> - enum pipe pipe = crtc->pipe;
> -
> - if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> - return;
> -
> - I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
> -}
> -
> -static void skl_initial_wm(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> - struct skl_ddb_values *results = &state->wm_results;
> -
> - if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> - return;
> -
> - mutex_lock(&dev_priv->wm.wm_mutex);
> -
> - if (crtc_state->uapi.active_changed)
> - skl_atomic_update_crtc_wm(state, crtc);
> -
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> -}
> -
> static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
> struct intel_wm_config *config)
> {
> @@ -5715,9 +5611,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> *crtc,
>
> if (!crtc->active)
> return;
> -
> - val = I915_READ(WM_LINETIME(pipe));
> - out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
> }
>
> void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
> @@ -5758,8 +5651,6 @@ static void ilk_pipe_wm_get_hw_state(struct
> intel_crtc *crtc)
> };
>
> hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> - hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
>
> memset(active, 0, sizeof(*active));
>
> @@ -5778,10 +5669,6 @@ static void ilk_pipe_wm_get_hw_state(struct
> intel_crtc *crtc)
> active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >>
> WM0_PIPE_PLANE_SHIFT;
> active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >>
> WM0_PIPE_SPRITE_SHIFT;
> active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
> - active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
> - hw-
> >wm_linetime[pipe]);
> - active->ips_linetime =
> REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
> - hw-
> >wm_linetime[pipe]);
> } else {
> int level, max_level = ilk_wm_max_level(dev_priv);
>
> @@ -7264,8 +7151,6 @@ void intel_init_pm(struct drm_i915_private
> *dev_priv)
> /* For FIFO watermark updates */
> if (INTEL_GEN(dev_priv) >= 9) {
> skl_setup_wm_latency(dev_priv);
> - dev_priv->display.initial_watermarks = skl_initial_wm;
> - dev_priv->display.atomic_update_watermarks =
> skl_atomic_update_crtc_wm;
> dev_priv->display.compute_global_watermarks =
> skl_compute_wm;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
2020-01-29 14:05 ` Lisovskiy, Stanislav
@ 2020-01-31 15:07 ` Ville Syrjälä
1 sibling, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2020-01-31 15:07 UTC (permalink / raw)
To: intel-gfx
On Mon, Jan 20, 2020 at 07:47:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The linetime watermarks really have very little in common with the
> plane watermarks. It looks to be cleaner to simply track them in
> the crtc_state and program them from the normal modeset/fastset
> paths.
>
> The only dark cloud comes from the fact that the register is
> still supposedly single buffered. So in theory it might still
> need some form of two stage programming. Note that even though
> HSW/BDWhave two stage programming we never computed any special
> intermediate values for the linetime watermarks, and on SKL+
> we don't even have the two stage stuff plugged in since everything
> else is double buffered. So let's assume it's all fine and
> continue doing what we've been doing.
>
> Actually on HSW/BDW the value should not even change without
> a full modeset since it doesn't account for pfit downscaling.
> Thus only fastboot might be affected. But on SKL+ the pfit
> scaling factor is take into consideration so the value may
> change during any fastset.
>
> As a bonus we'll plug this thing into the state
> checker/dump now.
>
> v2: Rebase due to bigjoiner prep
> v2: Only compute ips linetime for IPS capable pipes.
> Bspec says the register values is ignored for other
> pipes, but in fact it can't even be written so the
> state checker becomes unhappy if we don't compute
> it as zero.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extracted Stan's r-b from the trybot list (whoops) and pushed the lot:
https://lists.freedesktop.org/archives/intel-gfx-trybot/2020-January/086561.html
Thanks for the reviews.
As Imre pointed out there some further docs/function naming improvements
should probably be done to make the thing a bit less confusing. I'll
look at that as a followup.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2020-01-31 15:07 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
2020-01-29 14:05 ` Lisovskiy, Stanislav
2020-01-31 15:07 ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
2020-01-22 18:39 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
2020-01-22 18:43 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
2020-01-24 12:24 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
2020-01-24 15:06 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
2020-01-24 15:08 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
2020-01-24 15:19 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
2020-01-28 14:44 ` Lisovskiy, Stanislav
2020-01-28 15:29 ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
2020-01-22 19:00 ` Souza, Jose
2020-01-22 19:11 ` Ville Syrjälä
2020-01-27 15:02 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
2020-01-27 15:21 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
2020-01-27 15:25 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
2020-01-21 14:03 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-01-27 17:03 ` Imre Deak
2020-01-27 17:15 ` Ville Syrjälä
2020-01-27 17:54 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
2020-01-27 17:11 ` Imre Deak
2020-01-20 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework Patchwork
2020-01-21 2:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-21 13:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-21 17:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2) Patchwork
2020-01-21 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-23 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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