[Intel-gfx] [PATCH v3 00/15] Remaining RKL patches

[Intel-gfx] [PATCH v3 00/15] Remaining RKL patches

[Matt Roper]

I got pulled away by another task for a few weeks and had to put the RKL
upstreaming on hold, so these remaining patches needed a bit of
additional rebasing on top of other changes that have landed in the
meantime, but there weren't any serious conflicts.

The functional changes from the last series are relatively small:
 - Additional patch to only program ABOX_CTL on RKL and not the extra
   ABOX{1,2}_CTL registers that TGL added.  The bspec documentation here
   isn't fully updated yet, but we've confirmed experimentatlly that RKL
   doesn't have the additional register instances.

 - We now setup the transcoder mask properly in the device_info and use
   for_each_cpu_transcoder_masked() for our loops.

A couple of the patches included here already have r-b's, but since it's
been a while since they were originally posted it's probably worth
getting another CI run before applying them.

Aditya Swarup (1):
  drm/i915/rkl: Don't try to read out DSI transcoders

José Roberto de Souza (1):
  drm/i915/rkl: Disable PSR2

Lucas De Marchi (1):
  drm/i915/rkl: provide port/phy mapping for vbt

Matt Roper (12):
  drm/i915/rkl: Set transcoder mask properly
  drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
  drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1,2}
  drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
  drm/i915/rkl: Setup ports/phys
  drm/i915/rkl: Update TGP's pin mapping when paired with RKL
  drm/i915/rkl: Add DDC pin mapping
  drm/i915/rkl: Don't try to access transcoder D
  drm/i915/rkl: Handle comp master/slave relationships for PHYs
  drm/i915/rkl: Add DPLL4 support
  drm/i915/rkl: Handle HTI
  drm/i915/rkl: Add initial workarounds

 drivers/gpu/drm/i915/display/intel_bios.c     | 72 ++++++++++-----
 .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++-
 drivers/gpu/drm/i915/display/intel_display.c  | 82 ++++++++++++-----
 .../drm/i915/display/intel_display_power.c    | 46 +++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 22 ++++-
 drivers/gpu/drm/i915/display/intel_psr.c      | 15 ++++
 drivers/gpu/drm/i915/display/intel_sprite.c   |  5 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 88 ++++++++++++-------
 drivers/gpu/drm/i915/i915_drv.h               |  5 ++
 drivers/gpu/drm/i915/i915_irq.c               | 23 ++++-
 drivers/gpu/drm/i915/i915_pci.c               |  5 ++
 drivers/gpu/drm/i915/i915_reg.h               | 30 +++++--
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 16 files changed, 372 insertions(+), 116 deletions(-)

-- 
2.24.1

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[Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly

[Matt Roper]

Although we properly captured RKL's three pipes in the device info
structure, we forgot to make the corresponding update to the transcoder
mask.  Set this field so that our transcoder loops will operate
properly.

Fixes: 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 07b09af3a9c3..0ed586ee2047 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -881,6 +881,8 @@ static const struct intel_device_info rkl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ROCKETLAKE),
 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+		BIT(TRANSCODER_C),
 	.require_force_probe = 1,
 	.engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:15PM -0700, Matt Roper wrote:
> Although we properly captured RKL's three pipes in the device info
> structure, we forgot to make the corresponding update to the transcoder
> mask.  Set this field so that our transcoder loops will operate
> properly.
> 
> Fixes: 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids")
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Matches what I see in the spec.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 07b09af3a9c3..0ed586ee2047 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -881,6 +881,8 @@ static const struct intel_device_info rkl_info = {
>  	GEN12_FEATURES,
>  	PLATFORM(INTEL_ROCKETLAKE),
>  	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> +		BIT(TRANSCODER_C),
>  	.require_force_probe = 1,
>  	.engine_mask =
>  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> -- 
> 2.24.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Matt Roper]

RKL uses the same BW_BUDDY programming table as TGL, but programs the
values into a single set BUDDY0 set of registers rather than the
BUDDY1/BUDDY2 sets used by TGL.

Bspec: 49218
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
 2 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 72312b67b57a..2c1ce50b572b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	enum intel_dram_type type = dev_priv->dram_info.type;
 	u8 num_channels = dev_priv->dram_info.num_channels;
 	const struct buddy_page_mask *table;
-	int i;
+	int config, min_buddy, max_buddy, i;
 
 	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
 		/* Wa_1409767108: tgl */
@@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	else
 		table = tgl_buddy_page_masks;
 
-	for (i = 0; table[i].page_mask != 0; i++)
-		if (table[i].num_channels == num_channels &&
-		    table[i].type == type)
+	if (IS_ROCKETLAKE(dev_priv)) {
+		min_buddy = max_buddy = 0;
+	} else {
+		min_buddy = 1;
+		max_buddy = 2;
+	}
+
+	for (config = 0; table[config].page_mask != 0; config++)
+		if (table[config].num_channels == num_channels &&
+		    table[config].type == type)
 			break;
 
-	if (table[i].page_mask == 0) {
+	if (table[config].page_mask == 0) {
 		drm_dbg(&dev_priv->drm,
 			"Unknown memory configuration; disabling address buddy logic.\n");
-		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
-		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+		for (i = min_buddy; i <= max_buddy; i++)
+			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
+				       BW_BUDDY_DISABLE);
 	} else {
-		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
-			       table[i].page_mask);
-		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
-			       table[i].page_mask);
-
-		/* Wa_22010178259:tgl */
-		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
-			     BW_BUDDY_TLB_REQ_TIMER_MASK,
-			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
-		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
-			     BW_BUDDY_TLB_REQ_TIMER_MASK,
-			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
+		for (i = min_buddy; i <= max_buddy; i++) {
+			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
+				       table[config].page_mask);
+
+			/* Wa_22010178259:tgl,rkl */
+			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
+				     BW_BUDDY_TLB_REQ_TIMER_MASK,
+				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
+						    0x8));
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 578cfe11cbb9..3e79cefc510a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7837,13 +7837,19 @@ enum {
 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
 
-#define BW_BUDDY1_CTL			_MMIO(0x45140)
-#define BW_BUDDY2_CTL			_MMIO(0x45150)
+#define _BW_BUDDY0_CTL			0x45130
+#define _BW_BUDDY1_CTL			0x45140
+#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
+							 _BW_BUDDY0_CTL, \
+							 _BW_BUDDY1_CTL))
 #define   BW_BUDDY_DISABLE		REG_BIT(31)
 #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
 
-#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
-#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
+#define _BW_BUDDY0_PAGE_MASK		0x45134
+#define _BW_BUDDY1_PAGE_MASK		0x45144
+#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
+							 _BW_BUDDY0_PAGE_MASK, \
+							 _BW_BUDDY1_PAGE_MASK))
 
 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Aditya Swarup]

On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> RKL uses the same BW_BUDDY programming table as TGL, but programs the
> values into a single set BUDDY0 set of registers rather than the
> BUDDY1/BUDDY2 sets used by TGL.
> 
> Bspec: 49218
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
>  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
>  2 files changed, 35 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 72312b67b57a..2c1ce50b572b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	enum intel_dram_type type = dev_priv->dram_info.type;
>  	u8 num_channels = dev_priv->dram_info.num_channels;
>  	const struct buddy_page_mask *table;
> -	int i;
> +	int config, min_buddy, max_buddy, i;
>  
>  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>  		/* Wa_1409767108: tgl */
> @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	else
>  		table = tgl_buddy_page_masks;
>  
> -	for (i = 0; table[i].page_mask != 0; i++)
> -		if (table[i].num_channels == num_channels &&
> -		    table[i].type == type)
> +	if (IS_ROCKETLAKE(dev_priv)) {
> +		min_buddy = max_buddy = 0;
> +	} else {
> +		min_buddy = 1;
> +		max_buddy = 2;
> +	}
> +
> +	for (config = 0; table[config].page_mask != 0; config++)
> +		if (table[config].num_channels == num_channels &&
> +		    table[config].type == type)
>  			break;
>  
> -	if (table[i].page_mask == 0) {
> +	if (table[config].page_mask == 0) {
>  		drm_dbg(&dev_priv->drm,
>  			"Unknown memory configuration; disabling address buddy logic.\n");
> -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> +		for (i = min_buddy; i <= max_buddy; i++)
> +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> +				       BW_BUDDY_DISABLE);
>  	} else {
> -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> -			       table[i].page_mask);
> -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> -			       table[i].page_mask);
> -
> -		/* Wa_22010178259:tgl */
> -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> +		for (i = min_buddy; i <= max_buddy; i++) {
> +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> +				       table[config].page_mask);
> +
> +			/* Wa_22010178259:tgl,rkl */
> +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> +						    0x8));
We should be using REG_FIELD_PREP() in i915_reg.h to declare
TLB_REQ_TIMER value and then use the value here.
> +		}
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578cfe11cbb9..3e79cefc510a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7837,13 +7837,19 @@ enum {
>  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
>  
> -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> +#define _BW_BUDDY0_CTL			0x45130
> +#define _BW_BUDDY1_CTL			0x45140
> +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> +							 _BW_BUDDY0_CTL, \
> +							 _BW_BUDDY1_CTL))
>  #define   BW_BUDDY_DISABLE		REG_BIT(31)
>  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
>  
> -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> +#define _BW_BUDDY0_PAGE_MASK		0x45134
> +#define _BW_BUDDY1_PAGE_MASK		0x45144
> +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> +							 _BW_BUDDY0_PAGE_MASK, \
> +							 _BW_BUDDY1_PAGE_MASK))
>  
>  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> -- 
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Matt Roper]

On Wed, Jun 03, 2020 at 03:34:32PM -0700, Aditya Swarup wrote:
> On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> > RKL uses the same BW_BUDDY programming table as TGL, but programs the
> > values into a single set BUDDY0 set of registers rather than the
> > BUDDY1/BUDDY2 sets used by TGL.
> > 
> > Bspec: 49218
> > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
> >  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
> >  2 files changed, 35 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 72312b67b57a..2c1ce50b572b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >  	enum intel_dram_type type = dev_priv->dram_info.type;
> >  	u8 num_channels = dev_priv->dram_info.num_channels;
> >  	const struct buddy_page_mask *table;
> > -	int i;
> > +	int config, min_buddy, max_buddy, i;
> >  
> >  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> >  		/* Wa_1409767108: tgl */
> > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >  	else
> >  		table = tgl_buddy_page_masks;
> >  
> > -	for (i = 0; table[i].page_mask != 0; i++)
> > -		if (table[i].num_channels == num_channels &&
> > -		    table[i].type == type)
> > +	if (IS_ROCKETLAKE(dev_priv)) {
> > +		min_buddy = max_buddy = 0;
> > +	} else {
> > +		min_buddy = 1;
> > +		max_buddy = 2;
> > +	}
> > +
> > +	for (config = 0; table[config].page_mask != 0; config++)
> > +		if (table[config].num_channels == num_channels &&
> > +		    table[config].type == type)
> >  			break;
> >  
> > -	if (table[i].page_mask == 0) {
> > +	if (table[config].page_mask == 0) {
> >  		drm_dbg(&dev_priv->drm,
> >  			"Unknown memory configuration; disabling address buddy logic.\n");
> > -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> > -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> > +		for (i = min_buddy; i <= max_buddy; i++)
> > +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> > +				       BW_BUDDY_DISABLE);
> >  	} else {
> > -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> > -			       table[i].page_mask);
> > -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> > -			       table[i].page_mask);
> > -
> > -		/* Wa_22010178259:tgl */
> > -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > +		for (i = min_buddy; i <= max_buddy; i++) {
> > +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> > +				       table[config].page_mask);
> > +
> > +			/* Wa_22010178259:tgl,rkl */
> > +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> > +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> > +						    0x8));
> We should be using REG_FIELD_PREP() in i915_reg.h to declare
> TLB_REQ_TIMER value and then use the value here.

Any specific reason why?  The value "8" doesn't have any specific
hardware meaning that would be meaningful to define in the general
register definitions.  It's just a value that this specific hardware
workaround asked for in this case.  I'm not sure if we want to spread
the definition of the workaround into the register file if the value
isn't going to be meaningful to other driver programming or workarounds.


Matt

> > +		}
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 578cfe11cbb9..3e79cefc510a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7837,13 +7837,19 @@ enum {
> >  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
> >  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
> >  
> > -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> > -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> > +#define _BW_BUDDY0_CTL			0x45130
> > +#define _BW_BUDDY1_CTL			0x45140
> > +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> > +							 _BW_BUDDY0_CTL, \
> > +							 _BW_BUDDY1_CTL))
> >  #define   BW_BUDDY_DISABLE		REG_BIT(31)
> >  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
> >  
> > -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> > -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> > +#define _BW_BUDDY0_PAGE_MASK		0x45134
> > +#define _BW_BUDDY1_PAGE_MASK		0x45144
> > +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> > +							 _BW_BUDDY0_PAGE_MASK, \
> > +							 _BW_BUDDY1_PAGE_MASK))
> >  
> >  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
> >  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> > -- 
> > 2.24.1
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Aditya Swarup]

On Wed, Jun 03, 2020 at 04:12:59PM -0700, Matt Roper wrote:
> On Wed, Jun 03, 2020 at 03:34:32PM -0700, Aditya Swarup wrote:
> > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> > > RKL uses the same BW_BUDDY programming table as TGL, but programs the
> > > values into a single set BUDDY0 set of registers rather than the
> > > BUDDY1/BUDDY2 sets used by TGL.
> > > 
> > > Bspec: 49218
> > > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
> > >  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
> > >  2 files changed, 35 insertions(+), 23 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 72312b67b57a..2c1ce50b572b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > >  	enum intel_dram_type type = dev_priv->dram_info.type;
> > >  	u8 num_channels = dev_priv->dram_info.num_channels;
> > >  	const struct buddy_page_mask *table;
> > > -	int i;
> > > +	int config, min_buddy, max_buddy, i;
> > >  
> > >  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > >  		/* Wa_1409767108: tgl */
> > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > >  	else
> > >  		table = tgl_buddy_page_masks;
> > >  
> > > -	for (i = 0; table[i].page_mask != 0; i++)
> > > -		if (table[i].num_channels == num_channels &&
> > > -		    table[i].type == type)
> > > +	if (IS_ROCKETLAKE(dev_priv)) {
> > > +		min_buddy = max_buddy = 0;
> > > +	} else {
> > > +		min_buddy = 1;
> > > +		max_buddy = 2;
> > > +	}
> > > +
> > > +	for (config = 0; table[config].page_mask != 0; config++)
> > > +		if (table[config].num_channels == num_channels &&
> > > +		    table[config].type == type)
> > >  			break;
> > >  
> > > -	if (table[i].page_mask == 0) {
> > > +	if (table[config].page_mask == 0) {
> > >  		drm_dbg(&dev_priv->drm,
> > >  			"Unknown memory configuration; disabling address buddy logic.\n");
> > > -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> > > -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> > > +		for (i = min_buddy; i <= max_buddy; i++)
> > > +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> > > +				       BW_BUDDY_DISABLE);
> > >  	} else {
> > > -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> > > -			       table[i].page_mask);
> > > -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> > > -			       table[i].page_mask);
> > > -
> > > -		/* Wa_22010178259:tgl */
> > > -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> > > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > > -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> > > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > > +		for (i = min_buddy; i <= max_buddy; i++) {
> > > +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> > > +				       table[config].page_mask);
> > > +
> > > +			/* Wa_22010178259:tgl,rkl */
> > > +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> > > +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > +						    0x8));
> > We should be using REG_FIELD_PREP() in i915_reg.h to declare
> > TLB_REQ_TIMER value and then use the value here.
> 
> Any specific reason why?  The value "8" doesn't have any specific
> hardware meaning that would be meaningful to define in the general
> register definitions.  It's just a value that this specific hardware
> workaround asked for in this case.  I'm not sure if we want to spread
> the definition of the workaround into the register file if the value
> isn't going to be meaningful to other driver programming or workarounds.
> 
> 
> Matt
The value 8 is constant and as such should be defined in a header file
for that bitmask. If there was variable used to prepare the value on the
fly, I would have understood this usage.

If you are concerned about 8 being a random value and not spreading to
i915_reg.h, I would prefer a macro in i915_reg.h like:
#define TLB_REQ_TIMER(x)    REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,(x))       

Then the value doesn't filter to i915_reg.h and according to me looks
cleaner.

Most of the usage of REG_FIELD_PREP in *.c files is based on creating
bitfields using variable. Here we are using a constant which can easily
be moved to i915_reg.h. It shouldn't matter if it is a WA or not. 

Adi
> 
> > > +		}
> > >  	}
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 578cfe11cbb9..3e79cefc510a 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7837,13 +7837,19 @@ enum {
> > >  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
> > >  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
> > >  
> > > -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> > > -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> > > +#define _BW_BUDDY0_CTL			0x45130
> > > +#define _BW_BUDDY1_CTL			0x45140
> > > +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> > > +							 _BW_BUDDY0_CTL, \
> > > +							 _BW_BUDDY1_CTL))
> > >  #define   BW_BUDDY_DISABLE		REG_BIT(31)
> > >  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
> > >  
> > > -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> > > -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> > > +#define _BW_BUDDY0_PAGE_MASK		0x45134
> > > +#define _BW_BUDDY1_PAGE_MASK		0x45144
> > > +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> > > +							 _BW_BUDDY0_PAGE_MASK, \
> > > +							 _BW_BUDDY1_PAGE_MASK))
> > >  
> > >  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
> > >  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> > > -- 
> > > 2.24.1
> > > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> RKL uses the same BW_BUDDY programming table as TGL, but programs the
> values into a single set BUDDY0 set of registers rather than the
> BUDDY1/BUDDY2 sets used by TGL.

Maybe we just want some kind of HAS_ABOX() so we could use the same
thing here and in the ABOX_CTL programming?

> 
> Bspec: 49218
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
>  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
>  2 files changed, 35 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 72312b67b57a..2c1ce50b572b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	enum intel_dram_type type = dev_priv->dram_info.type;
>  	u8 num_channels = dev_priv->dram_info.num_channels;
>  	const struct buddy_page_mask *table;
> -	int i;
> +	int config, min_buddy, max_buddy, i;
>  
>  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>  		/* Wa_1409767108: tgl */
> @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	else
>  		table = tgl_buddy_page_masks;
>  
> -	for (i = 0; table[i].page_mask != 0; i++)
> -		if (table[i].num_channels == num_channels &&
> -		    table[i].type == type)
> +	if (IS_ROCKETLAKE(dev_priv)) {
> +		min_buddy = max_buddy = 0;
> +	} else {
> +		min_buddy = 1;
> +		max_buddy = 2;
> +	}
> +
> +	for (config = 0; table[config].page_mask != 0; config++)
> +		if (table[config].num_channels == num_channels &&
> +		    table[config].type == type)
>  			break;
>  
> -	if (table[i].page_mask == 0) {
> +	if (table[config].page_mask == 0) {
>  		drm_dbg(&dev_priv->drm,
>  			"Unknown memory configuration; disabling address buddy logic.\n");
> -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> +		for (i = min_buddy; i <= max_buddy; i++)
> +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> +				       BW_BUDDY_DISABLE);
>  	} else {
> -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> -			       table[i].page_mask);
> -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> -			       table[i].page_mask);
> -
> -		/* Wa_22010178259:tgl */
> -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> +		for (i = min_buddy; i <= max_buddy; i++) {
> +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> +				       table[config].page_mask);
> +
> +			/* Wa_22010178259:tgl,rkl */
> +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> +						    0x8));
> +		}
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578cfe11cbb9..3e79cefc510a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7837,13 +7837,19 @@ enum {
>  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
>  
> -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> +#define _BW_BUDDY0_CTL			0x45130
> +#define _BW_BUDDY1_CTL			0x45140
> +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> +							 _BW_BUDDY0_CTL, \
> +							 _BW_BUDDY1_CTL))
>  #define   BW_BUDDY_DISABLE		REG_BIT(31)
>  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
>  
> -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> +#define _BW_BUDDY0_PAGE_MASK		0x45134
> +#define _BW_BUDDY1_PAGE_MASK		0x45144
> +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> +							 _BW_BUDDY0_PAGE_MASK, \
> +							 _BW_BUDDY1_PAGE_MASK))
>  
>  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
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Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Matt Roper]

On Thu, Jun 04, 2020 at 08:01:57PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> > RKL uses the same BW_BUDDY programming table as TGL, but programs the
> > values into a single set BUDDY0 set of registers rather than the
> > BUDDY1/BUDDY2 sets used by TGL.
> 
> Maybe we just want some kind of HAS_ABOX() so we could use the same
> thing here and in the ABOX_CTL programming?

Although these are both related to how the display controller accesses
memory, I don't think they're quite a 1:1 mapping.  TGL has
MBUX_ABOX_CTL{0,1,2} (and we're directed to program all three), but only
has BW_BUDDY_CTL{1,2} and no 0 instance.

For now I'll just add separate bw_buddy and abox masks to our platform
device info structure.


Matt

> 
> > 
> > Bspec: 49218
> > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
> >  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
> >  2 files changed, 35 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 72312b67b57a..2c1ce50b572b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >  	enum intel_dram_type type = dev_priv->dram_info.type;
> >  	u8 num_channels = dev_priv->dram_info.num_channels;
> >  	const struct buddy_page_mask *table;
> > -	int i;
> > +	int config, min_buddy, max_buddy, i;
> >  
> >  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> >  		/* Wa_1409767108: tgl */
> > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >  	else
> >  		table = tgl_buddy_page_masks;
> >  
> > -	for (i = 0; table[i].page_mask != 0; i++)
> > -		if (table[i].num_channels == num_channels &&
> > -		    table[i].type == type)
> > +	if (IS_ROCKETLAKE(dev_priv)) {
> > +		min_buddy = max_buddy = 0;
> > +	} else {
> > +		min_buddy = 1;
> > +		max_buddy = 2;
> > +	}
> > +
> > +	for (config = 0; table[config].page_mask != 0; config++)
> > +		if (table[config].num_channels == num_channels &&
> > +		    table[config].type == type)
> >  			break;
> >  
> > -	if (table[i].page_mask == 0) {
> > +	if (table[config].page_mask == 0) {
> >  		drm_dbg(&dev_priv->drm,
> >  			"Unknown memory configuration; disabling address buddy logic.\n");
> > -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> > -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> > +		for (i = min_buddy; i <= max_buddy; i++)
> > +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> > +				       BW_BUDDY_DISABLE);
> >  	} else {
> > -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> > -			       table[i].page_mask);
> > -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> > -			       table[i].page_mask);
> > -
> > -		/* Wa_22010178259:tgl */
> > -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > +		for (i = min_buddy; i <= max_buddy; i++) {
> > +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> > +				       table[config].page_mask);
> > +
> > +			/* Wa_22010178259:tgl,rkl */
> > +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> > +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> > +						    0x8));
> > +		}
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 578cfe11cbb9..3e79cefc510a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7837,13 +7837,19 @@ enum {
> >  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
> >  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
> >  
> > -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> > -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> > +#define _BW_BUDDY0_CTL			0x45130
> > +#define _BW_BUDDY1_CTL			0x45140
> > +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> > +							 _BW_BUDDY0_CTL, \
> > +							 _BW_BUDDY1_CTL))
> >  #define   BW_BUDDY_DISABLE		REG_BIT(31)
> >  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
> >  
> > -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> > -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> > +#define _BW_BUDDY0_PAGE_MASK		0x45134
> > +#define _BW_BUDDY1_PAGE_MASK		0x45144
> > +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> > +							 _BW_BUDDY0_PAGE_MASK, \
> > +							 _BW_BUDDY1_PAGE_MASK))
> >  
> >  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
> >  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> > -- 
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2

[Ville Syrjälä]

On Thu, Jun 04, 2020 at 03:12:40PM -0700, Matt Roper wrote:
> On Thu, Jun 04, 2020 at 08:01:57PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> > > RKL uses the same BW_BUDDY programming table as TGL, but programs the
> > > values into a single set BUDDY0 set of registers rather than the
> > > BUDDY1/BUDDY2 sets used by TGL.
> > 
> > Maybe we just want some kind of HAS_ABOX() so we could use the same
> > thing here and in the ABOX_CTL programming?
> 
> Although these are both related to how the display controller accesses
> memory, I don't think they're quite a 1:1 mapping.  TGL has
> MBUX_ABOX_CTL{0,1,2} (and we're directed to program all three), but only
> has BW_BUDDY_CTL{1,2} and no 0 instance.

I see three different notes on this:

tgl style:
"Abox1 and Abox2 are used for pixel data reads. Program the BW_BUDDY1
 and BW_BUDDY2 registers."
abox0 is the legacy path, so doesn't need this stuff apparently.
abox1/2 are the dedicated path.

rkl style:
"Abox0 is used for pixel data reads. Program the BW_BUDDY0 registers."
the dedicated path is removed so I guess they had to add the buddy
registers for the legacy path abox.

some other style:
"Abox0 and Abox1 are used for pixel data reads. Program the BW_BUDDY0 and
 BW_BUDDY1 registers."
I presume this means the legacy path is getting nuked, and thus the
two aboxes for the dedicated path are just getting shifted down.
Unfortunately I can't find a hsd which tells the story. 

So yeah, there is a slight difference for the tgl style in that
we still want to program ABOX_CTL0 but not BW_BUDDY0.

> 
> For now I'll just add separate bw_buddy and abox masks to our platform
> device info structure.

Or could maybe just add an exception for tgl.

Either
if (HAS_ABOX(0) || IS_TGL)
	write(ABOX_CTL0);
...
or
if (HAS_ABOX(0) && !IS_TGL)
	write(BUDDY0);
...

would seem reasonable enough to me.

> 
> 
> Matt
> 
> > 
> > > 
> > > Bspec: 49218
> > > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
> > >  drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
> > >  2 files changed, 35 insertions(+), 23 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 72312b67b57a..2c1ce50b572b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > >  	enum intel_dram_type type = dev_priv->dram_info.type;
> > >  	u8 num_channels = dev_priv->dram_info.num_channels;
> > >  	const struct buddy_page_mask *table;
> > > -	int i;
> > > +	int config, min_buddy, max_buddy, i;
> > >  
> > >  	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > >  		/* Wa_1409767108: tgl */
> > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > >  	else
> > >  		table = tgl_buddy_page_masks;
> > >  
> > > -	for (i = 0; table[i].page_mask != 0; i++)
> > > -		if (table[i].num_channels == num_channels &&
> > > -		    table[i].type == type)
> > > +	if (IS_ROCKETLAKE(dev_priv)) {
> > > +		min_buddy = max_buddy = 0;
> > > +	} else {
> > > +		min_buddy = 1;
> > > +		max_buddy = 2;
> > > +	}
> > > +
> > > +	for (config = 0; table[config].page_mask != 0; config++)
> > > +		if (table[config].num_channels == num_channels &&
> > > +		    table[config].type == type)
> > >  			break;
> > >  
> > > -	if (table[i].page_mask == 0) {
> > > +	if (table[config].page_mask == 0) {
> > >  		drm_dbg(&dev_priv->drm,
> > >  			"Unknown memory configuration; disabling address buddy logic.\n");
> > > -		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> > > -		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> > > +		for (i = min_buddy; i <= max_buddy; i++)
> > > +			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> > > +				       BW_BUDDY_DISABLE);
> > >  	} else {
> > > -		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> > > -			       table[i].page_mask);
> > > -		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> > > -			       table[i].page_mask);
> > > -
> > > -		/* Wa_22010178259:tgl */
> > > -		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> > > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > > -		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> > > -			     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > -			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> > > +		for (i = min_buddy; i <= max_buddy; i++) {
> > > +			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> > > +				       table[config].page_mask);
> > > +
> > > +			/* Wa_22010178259:tgl,rkl */
> > > +			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> > > +				     BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > +				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> > > +						    0x8));
> > > +		}
> > >  	}
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 578cfe11cbb9..3e79cefc510a 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7837,13 +7837,19 @@ enum {
> > >  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
> > >  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
> > >  
> > > -#define BW_BUDDY1_CTL			_MMIO(0x45140)
> > > -#define BW_BUDDY2_CTL			_MMIO(0x45150)
> > > +#define _BW_BUDDY0_CTL			0x45130
> > > +#define _BW_BUDDY1_CTL			0x45140
> > > +#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
> > > +							 _BW_BUDDY0_CTL, \
> > > +							 _BW_BUDDY1_CTL))
> > >  #define   BW_BUDDY_DISABLE		REG_BIT(31)
> > >  #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
> > >  
> > > -#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
> > > -#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
> > > +#define _BW_BUDDY0_PAGE_MASK		0x45134
> > > +#define _BW_BUDDY1_PAGE_MASK		0x45144
> > > +#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
> > > +							 _BW_BUDDY0_PAGE_MASK, \
> > > +							 _BW_BUDDY1_PAGE_MASK))
> > >  
> > >  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
> > >  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
> > > -- 
> > > 2.24.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}

[Matt Roper]

Although RKL is a gen12 platform, it doesn't have the two extra
instances of the ABOX control register; we should only program
the single MBUS_ABOX_CTL on this platform.

Bspec: 50096
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2c1ce50b572b..37847b3d733c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4772,7 +4772,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 		MBUS_ABOX_BW_CREDIT(1);
 
 	intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val);
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (INTEL_GEN(dev_priv) >= 12 && !IS_ROCKETLAKE(dev_priv)) {
 		intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val);
 		intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val);
 	}
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:17PM -0700, Matt Roper wrote:
> Although RKL is a gen12 platform, it doesn't have the two extra
> instances of the ABOX control register; we should only program
> the single MBUS_ABOX_CTL on this platform.
> 
> Bspec: 50096
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2c1ce50b572b..37847b3d733c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4772,7 +4772,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  		MBUS_ABOX_BW_CREDIT(1);
>  
>  	intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val);
> -	if (INTEL_GEN(dev_priv) >= 12) {
> +	if (INTEL_GEN(dev_priv) >= 12 && !IS_ROCKETLAKE(dev_priv)) {
>  		intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val);
>  		intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val);
>  	}

Can't find anyting definitive in bspec, so not 100% sure but
since you say it gives unclaim reg errors it seems correct.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Though I think I'd like to see that HAS_ABOX() thing I suggested
and use it here as well.

> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout

[Matt Roper]

RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.

v2:
 - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
 - Checkpatch style fixes

Bspec: 50287
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 18 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h              |  6 ++++++
 3 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 236f3762b6f9..6752f63d1686 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2736,7 +2736,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 				     enum phy phy)
 {
-	if (intel_phy_is_combo(dev_priv, phy)) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	} else if (intel_phy_is_combo(dev_priv, phy)) {
 		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2763,6 +2765,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
+		u32 mask, sel;
+
+		if (IS_ROCKETLAKE(dev_priv)) {
+			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		} else {
+			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		}
+
 		/*
 		 * Even though this register references DDIs, note that we
 		 * want to pass the PHY rather than the port (DDI).  For
@@ -2773,8 +2785,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		 *   Clock Select chooses the PLL for both DDIA and DDID and
 		 *   drives port A in all cases."
 		 */
-		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		val &= ~mask;
+		val |= sel;
 		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a9f752d26b4e..b4f8c88c779f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10782,9 +10782,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	u32 temp;
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
-		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
-			ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		u32 mask, shift;
+
+		if (IS_ROCKETLAKE(dev_priv)) {
+			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		} else {
+			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		}
+
+		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+		id = temp >> shift;
 		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
 	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3e79cefc510a..db031269a05a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10173,12 +10173,18 @@ enum skl_power_gate {
 
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
 						       (tc_port) + 12 : \
 						       (tc_port) - PORT_TC4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
+	(3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
+	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
-- 
2.24.1

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[Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys

[Matt Roper]

RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.

Bspec: 49181
Cc: Imre Deak <imre.deak@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++-
 2 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b4f8c88c779f..019fef8023ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7218,30 +7218,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
-
-	if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_ROCKETLAKE(dev_priv))
+		return phy <= PHY_D;
+	else if (IS_ELKHARTLAKE(dev_priv))
 		return phy <= PHY_C;
-
-	if (INTEL_GEN(dev_priv) >= 11)
+	else if (INTEL_GEN(dev_priv) >= 11)
 		return phy <= PHY_B;
-
-	return false;
+	else
+		return false;
 }
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_ROCKETLAKE(dev_priv))
+		return false;
+	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
-
-	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
-
-	return false;
+	else
+		return false;
 }
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+		return (enum phy)port - 1;
+	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
 		return PHY_A;
 
 	return (enum phy)port;
@@ -16829,7 +16832,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_D);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index db031269a05a..85137d268c4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
+#define _RKL_COMBOPHY_D			0x161000
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
-					      _EHL_COMBOPHY_C)
+					      _EHL_COMBOPHY_C, \
+					      _RKL_COMBOPHY_D)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:19PM -0700, Matt Roper wrote:
> RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
> 
> Bspec: 49181
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++-
>  2 files changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b4f8c88c779f..019fef8023ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7218,30 +7218,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  {
>  	if (phy == PHY_NONE)
>  		return false;
> -
> -	if (IS_ELKHARTLAKE(dev_priv))
> +	else if (IS_ROCKETLAKE(dev_priv))
> +		return phy <= PHY_D;

Or just 'return true' since combo PHYs is all we have.

/me weeps when looking at these functions.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	else if (IS_ELKHARTLAKE(dev_priv))
>  		return phy <= PHY_C;
> -
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		return phy <= PHY_B;
> -
> -	return false;
> +	else
> +		return false;
>  }
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	if (INTEL_GEN(dev_priv) >= 12)
> +	if (IS_ROCKETLAKE(dev_priv))
> +		return false;
> +	else if (INTEL_GEN(dev_priv) >= 12)
>  		return phy >= PHY_D && phy <= PHY_I;
> -
> -	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> +	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>  		return phy >= PHY_C && phy <= PHY_F;
> -
> -	return false;
> +	else
> +		return false;
>  }
>  
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>  {
> -	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> +	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
> +		return (enum phy)port - 1;
> +	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>  		return PHY_A;
>  
>  	return (enum phy)port;
> @@ -16829,7 +16832,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
>  		return;
>  
> -	if (INTEL_GEN(dev_priv) >= 12) {
> +	if (IS_ROCKETLAKE(dev_priv)) {
> +		intel_ddi_init(dev_priv, PORT_A);
> +		intel_ddi_init(dev_priv, PORT_B);
> +		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> +		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> +	} else if (INTEL_GEN(dev_priv) >= 12) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_D);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index db031269a05a..85137d268c4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_COMBOPHY_A			0x162000
>  #define _ICL_COMBOPHY_B			0x6C000
>  #define _EHL_COMBOPHY_C			0x160000
> +#define _RKL_COMBOPHY_D			0x161000
>  #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>  					      _ICL_COMBOPHY_B, \
> -					      _EHL_COMBOPHY_C)
> +					      _EHL_COMBOPHY_C, \
> +					      _RKL_COMBOPHY_D)
>  
>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt

[Matt Roper]

From: Lucas De Marchi <lucas.demarchi@intel.com>

RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of view, but
that does not happen in practice.

Provide a table to convert the child devices to the "correct" port
numbering we use. Now this is the output we get while reading the VBT:

DDIA:
[drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)

DDIB:
[drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)

DDI USBC1:
[drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)

DDI USBC2:
[drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
 1 file changed, 51 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..4f1a72a90b8f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 	return 0;
 }
 
-static enum port dvo_port_to_port(u8 dvo_port)
+static enum port __dvo_port_to_port(int n_ports, int n_dvo,
+				    const int port_mapping[][3], u8 dvo_port)
 {
-	/*
-	 * Each DDI port can have more than one value on the "DVO Port" field,
-	 * so look for all the possible values for each port.
-	 */
-	static const int dvo_ports[][3] = {
-		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
-		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
-		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
-		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
-		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
-		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
-		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
-	};
 	enum port port;
 	int i;
 
-	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
-		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
-			if (dvo_ports[port][i] == -1)
+	for (port = PORT_A; port < n_ports; port++) {
+		for (i = 0; i < n_dvo; i++) {
+			if (port_mapping[port][i] == -1)
 				break;
 
-			if (dvo_port == dvo_ports[port][i])
+			if (dvo_port == port_mapping[port][i])
 				return port;
 		}
 	}
@@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
 	return PORT_NONE;
 }
 
+static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
+				  u8 dvo_port)
+{
+	/*
+	 * Each DDI port can have more than one value on the "DVO Port" field,
+	 * so look for all the possible values for each port.
+	 */
+	static const int port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
+		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+	};
+	/*
+	 * Bspec lists the ports as A, B, C, D - however internally in our
+	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
+	 * registers in Display Engine match the right offsets. Apply the
+	 * mapping here to translate from VBT to internal convention.
+	 */
+	static const int rkl_port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_C] = { -1 },
+		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+	};
+
+	if (IS_ROCKETLAKE(dev_priv))
+		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
+					  ARRAY_SIZE(rkl_port_mapping[0]),
+					  rkl_port_mapping,
+					  dvo_port);
+	else
+		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
+					  ARRAY_SIZE(port_mapping[0]),
+					  port_mapping,
+					  dvo_port);
+}
+
 static void parse_ddi_port(struct drm_i915_private *dev_priv,
 			   struct display_device_data *devdata,
 			   u8 bdb_version)
@@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
 	enum port port;
 
-	port = dvo_port_to_port(child->dvo_port);
+	port = dvo_port_to_port(dev_priv, child->dvo_port);
 	if (port == PORT_NONE)
 		return;
 
@@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		aux_ch = AUX_CH_C;
+		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = AUX_CH_D;
+		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
-- 
2.24.1

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[Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL

[Matt Roper]

When TGP is paired with RKL it uses a different HPD pin mapping than
when paired with TGL.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 490574669eaa..f3ea81a17352 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
 	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
 };
 
+/*
+ * TGP when paired with RKL has different pin mappings than when paired
+ * with TGL.
+ */
+static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = {
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+	[HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
+	[HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
+};
+
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 {
 	struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
 		return;
 
-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+	if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv))
+		hpd->pch_hpd = hpd_rkl_tgp;
+	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
 		hpd->pch_hpd = hpd_tgp;
 	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
 		hpd->pch_hpd = hpd_icp;
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote:
> When TGP is paired with RKL it uses a different HPD pin mapping than
> when paired with TGL.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 490574669eaa..f3ea81a17352 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
>  	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
>  };
>  
> +/*
> + * TGP when paired with RKL has different pin mappings than when paired
> + * with TGL.
> + */
> +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = {
> +	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> +	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> +	[HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> +	[HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> +};

Hmm. So basically it looks like we'd want to pick the hpd_pin
based on the DDI rather than the PHY on this platform?

OK, I guess we need to remap somehow. The question is
whether we want to do it before or after selecting hpd_pin...
I think we would want to do it before, as otherwise the
long_detect() stuff won't work right AFAICS. Or am I
missing something?

Side note: we should probably convert the long_detect()
switches to arrays just like we have for the isr bits here.
Would potentially avoid having to touch that code every time
they tweak these thinhs in hw.

And in fact it looks like icp already has all the same hpd
pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/
and for icl/jsl we should remap hpd_pin as well. Oh and the
mcc case would just need a slightly different mapping of
port C -> HPD_PORT_D (aka. tc1).

This way all the hpd[] arrays and whatnot would just be based
on the actual pch type and not based on what it happens to be
paired with.

Anwyays, most of that is out of scope for this rkl stuff, so
I guess for now just add a bit of logic to remap hpd_pin for rkl?

> +
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_hotplug *hpd = &dev_priv->hotplug;
> @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>  	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>  		return;
>  
> -	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> +	if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv))
> +		hpd->pch_hpd = hpd_rkl_tgp;
> +	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
>  		hpd->pch_hpd = hpd_tgp;
>  	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>  		hpd->pch_hpd = hpd_icp;
> -- 
> 2.24.1

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL

[Matt Roper]

On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote:
> > When TGP is paired with RKL it uses a different HPD pin mapping than
> > when paired with TGL.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++-
> >  1 file changed, 14 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 490574669eaa..f3ea81a17352 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> >  	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> >  };
> >  
> > +/*
> > + * TGP when paired with RKL has different pin mappings than when paired
> > + * with TGL.
> > + */
> > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = {
> > +	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> > +	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> > +	[HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> > +	[HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> > +};
> 
> Hmm. So basically it looks like we'd want to pick the hpd_pin
> based on the DDI rather than the PHY on this platform?

I may be misinterpreting the table on bspec 49181, but I *think* it
looks like we use the DDI when paired with a TGP PCH and the PHY when
paired with CMP PCH.  So if I just set the hpd_pin based on the DDI,
then I think that will break the CMP-based systems (although I haven't
tested on one of those, so I'm not 100% sure).


Matt

> 
> OK, I guess we need to remap somehow. The question is
> whether we want to do it before or after selecting hpd_pin...
> I think we would want to do it before, as otherwise the
> long_detect() stuff won't work right AFAICS. Or am I
> missing something?
> 
> Side note: we should probably convert the long_detect()
> switches to arrays just like we have for the isr bits here.
> Would potentially avoid having to touch that code every time
> they tweak these thinhs in hw.
> 
> And in fact it looks like icp already has all the same hpd
> pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/
> and for icl/jsl we should remap hpd_pin as well. Oh and the
> mcc case would just need a slightly different mapping of
> port C -> HPD_PORT_D (aka. tc1).
> 
> This way all the hpd[] arrays and whatnot would just be based
> on the actual pch type and not based on what it happens to be
> paired with.
> 
> Anwyays, most of that is out of scope for this rkl stuff, so
> I guess for now just add a bit of logic to remap hpd_pin for rkl?
> 
> > +
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> >  {
> >  	struct i915_hotplug *hpd = &dev_priv->hotplug;
> > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> >  	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> >  		return;
> >  
> > -	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > +	if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv))
> > +		hpd->pch_hpd = hpd_rkl_tgp;
> > +	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> >  		hpd->pch_hpd = hpd_tgp;
> >  	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> >  		hpd->pch_hpd = hpd_icp;
> > -- 
> > 2.24.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL

[Ville Syrjälä]

On Thu, Jun 04, 2020 at 04:18:49PM -0700, Matt Roper wrote:
> On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote:
> > > When TGP is paired with RKL it uses a different HPD pin mapping than
> > > when paired with TGL.
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++-
> > >  1 file changed, 14 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index 490574669eaa..f3ea81a17352 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> > >  	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> > >  };
> > >  
> > > +/*
> > > + * TGP when paired with RKL has different pin mappings than when paired
> > > + * with TGL.
> > > + */
> > > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = {
> > > +	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> > > +	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> > > +	[HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> > > +	[HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> > > +};
> > 
> > Hmm. So basically it looks like we'd want to pick the hpd_pin
> > based on the DDI rather than the PHY on this platform?
> 
> I may be misinterpreting the table on bspec 49181, but I *think* it
> looks like we use the DDI when paired with a TGP PCH and the PHY when
> paired with CMP PCH.  So if I just set the hpd_pin based on the DDI,
> then I think that will break the CMP-based systems (although I haven't
> tested on one of those, so I'm not 100% sure).

After staring at the spec+code a bit I think what I want to
do is introduce proper HPD_PORT_TC1-6 enums (and remove
HPD_PORT_F+ since they become unused).

In the meantime I think assigning hpd_pin in a custom way
for rkl only should work.

> 
> 
> Matt
> 
> > 
> > OK, I guess we need to remap somehow. The question is
> > whether we want to do it before or after selecting hpd_pin...
> > I think we would want to do it before, as otherwise the
> > long_detect() stuff won't work right AFAICS. Or am I
> > missing something?
> > 
> > Side note: we should probably convert the long_detect()
> > switches to arrays just like we have for the isr bits here.
> > Would potentially avoid having to touch that code every time
> > they tweak these thinhs in hw.
> > 
> > And in fact it looks like icp already has all the same hpd
> > pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/
> > and for icl/jsl we should remap hpd_pin as well. Oh and the
> > mcc case would just need a slightly different mapping of
> > port C -> HPD_PORT_D (aka. tc1).
> > 
> > This way all the hpd[] arrays and whatnot would just be based
> > on the actual pch type and not based on what it happens to be
> > paired with.
> > 
> > Anwyays, most of that is out of scope for this rkl stuff, so
> > I guess for now just add a bit of logic to remap hpd_pin for rkl?
> > 
> > > +
> > >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > >  {
> > >  	struct i915_hotplug *hpd = &dev_priv->hotplug;
> > > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > >  	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> > >  		return;
> > >  
> > > -	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > > +	if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv))
> > > +		hpd->pch_hpd = hpd_rkl_tgp;
> > > +	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > >  		hpd->pch_hpd = hpd_tgp;
> > >  	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> > >  		hpd->pch_hpd = hpd_icp;
> > > -- 
> > > 2.24.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

-- 
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Intel
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[Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping

[Matt Roper]

The pin mapping for the final two outputs varies according to which PCH
is present on the platform:  with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.

Bspec: 49181
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 010f37240710..a31a98d26882 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return ddc_pin;
 }
 
+static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	WARN_ON(port == PORT_C);
+
+	/*
+	 * Pin mapping for RKL depends on which PCH is present.  With TGP, the
+	 * final two outputs use type-c pins, even though they're actually
+	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
+	 * all outputs.
+	 */
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
+		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
+
+	return GMBUS_PIN_1_BXT + phy;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (HAS_PCH_MCC(dev_priv))
+	if (IS_ROCKETLAKE(dev_priv))
+		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
+	else if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
-- 
2.24.1

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[Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D

[Matt Roper]

There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes.  We should add checks for transcoder
existence where appropriate.

v2: Move one transcoder check that wound up in the wrong function after
    conflict resolution.  It belongs in bdw_get_trans_port_sync_config
    rather than bxt_get_dsi_transcoder_state.

v3: Switch loops to use for_each_cpu_transcoder_masked() since this
    iterator already checks the platform's transcoder mask for us.
    (Ville)

Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f3ea81a17352..40a71c4a1ef5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2885,13 +2885,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
 	enum pipe pipe;
+	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
 
 	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		enum transcoder trans;
 
-		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
 			enum intel_display_power_domain domain;
 
 			domain = POWER_DOMAIN_TRANSCODER(trans);
@@ -3413,6 +3415,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
 	u32 de_port_enables;
 	u32 de_misc_masked = GEN8_DE_EDP_PSR;
+	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
 	enum pipe pipe;
 
 	if (INTEL_GEN(dev_priv) <= 10)
@@ -3433,7 +3437,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 12) {
 		enum transcoder trans;
 
-		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
 			enum intel_display_power_domain domain;
 
 			domain = POWER_DOMAIN_TRANSCODER(trans);
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:23PM -0700, Matt Roper wrote:
> There are a couple places in our driver that loop over transcoders A..D
> for gen11+; since RKL only has three pipes/transcoders, this can lead to
> unclaimed register reads/writes.  We should add checks for transcoder
> existence where appropriate.
> 
> v2: Move one transcoder check that wound up in the wrong function after
>     conflict resolution.  It belongs in bdw_get_trans_port_sync_config
>     rather than bxt_get_dsi_transcoder_state.
> 
> v3: Switch loops to use for_each_cpu_transcoder_masked() since this
>     iterator already checks the platform's transcoder mask for us.
>     (Ville)
> 
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f3ea81a17352..40a71c4a1ef5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2885,13 +2885,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
>  	enum pipe pipe;
> +	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
>  
>  	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		enum transcoder trans;
>  
> -		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> +		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
>  			enum intel_display_power_domain domain;
>  
>  			domain = POWER_DOMAIN_TRANSCODER(trans);
> @@ -3413,6 +3415,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
>  	u32 de_port_enables;
>  	u32 de_misc_masked = GEN8_DE_EDP_PSR;
> +	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
>  	enum pipe pipe;
>  
>  	if (INTEL_GEN(dev_priv) <= 10)
> @@ -3433,7 +3437,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		enum transcoder trans;
>  
> -		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> +		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
>  			enum intel_display_power_domain domain;
>  
>  			domain = POWER_DOMAIN_TRANSCODER(trans);
> -- 
> 2.24.1

-- 
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[Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders

[Matt Roper]

From: Aditya Swarup <aditya.swarup@intel.com>

RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
transcoder registers.

v2(MattR):
 - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask
   against the platform's cpu_transcoder_mask to filter out the ones
   that don't exist on a given platform.  (Ville)

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 019fef8023ca..bcc6dc4e321b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10904,19 +10904,13 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum intel_display_power_domain power_domain;
-	unsigned long panel_transcoder_mask = 0;
+	unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP) |
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
 	unsigned long enabled_panel_transcoders = 0;
 	enum transcoder panel_transcoder;
 	intel_wakeref_t wf;
 	u32 tmp;
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		panel_transcoder_mask |=
-			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
-
-	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP))
-		panel_transcoder_mask |= BIT(TRANSCODER_EDP);
-
 	/*
 	 * The pipe->transcoder mapping is fixed with the exception of the eDP
 	 * and DSI transcoders handled below.
@@ -10927,6 +10921,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
 	 * consistency and less surprising code; it's in always on power).
 	 */
+	panel_transcoder_mask &= INTEL_INFO(dev_priv)->cpu_transcoder_mask;
 	for_each_set_bit(panel_transcoder,
 			 &panel_transcoder_mask,
 			 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:24PM -0700, Matt Roper wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
> 
> RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
> transcoder registers.
> 
> v2(MattR):
>  - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask
>    against the platform's cpu_transcoder_mask to filter out the ones
>    that don't exist on a given platform.  (Ville)
> 
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 019fef8023ca..bcc6dc4e321b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10904,19 +10904,13 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum intel_display_power_domain power_domain;
> -	unsigned long panel_transcoder_mask = 0;
> +	unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP) |
> +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);

TRANSCODER_DSI_0/1 alias TRANSCODER_DSI_A/C which we do not
want in this mask.

>  	unsigned long enabled_panel_transcoders = 0;
>  	enum transcoder panel_transcoder;
>  	intel_wakeref_t wf;
>  	u32 tmp;
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		panel_transcoder_mask |=
> -			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
> -
> -	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP))
> -		panel_transcoder_mask |= BIT(TRANSCODER_EDP);
> -
>  	/*
>  	 * The pipe->transcoder mapping is fixed with the exception of the eDP
>  	 * and DSI transcoders handled below.
> @@ -10927,6 +10921,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>  	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
>  	 * consistency and less surprising code; it's in always on power).
>  	 */
> +	panel_transcoder_mask &= INTEL_INFO(dev_priv)->cpu_transcoder_mask;
>  	for_each_set_bit(panel_transcoder,
>  			 &panel_transcoder_mask,
>  			 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {

Can't we just use for_each_cpu_transcoder_masked() ?

> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs

[Matt Roper]

Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register.  Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.

Bspec: 49291
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 43d8784f6fa0..77b04bb3ec62 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
 	return false;
 }
 
+static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
+{
+	/*
+	 * Certain PHYs are connected to compensation resistors and act
+	 * as masters to other PHYs.
+	 *
+	 * ICL,TGL:
+	 *   A(master) -> B(slave), C(slave)
+	 * RKL:
+	 *   A(master) -> B(slave)
+	 *   C(master) -> D(slave)
+	 *
+	 * We must set the IREFGEN bit for any PHY acting as a master
+	 * to another PHY.
+	 */
+	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+		return true;
+
+	return phy == PHY_A;
+}
+
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				       enum phy phy)
 {
@@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 
 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	if (phy == PHY_A) {
+	if (phy_is_master(dev_priv, phy)) {
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
@@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 skip_phy_misc:
 		cnl_set_procmon_ref_values(dev_priv, phy);
 
-		if (phy == PHY_A) {
+		if (phy_is_master(dev_priv, phy)) {
 			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
 			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
-- 
2.24.1

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[Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support

[Matt Roper]

Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display.  Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1.  And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.

v2:
 - Add new .update_ref_clks() hook.

Bspec: 49202
Bspec: 49443
Bspec: 50288
Bspec: 50289
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++--
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec..b5f4d4cef682 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 		return false;
 	}
 
-	if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+	if (IS_ROCKETLAKE(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	else
+	} else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+		dpll_mask =
+			BIT(DPLL_ID_EHL_DPLL4) |
+			BIT(DPLL_ID_ICL_DPLL1) |
+			BIT(DPLL_ID_ICL_DPLL0);
+	} else {
 		dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
+	}
 
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
@@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info rkl_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr rkl_pll_mgr = {
+	.dpll_info = rkl_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_ROCKETLAKE(dev_priv))
+		dpll_mgr = &rkl_pll_mgr;
+	else if (INTEL_GEN(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
 	else if (IS_ELKHARTLAKE(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
-- 
2.24.1

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[Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI

[Matt Roper]

If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage.  Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.

v2:
 - Fix minor checkpatch warnings

Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 30 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 drivers/gpu/drm/i915/i915_drv.h               |  3 ++
 drivers/gpu/drm/i915/i915_reg.h               |  6 ++++
 5 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bcc6dc4e321b..cdd84a419cf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
 #include "display/intel_dp_mst.h"
+#include "display/intel_dpll_mgr.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
 	intel_pps_unlock_regs_wa(dev_priv);
 }
 
+static bool hti_uses_phy(u32 hdport_state, enum phy phy)
+{
+	return hdport_state & HDPORT_ENABLED &&
+		(hdport_state & HDPORT_PHY_USED_DP(phy) ||
+		 hdport_state & HDPORT_PHY_USED_HDMI(phy));
+}
+
 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 {
 	struct intel_encoder *encoder;
@@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_ROCKETLAKE(dev_priv)) {
-		intel_ddi_init(dev_priv, PORT_A);
-		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		/*
+		 * If HTI (aka HDPORT) is enabled at boot, it may have taken
+		 * over some of the PHYs and made them unavailable to the
+		 * driver.  In that case we should skip initializing the
+		 * corresponding outputs.
+		 */
+		u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+
+		if (!hti_uses_phy(hdport_state, PHY_A))
+			intel_ddi_init(dev_priv, PORT_A);
+		if (!hti_uses_phy(hdport_state, PHY_B))
+			intel_ddi_init(dev_priv, PORT_B);
+		if (!hti_uses_phy(hdport_state, PHY_C))
+			intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		if (!hti_uses_phy(hdport_state, PHY_D))
+			intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
@@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 	intel_dpll_readout_hw_state(dev_priv);
 
+	dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
+
 	for_each_intel_encoder(dev, encoder) {
 		pipe = 0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b5f4d4cef682..6f59f9ec453b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+/*
+ * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
+ * unavailable for use.
+ */
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
+{
+	u32 hdport_state;
+
+	if (!IS_ROCKETLAKE(dev_priv))
+		return 0;
+
+	hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+	if (!(hdport_state & HDPORT_ENABLED))
+		return 0;
+
+	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
+}
+
 static struct intel_shared_dpll *
 intel_find_shared_dpll(struct intel_atomic_state *state,
 		       const struct intel_crtc *crtc,
@@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
 
+	/* Eliminate DPLLs from consideration if reserved by HTI */
+	dpll_mask &= ~dev_priv->hti_pll_mask;
+
 	for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
 		pll = &dev_priv->dpll.shared_dplls[i];
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..ac2238646fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_device *dev);
 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
 
 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 			      const struct intel_dpll_hw_state *hw_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e99255e17eb7..668b3c9cf3ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1037,6 +1037,9 @@ struct drm_i915_private {
 
 	struct intel_l3_parity l3_parity;
 
+	/* Mask of PLLs reserved for use by HTI and unavailable to driver. */
+	u32 hti_pll_mask;
+
 	/*
 	 * edram size in MB.
 	 * Cannot be determined by PCIID. You must always read a register.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85137d268c4a..b9faf0f978cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
+#define HDPORT_STATE			_MMIO(0x45050)
+#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*(phy) + 2)
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*(phy) + 1)
+#define   HDPORT_ENABLED		REG_BIT(0)
+
 /* Make render/texture TLB fetches lower priorty than associated data
  *   fetches. This is not turned on by default
  */
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI

[Ville Syrjälä]

On Wed, Jun 03, 2020 at 02:15:27PM -0700, Matt Roper wrote:
> If HTI (also sometimes called HDPORT) is enabled at startup, it may be

whatis HTI?

> using some of the PHYs and DPLLs making them unavailable for general
> usage.  Let's read out the HDPORT_STATE register and avoid making use of
> resources that HTI is already using.
> 
> v2:
>  - Fix minor checkpatch warnings
> 
> Bspec: 49189
> Bspec: 53707
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 30 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
>  drivers/gpu/drm/i915/i915_drv.h               |  3 ++
>  drivers/gpu/drm/i915/i915_reg.h               |  6 ++++
>  5 files changed, 57 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bcc6dc4e321b..cdd84a419cf7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -46,6 +46,7 @@
>  #include "display/intel_ddi.h"
>  #include "display/intel_dp.h"
>  #include "display/intel_dp_mst.h"
> +#include "display/intel_dpll_mgr.h"
>  #include "display/intel_dsi.h"
>  #include "display/intel_dvo.h"
>  #include "display/intel_gmbus.h"
> @@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
>  	intel_pps_unlock_regs_wa(dev_priv);
>  }
>  
> +static bool hti_uses_phy(u32 hdport_state, enum phy phy)
> +{
> +	return hdport_state & HDPORT_ENABLED &&
> +		(hdport_state & HDPORT_PHY_USED_DP(phy) ||
> +		 hdport_state & HDPORT_PHY_USED_HDMI(phy));
> +}
> +
>  static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_encoder *encoder;
> @@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  		return;
>  
>  	if (IS_ROCKETLAKE(dev_priv)) {
> -		intel_ddi_init(dev_priv, PORT_A);
> -		intel_ddi_init(dev_priv, PORT_B);
> -		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> -		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> +		/*
> +		 * If HTI (aka HDPORT) is enabled at boot, it may have taken
> +		 * over some of the PHYs and made them unavailable to the
> +		 * driver.  In that case we should skip initializing the
> +		 * corresponding outputs.
> +		 */
> +		u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> +
> +		if (!hti_uses_phy(hdport_state, PHY_A))
> +			intel_ddi_init(dev_priv, PORT_A);
> +		if (!hti_uses_phy(hdport_state, PHY_B))
> +			intel_ddi_init(dev_priv, PORT_B);
> +		if (!hti_uses_phy(hdport_state, PHY_C))
> +			intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> +		if (!hti_uses_phy(hdport_state, PHY_D))
> +			intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
>  	} else if (INTEL_GEN(dev_priv) >= 12) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
> @@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  
>  	intel_dpll_readout_hw_state(dev_priv);
>  
> +	dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
> +
>  	for_each_intel_encoder(dev, encoder) {
>  		pipe = 0;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b5f4d4cef682..6f59f9ec453b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  	mutex_unlock(&dev_priv->dpll.lock);
>  }
>  
> +/*
> + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
> + * unavailable for use.
> + */
> +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
> +{
> +	u32 hdport_state;
> +
> +	if (!IS_ROCKETLAKE(dev_priv))
> +		return 0;
> +
> +	hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> +	if (!(hdport_state & HDPORT_ENABLED))
> +		return 0;
> +
> +	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
> +}
> +
>  static struct intel_shared_dpll *
>  intel_find_shared_dpll(struct intel_atomic_state *state,
>  		       const struct intel_crtc *crtc,
> @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
>  
>  	drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
>  
> +	/* Eliminate DPLLs from consideration if reserved by HTI */
> +	dpll_mask &= ~dev_priv->hti_pll_mask;
> +
>  	for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
>  		pll = &dev_priv->dpll.shared_dplls[i];
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 5d9a2bc371e7..ac2238646fe7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
>  void intel_shared_dpll_init(struct drm_device *dev);
>  void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
>  void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
> +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
>  
>  void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
>  			      const struct intel_dpll_hw_state *hw_state);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e99255e17eb7..668b3c9cf3ae 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1037,6 +1037,9 @@ struct drm_i915_private {
>  
>  	struct intel_l3_parity l3_parity;
>  
> +	/* Mask of PLLs reserved for use by HTI and unavailable to driver. */
> +	u32 hti_pll_mask;
> +
>  	/*
>  	 * edram size in MB.
>  	 * Cannot be determined by PCIID. You must always read a register.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85137d268c4a..b9faf0f978cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
>  #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
>  
> +#define HDPORT_STATE			_MMIO(0x45050)
> +#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
> +#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*(phy) + 2)
> +#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*(phy) + 1)
> +#define   HDPORT_ENABLED		REG_BIT(0)
> +
>  /* Make render/texture TLB fetches lower priorty than associated data
>   *   fetches. This is not turned on by default
>   */
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI

[Matt Roper]

On Thu, Jun 04, 2020 at 07:59:55PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 03, 2020 at 02:15:27PM -0700, Matt Roper wrote:
> > If HTI (also sometimes called HDPORT) is enabled at startup, it may be
> 
> whatis HTI?

That's not really clear in the bspec or any other documents I've seen.
It sounds like its something setup by the boot firmware that can
potentially steal PLL and PHYs away.  Driver-wise there doesn't seem to
be much we need to do other than avoid using the reserved resources,
sort of like how we avoid using fused off units.


Matt

> 
> > using some of the PHYs and DPLLs making them unavailable for general
> > usage.  Let's read out the HDPORT_STATE register and avoid making use of
> > resources that HTI is already using.
> > 
> > v2:
> >  - Fix minor checkpatch warnings
> > 
> > Bspec: 49189
> > Bspec: 53707
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 30 ++++++++++++++++---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
> >  drivers/gpu/drm/i915/i915_drv.h               |  3 ++
> >  drivers/gpu/drm/i915/i915_reg.h               |  6 ++++
> >  5 files changed, 57 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index bcc6dc4e321b..cdd84a419cf7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -46,6 +46,7 @@
> >  #include "display/intel_ddi.h"
> >  #include "display/intel_dp.h"
> >  #include "display/intel_dp_mst.h"
> > +#include "display/intel_dpll_mgr.h"
> >  #include "display/intel_dsi.h"
> >  #include "display/intel_dvo.h"
> >  #include "display/intel_gmbus.h"
> > @@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
> >  	intel_pps_unlock_regs_wa(dev_priv);
> >  }
> >  
> > +static bool hti_uses_phy(u32 hdport_state, enum phy phy)
> > +{
> > +	return hdport_state & HDPORT_ENABLED &&
> > +		(hdport_state & HDPORT_PHY_USED_DP(phy) ||
> > +		 hdport_state & HDPORT_PHY_USED_HDMI(phy));
> > +}
> > +
> >  static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_encoder *encoder;
> > @@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> >  		return;
> >  
> >  	if (IS_ROCKETLAKE(dev_priv)) {
> > -		intel_ddi_init(dev_priv, PORT_A);
> > -		intel_ddi_init(dev_priv, PORT_B);
> > -		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> > -		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> > +		/*
> > +		 * If HTI (aka HDPORT) is enabled at boot, it may have taken
> > +		 * over some of the PHYs and made them unavailable to the
> > +		 * driver.  In that case we should skip initializing the
> > +		 * corresponding outputs.
> > +		 */
> > +		u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> > +
> > +		if (!hti_uses_phy(hdport_state, PHY_A))
> > +			intel_ddi_init(dev_priv, PORT_A);
> > +		if (!hti_uses_phy(hdport_state, PHY_B))
> > +			intel_ddi_init(dev_priv, PORT_B);
> > +		if (!hti_uses_phy(hdport_state, PHY_C))
> > +			intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
> > +		if (!hti_uses_phy(hdport_state, PHY_D))
> > +			intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> >  	} else if (INTEL_GEN(dev_priv) >= 12) {
> >  		intel_ddi_init(dev_priv, PORT_A);
> >  		intel_ddi_init(dev_priv, PORT_B);
> > @@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >  
> >  	intel_dpll_readout_hw_state(dev_priv);
> >  
> > +	dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
> > +
> >  	for_each_intel_encoder(dev, encoder) {
> >  		pipe = 0;
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index b5f4d4cef682..6f59f9ec453b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> >  	mutex_unlock(&dev_priv->dpll.lock);
> >  }
> >  
> > +/*
> > + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
> > + * unavailable for use.
> > + */
> > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
> > +{
> > +	u32 hdport_state;
> > +
> > +	if (!IS_ROCKETLAKE(dev_priv))
> > +		return 0;
> > +
> > +	hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> > +	if (!(hdport_state & HDPORT_ENABLED))
> > +		return 0;
> > +
> > +	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
> > +}
> > +
> >  static struct intel_shared_dpll *
> >  intel_find_shared_dpll(struct intel_atomic_state *state,
> >  		       const struct intel_crtc *crtc,
> > @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> >  
> >  	drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
> >  
> > +	/* Eliminate DPLLs from consideration if reserved by HTI */
> > +	dpll_mask &= ~dev_priv->hti_pll_mask;
> > +
> >  	for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
> >  		pll = &dev_priv->dpll.shared_dplls[i];
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 5d9a2bc371e7..ac2238646fe7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> >  void intel_shared_dpll_init(struct drm_device *dev);
> >  void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
> >  void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
> > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
> >  
> >  void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> >  			      const struct intel_dpll_hw_state *hw_state);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e99255e17eb7..668b3c9cf3ae 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1037,6 +1037,9 @@ struct drm_i915_private {
> >  
> >  	struct intel_l3_parity l3_parity;
> >  
> > +	/* Mask of PLLs reserved for use by HTI and unavailable to driver. */
> > +	u32 hti_pll_mask;
> > +
> >  	/*
> >  	 * edram size in MB.
> >  	 * Cannot be determined by PCIID. You must always read a register.
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 85137d268c4a..b9faf0f978cf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
> >  #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
> >  
> > +#define HDPORT_STATE			_MMIO(0x45050)
> > +#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
> > +#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*(phy) + 2)
> > +#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*(phy) + 1)
> > +#define   HDPORT_ENABLED		REG_BIT(0)
> > +
> >  /* Make render/texture TLB fetches lower priorty than associated data
> >   *   fetches. This is not turned on by default
> >   */
> > -- 
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2

[Matt Roper]

From: José Roberto de Souza <jose.souza@intel.com>

RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
tracking.  The driver is required to track the areas that needs update
and program hardware to send selective updates.

So until the software tracking is implemented, PSR2 needs to be disabled
for platforms without PSR2 HW tracking.

BSpec: 50422
BSpec: 50424

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          |  3 +++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 4 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b7a2c102648a..714c590b39f5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -646,6 +646,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	/*
+	 * Some platforms lack PSR2 HW tracking and instead require manual
+	 * tracking by software.  In this case, the driver is required to track
+	 * the areas that need updates and program hardware to send selective
+	 * updates.
+	 *
+	 * So until the software tracking is implemented, PSR2 needs to be
+	 * disabled for platforms without PSR2 HW tracking.
+	 */
+	if (!HAS_PSR_HW_TRACKING(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "No PSR2 HW tracking in the platform\n");
+		return false;
+	}
+
 	/*
 	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
 	 * resolution requires DSC to be enabled, priority is given to DSC
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 668b3c9cf3ae..87f4000413f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1644,6 +1644,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR_HW_TRACKING(dev_priv) \
+	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0ed586ee2047..ef4a457a6c4f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
 	.display.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.display.has_psr = 1, \
+	.display.has_psr_hw_tracking = 1, \
 	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	HSW_PIPE_OFFSETS, \
@@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_fbc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_psr = 1, \
+	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_csr = 1, \
 	.has_rc6 = 1, \
@@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = {
 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C),
 	.require_force_probe = 1,
+	.display.has_psr_hw_tracking = 0,
 	.engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 3613c04904e0..34dbffd65bad 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -148,6 +148,7 @@ enum intel_ppgtt_type {
 	func(has_modular_fia); \
 	func(has_overlay); \
 	func(has_psr); \
+	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
 
-- 
2.24.1

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Re: [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2

[Rodrigo Vivi]

On Wed, Jun 03, 2020 at 02:15:28PM -0700, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
> tracking.  The driver is required to track the areas that needs update
> and program hardware to send selective updates.
> 
> So until the software tracking is implemented, PSR2 needs to be disabled
> for platforms without PSR2 HW tracking.
> 
> BSpec: 50422
> BSpec: 50424
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h          |  2 ++
>  drivers/gpu/drm/i915/i915_pci.c          |  3 +++
>  drivers/gpu/drm/i915/intel_device_info.h |  1 +
>  4 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b7a2c102648a..714c590b39f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -646,6 +646,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	/*
> +	 * Some platforms lack PSR2 HW tracking and instead require manual
> +	 * tracking by software.  In this case, the driver is required to track
> +	 * the areas that need updates and program hardware to send selective
> +	 * updates.
> +	 *
> +	 * So until the software tracking is implemented, PSR2 needs to be
> +	 * disabled for platforms without PSR2 HW tracking.
> +	 */
> +	if (!HAS_PSR_HW_TRACKING(dev_priv)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "No PSR2 HW tracking in the platform\n");
> +		return false;
> +	}
> +
>  	/*
>  	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
>  	 * resolution requires DSC to be enabled, priority is given to DSC
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 668b3c9cf3ae..87f4000413f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1644,6 +1644,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PSR_HW_TRACKING(dev_priv) \
> +	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>  #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
>  
>  #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0ed586ee2047..ef4a457a6c4f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
>  	.display.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
>  	.display.has_psr = 1, \
> +	.display.has_psr_hw_tracking = 1, \
>  	.display.has_dp_mst = 1, \
>  	.has_rc6p = 0 /* RC6p removed-by HSW */, \
>  	HSW_PIPE_OFFSETS, \
> @@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = {
>  	.display.has_fbc = 1, \
>  	.display.has_hdcp = 1, \
>  	.display.has_psr = 1, \
> +	.display.has_psr_hw_tracking = 1, \
>  	.has_runtime_pm = 1, \
>  	.display.has_csr = 1, \
>  	.has_rc6 = 1, \
> @@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = {
>  	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>  		BIT(TRANSCODER_C),
>  	.require_force_probe = 1,
> +	.display.has_psr_hw_tracking = 0,
>  	.engine_mask =
>  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
>  };
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 3613c04904e0..34dbffd65bad 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -148,6 +148,7 @@ enum intel_ppgtt_type {
>  	func(has_modular_fia); \
>  	func(has_overlay); \
>  	func(has_psr); \
> +	func(has_psr_hw_tracking); \
>  	func(overlay_needs_physical); \
>  	func(supports_tv);
>  
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds

[Matt Roper]

RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c |  5 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
 2 files changed, 59 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 3cd461bf9131..63ac79f88fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 					enum plane_id plane_id)
 {
-	/* Wa_14010477008:tgl[a0..c0] */
-	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+	/* Wa_14010477008:tgl[a0..c0],rkl[all] */
+	if (IS_ROCKETLAKE(dev_priv) ||
+	    IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 30cd798b9664..d2f8e285491f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -590,8 +590,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 }
 
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
-				     struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+				       struct i915_wa_list *wal)
 {
 	/*
 	 * Wa_1409142259:tgl
@@ -601,12 +601,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 * Wa_1409207793:tgl
 	 * Wa_1409178076:tgl
 	 * Wa_1408979724:tgl
+	 * Wa_14010443199:rkl
+	 * Wa_14010698770:rkl
 	 */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 
+	/* WaDisableGPGPUMidThreadPreemption:gen12 */
+	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+
 	/*
-	 * Wa_1604555607:gen12 and Wa_1608008084:gen12
+	 * Wa_1604555607:tgl
+	 *
+	 * Note that the implementation of this workaround is further modified
+	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
 	 * FF_MODE2 register will return the wrong value when read. The default
 	 * value for this register is zero for all fields and there are no bit
 	 * masks. So instead of doing a RMW we should just write the TDS timer
@@ -614,11 +630,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 */
 	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 	       FF_MODE2_TDS_TIMER_128, 0);
-
-	/* WaDisableGPGPUMidThreadPreemption:tgl */
-	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
-			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
-			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 }
 
 static void
@@ -633,8 +644,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_GEN(i915, 12))
+	if (IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
+	else if (IS_GEN(i915, 12))
+		gen12_ctx_workarounds_init(engine, wal);
 	else if (IS_GEN(i915, 11))
 		icl_ctx_workarounds_init(engine, wal);
 	else if (IS_CANNONLAKE(i915))
@@ -946,9 +959,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 }
 
 static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+			  struct i915_wa_list *wal)
 {
 	wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
 	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -966,8 +986,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_GEN(i915, 12))
+	if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
+	else if (IS_GEN(i915, 12))
+		gen12_gt_workarounds_init(i915, wal);
 	else if (IS_GEN(i915, 11))
 		icl_gt_workarounds_init(i915, wal);
 	else if (IS_CANNONLAKE(i915))
@@ -1385,18 +1407,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 
-		/*
-		 * Wa_1607030317:tgl
-		 * Wa_1607186500:tgl
-		 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
-		 * of then says it is fixed on B0 the other one says it is
-		 * permanent
-		 */
-		wa_masked_en(wal,
-			     GEN6_RC_SLEEP_PSMI_CONTROL,
-			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
-
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
@@ -1415,24 +1425,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
-	if (IS_TIGERLAKE(i915)) {
-		/* Wa_1606931601:tgl */
+	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl,rkl */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
-		/* Wa_1409804808:tgl */
+		/* Wa_1409804808:tgl,rkl */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
-		/* Wa_1606700617:tgl */
-		wa_masked_en(wal,
-			     GEN9_CS_DEBUG_MODE1,
-			     FF_DOP_CLOCK_GATE_DISABLE);
-
 		/*
 		 * Wa_1409085225:tgl
-		 * Wa_14010229206:tgl
+		 * Wa_14010229206:tgl,rkl
 		 */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+
+		/*
+		 * Wa_1607030317:tgl
+		 * Wa_1607186500:tgl
+		 * Wa_1607297627:tgl,rkl there are multiple entries for this
+		 * WA in the BSpec; some indicate this is an A0-only WA,
+		 * others indicate it applies to all steppings.
+		 */
+		wa_masked_en(wal,
+			     GEN6_RC_SLEEP_PSMI_CONTROL,
+			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+	}
+
+	if (IS_TIGERLAKE(i915)) {
+		/* Wa_1606700617:tgl */
+		wa_masked_en(wal,
+			     GEN9_CS_DEBUG_MODE1,
+			     FF_DOP_CLOCK_GATE_DISABLE);
 	}
 
 	if (IS_GEN(i915, 11)) {
-- 
2.24.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining RKL patches

[Patchwork]

== Series Details ==

Series: Remaining RKL patches
URL   : https://patchwork.freedesktop.org/series/77971/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9433b10a50aa drm/i915/rkl: Set transcoder mask properly
-:22: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#22: FILE: drivers/gpu/drm/i915/i915_pci.c:884:
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

total: 0 errors, 1 warnings, 0 checks, 8 lines checked
d848bdb66774 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
-:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5266:
+		min_buddy = max_buddy = 0;

total: 0 errors, 0 warnings, 1 checks, 84 lines checked
ef03bae65599 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}
6c98fe20e57a drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
9f0cbd84fd69 drm/i915/rkl: Setup ports/phys
3ae91df36611 drm/i915/rkl: provide port/phy mapping for vbt
-:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#20: 
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]

total: 0 errors, 1 warnings, 0 checks, 104 lines checked
8795a1027509 drm/i915/rkl: Update TGP's pin mapping when paired with RKL
e05a981ee980 drm/i915/rkl: Add DDC pin mapping
729aaa26c152 drm/i915/rkl: Don't try to access transcoder D
8a112abfdc1c drm/i915/rkl: Don't try to read out DSI transcoders
307b9ecdbdbb drm/i915/rkl: Handle comp master/slave relationships for PHYs
f57c6c3d15ce drm/i915/rkl: Add DPLL4 support
20a10ff5d3a6 drm/i915/rkl: Handle HTI
-:156: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#156: FILE: drivers/gpu/drm/i915/i915_reg.h:2911:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*(phy) + 2)
                                  	         ^

-:157: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#157: FILE: drivers/gpu/drm/i915/i915_reg.h:2912:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*(phy) + 1)
                                    	         ^

total: 0 errors, 0 warnings, 2 checks, 115 lines checked
bfe78337ad8d drm/i915/rkl: Disable PSR2
c298c9e3576e drm/i915/rkl: Add initial workarounds

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remaining RKL patches

[Patchwork]

== Series Details ==

Series: Remaining RKL patches
URL   : https://patchwork.freedesktop.org/series/77971/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block

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[Intel-gfx] ✓ Fi.CI.BAT: success for Remaining RKL patches

[Patchwork]

== Series Details ==

Series: Remaining RKL patches
URL   : https://patchwork.freedesktop.org/series/77971/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17859
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html

Known issues
------------

  Here are the changes found in Patchwork_17859 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-byt-n2820:       [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-byt-n2820/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-n3050:       [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - fi-bsw-kefka:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * {igt@kms_flip@basic-flip-vs-wf_vblank@b-dvi-d1}:
    - fi-bwr-2160:        [FAIL][9] ([i915#1928]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank@b-dvi-d1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank@b-dvi-d1.html

  * {igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1}:
    - fi-icl-u2:          [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8579 -> Patchwork_17859

  CI-20190529: 20190529
  CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c298c9e3576e drm/i915/rkl: Add initial workarounds
bfe78337ad8d drm/i915/rkl: Disable PSR2
20a10ff5d3a6 drm/i915/rkl: Handle HTI
f57c6c3d15ce drm/i915/rkl: Add DPLL4 support
307b9ecdbdbb drm/i915/rkl: Handle comp master/slave relationships for PHYs
8a112abfdc1c drm/i915/rkl: Don't try to read out DSI transcoders
729aaa26c152 drm/i915/rkl: Don't try to access transcoder D
e05a981ee980 drm/i915/rkl: Add DDC pin mapping
8795a1027509 drm/i915/rkl: Update TGP's pin mapping when paired with RKL
3ae91df36611 drm/i915/rkl: provide port/phy mapping for vbt
9f0cbd84fd69 drm/i915/rkl: Setup ports/phys
6c98fe20e57a drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
ef03bae65599 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}
d848bdb66774 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
9433b10a50aa drm/i915/rkl: Set transcoder mask properly

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches

[Patchwork]

== Series Details ==

Series: Remaining RKL patches
URL   : https://patchwork.freedesktop.org/series/77971/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17859_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_isolation@preservation-s3@vcs0}:
    - shard-kbl:          [INCOMPLETE][1] ([i915#1780]) -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_17859_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-internal-10ms:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt@gem_eio@in-flight-internal-10ms.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@gem_eio@in-flight-internal-10ms.html

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt@gem_eio@in-flight-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl10/igt@gem_eio@in-flight-suspend.html

  * igt@gem_mmap_offset@clear:
    - shard-skl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +10 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt@gem_mmap_offset@clear.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl9/igt@gem_mmap_offset@clear.html

  * igt@i915_module_load@reload:
    - shard-tglb:         [PASS][9] -> [DMESG-WARN][10] ([i915#402])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt@i915_module_load@reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb2/igt@i915_module_load@reload.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt@i915_suspend@forcewake.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl4/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-c-cursor-size-change:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#54])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-size-change.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-size-change.html

  * igt@kms_cursor_legacy@all-pipes-torture-move:
    - shard-iclb:         [PASS][17] -> [DMESG-WARN][18] ([i915#128])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt@kms_cursor_legacy@all-pipes-torture-move.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb6/igt@kms_cursor_legacy@all-pipes-torture-move.html
    - shard-tglb:         [PASS][19] -> [DMESG-WARN][20] ([i915#128])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt@kms_cursor_legacy@all-pipes-torture-move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb6/igt@kms_cursor_legacy@all-pipes-torture-move.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-glk:          [PASS][21] -> [DMESG-FAIL][22] ([i915#1925] / [i915#1926])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_flip_tiling@flip-yf-tiled:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_flip_tiling@flip-yf-tiled.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_flip_tiling@flip-yf-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - shard-glk:          [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt@kms_frontbuffer_tracking@fbc-badstride.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt@kms_frontbuffer_tracking@fbc-badstride.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#49])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#53])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([i915#173])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt@kms_psr@no_drrs.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][37] -> [FAIL][38] ([i915#31])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_setmode@basic.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-wait-busy:
    - shard-tglb:         [PASS][39] -> [DMESG-WARN][40] ([i915#1982])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt@kms_vblank@pipe-c-wait-busy.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt@kms_vblank@pipe-c-wait-busy.html

  * igt@syncobj_wait@single-wait-all-signaled:
    - shard-kbl:          [PASS][41] -> [DMESG-WARN][42] ([i915#93] / [i915#95]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt@syncobj_wait@single-wait-all-signaled.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl3/igt@syncobj_wait@single-wait-all-signaled.html

  
#### Possible fixes ####

  * {igt@gem_exec_reloc@basic-concurrent0}:
    - shard-glk:          [FAIL][43] ([i915#1930]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt@gem_exec_reloc@basic-concurrent0.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html
    - shard-apl:          [FAIL][45] ([i915#1930]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@gem_exec_reloc@basic-concurrent0.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt@gem_exec_reloc@basic-concurrent0.html

  * {igt@gem_exec_schedule@implicit-write-read@rcs0}:
    - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt@gem_exec_schedule@implicit-write-read@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-snb6/igt@gem_exec_schedule@implicit-write-read@rcs0.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-apl:          [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
    - shard-tglb:         [DMESG-WARN][53] ([i915#402]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html

  * {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
    - shard-skl:          [FAIL][55] ([i915#46]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * {igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1}:
    - shard-kbl:          [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-kbl:          [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
    - shard-tglb:         [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-skl:          [INCOMPLETE][63] ([i915#69]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane@plane-panning-top-left-pipe-c-planes:
    - shard-skl:          [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +10 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid:
    - shard-apl:          [DMESG-WARN][67] ([i915#95]) -> [PASS][68] +11 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html

  * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
    - shard-iclb:         [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb8/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * {igt@perf@blocking-parameterized}:
    - shard-tglb:         [FAIL][73] ([i915#1542]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt@perf@blocking-parameterized.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt@perf@blocking-parameterized.html

  * igt@perf_pmu@rc6-runtime-pm:
    - shard-glk:          [TIMEOUT][75] ([i915#1958]) -> [PASS][76] +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt@perf_pmu@rc6-runtime-pm.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt@perf_pmu@rc6-runtime-pm.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-kbl:          [TIMEOUT][77] ([i915#1319]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt@kms_content_protection@atomic.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl7/igt@kms_content_protection@atomic.html
    - shard-apl:          [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_content_protection@atomic.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [TIMEOUT][81] ([i915#1319]) -> [FAIL][82] ([fdo#110321] / [fdo#110336])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt@kms_content_protection@atomic-dpms.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@lic:
    - shard-apl:          [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_content_protection@lic.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@srm:
    - shard-apl:          [FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@kms_content_protection@srm.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-apl:          [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_vblank@pipe-d-query-idle-hang:
    - shard-glk:          [TIMEOUT][89] ([i915#1640] / [i915#1958]) -> [SKIP][90] ([fdo#109271])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt@kms_vblank@pipe-d-query-idle-hang.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt@kms_vblank@pipe-d-query-idle-hang.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640
  [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
  [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925
  [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926
  [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_8579 -> Patchwork_17859

  CI-20190529: 20190529
  CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches

[Matt Roper]

On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Remaining RKL patches
> URL   : https://patchwork.freedesktop.org/series/77971/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.

Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's.


Matt

> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_17859_full:
> 
> ### IGT changes ###
> 
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@gem_ctx_isolation@preservation-s3@vcs0}:
>     - shard-kbl:          [INCOMPLETE][1] ([i915#1780]) -> [INCOMPLETE][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_17859_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_eio@in-flight-internal-10ms:
>     - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +8 similar issues
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt@gem_eio@in-flight-internal-10ms.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@gem_eio@in-flight-internal-10ms.html
> 
>   * igt@gem_eio@in-flight-suspend:
>     - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt@gem_eio@in-flight-suspend.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl10/igt@gem_eio@in-flight-suspend.html
> 
>   * igt@gem_mmap_offset@clear:
>     - shard-skl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +10 similar issues
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt@gem_mmap_offset@clear.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl9/igt@gem_mmap_offset@clear.html
> 
>   * igt@i915_module_load@reload:
>     - shard-tglb:         [PASS][9] -> [DMESG-WARN][10] ([i915#402])
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt@i915_module_load@reload.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb2/igt@i915_module_load@reload.html
> 
>   * igt@i915_suspend@fence-restore-tiled2untiled:
>     - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
> 
>   * igt@i915_suspend@forcewake:
>     - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt@i915_suspend@forcewake.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl4/igt@i915_suspend@forcewake.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-size-change:
>     - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#54])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-size-change.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-size-change.html
> 
>   * igt@kms_cursor_legacy@all-pipes-torture-move:
>     - shard-iclb:         [PASS][17] -> [DMESG-WARN][18] ([i915#128])
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt@kms_cursor_legacy@all-pipes-torture-move.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb6/igt@kms_cursor_legacy@all-pipes-torture-move.html
>     - shard-tglb:         [PASS][19] -> [DMESG-WARN][20] ([i915#128])
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt@kms_cursor_legacy@all-pipes-torture-move.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb6/igt@kms_cursor_legacy@all-pipes-torture-move.html
> 
>   * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
>     - shard-glk:          [PASS][21] -> [DMESG-FAIL][22] ([i915#1925] / [i915#1926])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
> 
>   * igt@kms_flip_tiling@flip-yf-tiled:
>     - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145])
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_flip_tiling@flip-yf-tiled.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_flip_tiling@flip-yf-tiled.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-badstride:
>     - shard-glk:          [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt@kms_frontbuffer_tracking@fbc-badstride.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt@kms_frontbuffer_tracking@fbc-badstride.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
>     - shard-iclb:         [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
>     - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#49])
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
> 
>   * igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
>     - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#53])
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
>     - shard-skl:          [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265])
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> 
>   * igt@kms_psr@no_drrs:
>     - shard-iclb:         [PASS][35] -> [FAIL][36] ([i915#173])
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt@kms_psr@no_drrs.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb1/igt@kms_psr@no_drrs.html
> 
>   * igt@kms_setmode@basic:
>     - shard-apl:          [PASS][37] -> [FAIL][38] ([i915#31])
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_setmode@basic.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt@kms_setmode@basic.html
> 
>   * igt@kms_vblank@pipe-c-wait-busy:
>     - shard-tglb:         [PASS][39] -> [DMESG-WARN][40] ([i915#1982])
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt@kms_vblank@pipe-c-wait-busy.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt@kms_vblank@pipe-c-wait-busy.html
> 
>   * igt@syncobj_wait@single-wait-all-signaled:
>     - shard-kbl:          [PASS][41] -> [DMESG-WARN][42] ([i915#93] / [i915#95]) +1 similar issue
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt@syncobj_wait@single-wait-all-signaled.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl3/igt@syncobj_wait@single-wait-all-signaled.html
> 
>   
> #### Possible fixes ####
> 
>   * {igt@gem_exec_reloc@basic-concurrent0}:
>     - shard-glk:          [FAIL][43] ([i915#1930]) -> [PASS][44]
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt@gem_exec_reloc@basic-concurrent0.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html
>     - shard-apl:          [FAIL][45] ([i915#1930]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@gem_exec_reloc@basic-concurrent0.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt@gem_exec_reloc@basic-concurrent0.html
> 
>   * {igt@gem_exec_schedule@implicit-write-read@rcs0}:
>     - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt@gem_exec_schedule@implicit-write-read@rcs0.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-snb6/igt@gem_exec_schedule@implicit-write-read@rcs0.html
> 
>   * igt@gem_workarounds@suspend-resume-context:
>     - shard-apl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +2 similar issues
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
> 
>   * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
>     - shard-apl:          [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
>     - shard-tglb:         [DMESG-WARN][53] ([i915#402]) -> [PASS][54]
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
> 
>   * {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
>     - shard-skl:          [FAIL][55] ([i915#46]) -> [PASS][56]
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
> 
>   * {igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1}:
>     - shard-kbl:          [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
>     - shard-kbl:          [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60]
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
>     - shard-tglb:         [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
>     - shard-skl:          [INCOMPLETE][63] ([i915#69]) -> [PASS][64]
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
> 
>   * igt@kms_plane@plane-panning-top-left-pipe-c-planes:
>     - shard-skl:          [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +10 similar issues
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid:
>     - shard-apl:          [DMESG-WARN][67] ([i915#95]) -> [PASS][68] +11 similar issues
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html
> 
>   * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
>     - shard-iclb:         [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +1 similar issue
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb8/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
> 
>   * igt@kms_vblank@pipe-a-ts-continuation-suspend:
>     - shard-kbl:          [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +4 similar issues
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> 
>   * {igt@perf@blocking-parameterized}:
>     - shard-tglb:         [FAIL][73] ([i915#1542]) -> [PASS][74]
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt@perf@blocking-parameterized.html
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt@perf@blocking-parameterized.html
> 
>   * igt@perf_pmu@rc6-runtime-pm:
>     - shard-glk:          [TIMEOUT][75] ([i915#1958]) -> [PASS][76] +3 similar issues
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt@perf_pmu@rc6-runtime-pm.html
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt@perf_pmu@rc6-runtime-pm.html
> 
>   
> #### Warnings ####
> 
>   * igt@kms_content_protection@atomic:
>     - shard-kbl:          [TIMEOUT][77] ([i915#1319]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95])
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt@kms_content_protection@atomic.html
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl7/igt@kms_content_protection@atomic.html
>     - shard-apl:          [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95])
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_content_protection@atomic.html
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@kms_content_protection@atomic.html
> 
>   * igt@kms_content_protection@atomic-dpms:
>     - shard-apl:          [TIMEOUT][81] ([i915#1319]) -> [FAIL][82] ([fdo#110321] / [fdo#110336])
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt@kms_content_protection@atomic-dpms.html
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt@kms_content_protection@atomic-dpms.html
> 
>   * igt@kms_content_protection@lic:
>     - shard-apl:          [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319])
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt@kms_content_protection@lic.html
>    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt@kms_content_protection@lic.html
> 
>   * igt@kms_content_protection@srm:
>     - shard-apl:          [FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319])
>    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@kms_content_protection@srm.html
>    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@kms_content_protection@srm.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
>     - shard-apl:          [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49])
>    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
>    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
> 
>   * igt@kms_vblank@pipe-d-query-idle-hang:
>     - shard-glk:          [TIMEOUT][89] ([i915#1640] / [i915#1958]) -> [SKIP][90] ([fdo#109271])
>    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt@kms_vblank@pipe-d-query-idle-hang.html
>    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt@kms_vblank@pipe-d-query-idle-hang.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
>   [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
>   [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
>   [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
>   [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
>   [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
>   [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640
>   [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
>   [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925
>   [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926
>   [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
>   [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
>   [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
>   [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
>   [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
>   [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
>   [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
>   [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
>   [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
>   [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>   [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
>   [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
>   [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> 
> 
> Participating hosts (11 -> 11)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_8579 -> Patchwork_17859
> 
>   CI-20190529: 20190529
>   CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches

[Chris Wilson]

Quoting Matt Roper (2020-06-04 17:39:16)
> On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: Remaining RKL patches
> > URL   : https://patchwork.freedesktop.org/series/77971/
> > State : success
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full
> > ====================================================
> > 
> > Summary
> > -------
> > 
> >   **SUCCESS**
> > 
> >   No regressions found.
> 
> Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's.

This seems to have introduced
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt@runner@aborted.html

<4>[    3.422515] i915 0000:00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
<4>[    3.422528] WARNING: CPU: 4 PID: 372 at drivers/gpu/drm/drm_vblank.c:719 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370
<4>[    3.422529] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel snd_intel_dspcfg crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep snd_hda_core ghash_clmulni_intel snd_pcm mei_me e1000e mei ptp prime_numbers pps_core
<4>[    3.422540] CPU: 4 PID: 372 Comm: systemd-udevd Tainted: G     U            5.7.0-CI-CI_DRM_8584+ #1
<4>[    3.422542] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 3402 04/26/2017
<4>[    3.422544] RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370
<4>[    3.422547] Code: 8b 5f 50 48 85 db 0f 84 e8 00 00 00 e8 65 62 01 00 48 c7 c1 08 90 35 82 48 89 da 48 89 c6 48 c7 c7 c8 95 35 82 e8 ec d6 9c ff <0f> 0b 45 31 d2 e9 32 ff ff ff 48 8b 7b 18 8b 4d 9c 48 c7 c2 40 90
<4>[    3.422548] RSP: 0018:ffffc9000050b808 EFLAGS: 00010082
<4>[    3.422550] RAX: 0000000000000000 RBX: ffff88822ba975a0 RCX: 0000000000000003
<4>[    3.422552] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffffffff82383f0a
<4>[    3.422554] RBP: ffffc9000050b878 R08: 0000000000000000 R09: 0000000000000001
<4>[    3.422555] R10: 0000000000000000 R11: 00000000e5a843ae R12: ffff8882193eb800
<4>[    3.422557] R13: ffffc9000050b8c8 R14: 0000000000000000 R15: ffff88820c1fd350
<4>[    3.422559] FS:  00007f3e6ef07680(0000) GS:ffff88822ec00000(0000) knlGS:0000000000000000
<4>[    3.422561] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[    3.422562] CR2: 00007f91492aa290 CR3: 000000022368a004 CR4: 00000000003606e0
<4>[    3.422564] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
<4>[    3.422565] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
<4>[    3.422567] Call Trace:
<4>[    3.422604]  ? fwtable_read32+0x83/0x310 [i915]
<4>[    3.422611]  drm_get_last_vbltimestamp+0xb2/0xc0
<4>[    3.422616]  drm_reset_vblank_timestamp+0x54/0xc0
<4>[    3.422621]  drm_crtc_vblank_on+0x83/0x140
<4>[    3.422670]  intel_modeset_setup_hw_state+0x8f7/0x16c0 [i915]
<4>[    3.422676]  ? drm_modeset_lock+0xad/0x120
<4>[    3.422727]  intel_modeset_init+0x582/0x1c50 [i915]
<4>[    3.422731]  ? _raw_spin_unlock_irqrestore+0x34/0x60
<4>[    3.422764]  ? intel_irq_postinstall+0x284/0x610 [i915]
<4>[    3.422799]  i915_driver_probe+0x778/0xf90 [i915]
<4>[    3.422805]  ? __pm_runtime_resume+0x4f/0x80
<4>[    3.422840]  i915_pci_probe+0x3b/0x1d0 [i915]
<4>[    3.422843]  ? _raw_spin_unlock_irqrestore+0x34/0x60
<4>[    3.422849]  pci_device_probe+0x9e/0x120
<4>[    3.422853]  really_probe+0xea/0x430
<4>[    3.422858]  driver_probe_device+0x10b/0x120
<4>[    3.422861]  device_driver_attach+0x4a/0x50
<4>[    3.422865]  __driver_attach+0x97/0x130
<4>[    3.422868]  ? device_driver_attach+0x50/0x50
<4>[    3.422871]  bus_for_each_dev+0x74/0xc0
<4>[    3.422875]  bus_add_driver+0x142/0x220
<4>[    3.422879]  driver_register+0x56/0xf0
<4>[    3.422913]  i915_init+0x6c/0x7c [i915]
<4>[    3.422916]  ? 0xffffffffa08c9000
<4>[    3.422918]  do_one_initcall+0x58/0x300
<4>[    3.422921]  ? do_init_module+0x1d/0x1f2
<4>[    3.422924]  ? rcu_read_lock_sched_held+0x4d/0x80
<4>[    3.422928]  ? kmem_cache_alloc_trace+0x2a6/0x2d0
<4>[    3.422933]  do_init_module+0x56/0x1f2
<4>[    3.422936]  load_module+0x2339/0x2a20
<4>[    3.422953]  ? __do_sys_finit_module+0xe9/0x110
<4>[    3.422955]  __do_sys_finit_module+0xe9/0x110
<4>[    3.422966]  do_syscall_64+0x4f/0x220
<4>[    3.422969]  entry_SYSCALL_64_after_hwframe+0x49/0xb3
<4>[    3.422971] RIP: 0033:0x7f3e6ea28839
<4>[    3.422973] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
<4>[    3.422975] RSP: 002b:00007ffebbc0c118 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
<4>[    3.422977] RAX: ffffffffffffffda RBX: 0000557f8afde730 RCX: 00007f3e6ea28839
<4>[    3.422979] RDX: 0000000000000000 RSI: 0000557f8afd62c0 RDI: 000000000000000f
<4>[    3.422980] RBP: 0000557f8afd62c0 R08: 0000000000000000 R09: 00007ffebbc0c230
<4>[    3.422982] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
<4>[    3.422984] R13: 0000557f8afb99e0 R14: 0000000000020000 R15: 0000000000000000
<4>[    3.422993] irq event stamp: 603166
<4>[    3.422996] hardirqs last  enabled at (603165): [<ffffffff81a4dfd7>] _raw_spin_unlock_irqrestore+0x47/0x60
<4>[    3.422998] hardirqs last disabled at (603166): [<ffffffff81a4dd5d>] _raw_spin_lock_irqsave+0xd/0x50
<4>[    3.423000] softirqs last  enabled at (603132): [<ffffffff81e00395>] __do_softirq+0x395/0x
-Chris
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches

[Matt Roper]

On Fri, Jun 05, 2020 at 11:11:23PM +0100, Chris Wilson wrote:
> Quoting Matt Roper (2020-06-04 17:39:16)
> > On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote:
> > > == Series Details ==
> > > 
> > > Series: Remaining RKL patches
> > > URL   : https://patchwork.freedesktop.org/series/77971/
> > > State : success
> > > 
> > > == Summary ==
> > > 
> > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full
> > > ====================================================
> > > 
> > > Summary
> > > -------
> > > 
> > >   **SUCCESS**
> > > 
> > >   No regressions found.
> > 
> > Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's.
> 
> This seems to have introduced
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt@runner@aborted.html

Thanks for pointing that out.  I think it's because we lost DP-E
matching in the VBT mapping table during the refactor.  If so,

        https://patchwork.freedesktop.org/patch/368948/?series=78060&rev=1

should fix it.  Was there a gitlab bug for this failure?


Matt

> 
> <4>[    3.422515] i915 0000:00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
> <4>[    3.422528] WARNING: CPU: 4 PID: 372 at drivers/gpu/drm/drm_vblank.c:719 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370
> <4>[    3.422529] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel snd_intel_dspcfg crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep snd_hda_core ghash_clmulni_intel snd_pcm mei_me e1000e mei ptp prime_numbers pps_core
> <4>[    3.422540] CPU: 4 PID: 372 Comm: systemd-udevd Tainted: G     U            5.7.0-CI-CI_DRM_8584+ #1
> <4>[    3.422542] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 3402 04/26/2017
> <4>[    3.422544] RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370
> <4>[    3.422547] Code: 8b 5f 50 48 85 db 0f 84 e8 00 00 00 e8 65 62 01 00 48 c7 c1 08 90 35 82 48 89 da 48 89 c6 48 c7 c7 c8 95 35 82 e8 ec d6 9c ff <0f> 0b 45 31 d2 e9 32 ff ff ff 48 8b 7b 18 8b 4d 9c 48 c7 c2 40 90
> <4>[    3.422548] RSP: 0018:ffffc9000050b808 EFLAGS: 00010082
> <4>[    3.422550] RAX: 0000000000000000 RBX: ffff88822ba975a0 RCX: 0000000000000003
> <4>[    3.422552] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffffffff82383f0a
> <4>[    3.422554] RBP: ffffc9000050b878 R08: 0000000000000000 R09: 0000000000000001
> <4>[    3.422555] R10: 0000000000000000 R11: 00000000e5a843ae R12: ffff8882193eb800
> <4>[    3.422557] R13: ffffc9000050b8c8 R14: 0000000000000000 R15: ffff88820c1fd350
> <4>[    3.422559] FS:  00007f3e6ef07680(0000) GS:ffff88822ec00000(0000) knlGS:0000000000000000
> <4>[    3.422561] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[    3.422562] CR2: 00007f91492aa290 CR3: 000000022368a004 CR4: 00000000003606e0
> <4>[    3.422564] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> <4>[    3.422565] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> <4>[    3.422567] Call Trace:
> <4>[    3.422604]  ? fwtable_read32+0x83/0x310 [i915]
> <4>[    3.422611]  drm_get_last_vbltimestamp+0xb2/0xc0
> <4>[    3.422616]  drm_reset_vblank_timestamp+0x54/0xc0
> <4>[    3.422621]  drm_crtc_vblank_on+0x83/0x140
> <4>[    3.422670]  intel_modeset_setup_hw_state+0x8f7/0x16c0 [i915]
> <4>[    3.422676]  ? drm_modeset_lock+0xad/0x120
> <4>[    3.422727]  intel_modeset_init+0x582/0x1c50 [i915]
> <4>[    3.422731]  ? _raw_spin_unlock_irqrestore+0x34/0x60
> <4>[    3.422764]  ? intel_irq_postinstall+0x284/0x610 [i915]
> <4>[    3.422799]  i915_driver_probe+0x778/0xf90 [i915]
> <4>[    3.422805]  ? __pm_runtime_resume+0x4f/0x80
> <4>[    3.422840]  i915_pci_probe+0x3b/0x1d0 [i915]
> <4>[    3.422843]  ? _raw_spin_unlock_irqrestore+0x34/0x60
> <4>[    3.422849]  pci_device_probe+0x9e/0x120
> <4>[    3.422853]  really_probe+0xea/0x430
> <4>[    3.422858]  driver_probe_device+0x10b/0x120
> <4>[    3.422861]  device_driver_attach+0x4a/0x50
> <4>[    3.422865]  __driver_attach+0x97/0x130
> <4>[    3.422868]  ? device_driver_attach+0x50/0x50
> <4>[    3.422871]  bus_for_each_dev+0x74/0xc0
> <4>[    3.422875]  bus_add_driver+0x142/0x220
> <4>[    3.422879]  driver_register+0x56/0xf0
> <4>[    3.422913]  i915_init+0x6c/0x7c [i915]
> <4>[    3.422916]  ? 0xffffffffa08c9000
> <4>[    3.422918]  do_one_initcall+0x58/0x300
> <4>[    3.422921]  ? do_init_module+0x1d/0x1f2
> <4>[    3.422924]  ? rcu_read_lock_sched_held+0x4d/0x80
> <4>[    3.422928]  ? kmem_cache_alloc_trace+0x2a6/0x2d0
> <4>[    3.422933]  do_init_module+0x56/0x1f2
> <4>[    3.422936]  load_module+0x2339/0x2a20
> <4>[    3.422953]  ? __do_sys_finit_module+0xe9/0x110
> <4>[    3.422955]  __do_sys_finit_module+0xe9/0x110
> <4>[    3.422966]  do_syscall_64+0x4f/0x220
> <4>[    3.422969]  entry_SYSCALL_64_after_hwframe+0x49/0xb3
> <4>[    3.422971] RIP: 0033:0x7f3e6ea28839
> <4>[    3.422973] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
> <4>[    3.422975] RSP: 002b:00007ffebbc0c118 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
> <4>[    3.422977] RAX: ffffffffffffffda RBX: 0000557f8afde730 RCX: 00007f3e6ea28839
> <4>[    3.422979] RDX: 0000000000000000 RSI: 0000557f8afd62c0 RDI: 000000000000000f
> <4>[    3.422980] RBP: 0000557f8afd62c0 R08: 0000000000000000 R09: 00007ffebbc0c230
> <4>[    3.422982] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
> <4>[    3.422984] R13: 0000557f8afb99e0 R14: 0000000000020000 R15: 0000000000000000
> <4>[    3.422993] irq event stamp: 603166
> <4>[    3.422996] hardirqs last  enabled at (603165): [<ffffffff81a4dfd7>] _raw_spin_unlock_irqrestore+0x47/0x60
> <4>[    3.422998] hardirqs last disabled at (603166): [<ffffffff81a4dd5d>] _raw_spin_lock_irqsave+0xd/0x50
> <4>[    3.423000] softirqs last  enabled at (603132): [<ffffffff81e00395>] __do_softirq+0x395/0x
> -Chris

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches

[Chris Wilson]

Quoting Matt Roper (2020-06-06 04:21:37)
> On Fri, Jun 05, 2020 at 11:11:23PM +0100, Chris Wilson wrote:
> > Quoting Matt Roper (2020-06-04 17:39:16)
> > > On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote:
> > > > == Series Details ==
> > > > 
> > > > Series: Remaining RKL patches
> > > > URL   : https://patchwork.freedesktop.org/series/77971/
> > > > State : success
> > > > 
> > > > == Summary ==
> > > > 
> > > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full
> > > > ====================================================
> > > > 
> > > > Summary
> > > > -------
> > > > 
> > > >   **SUCCESS**
> > > > 
> > > >   No regressions found.
> > > 
> > > Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's.
> > 
> > This seems to have introduced
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt@runner@aborted.html
> 
> Thanks for pointing that out.  I think it's because we lost DP-E
> matching in the VBT mapping table during the refactor.  If so,
> 
>         https://patchwork.freedesktop.org/patch/368948/?series=78060&rev=1
> 
> should fix it.

It did indeed.

> Was there a gitlab bug for this failure?

Not yet.
-Chris
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