* [PULL v2 00/32] riscv-to-apply queue
@ 2020-06-19 16:57 Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
` (33 more replies)
0 siblings, 34 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit 4d285821c5055ed68a6f6b7693fd11a06a1aa426:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into staging (2020-06-19 11:44:03 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200619-3
for you to fetch changes up to 3eaea6eb4e534f7b87c6eca808149bb671976800:
hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-19 08:25:27 -0700)
----------------------------------------------------------------
This is a range of patches for RISC-V.
Some key points are:
- Generalise the CPU init functions
- Support the SiFive revB machine
- Improvements to the Hypervisor implementation and error checking
- Connect some OpenTitan devices
- Changes to the sifive_u machine to support U-boot
v2:
- Fix missing realise assert
----------------------------------------------------------------
Alistair Francis (11):
sifive_e: Support the revB machine
target/riscv: Set access as data_load when validating stage-2 PTEs
target/riscv: Report errors validating 2nd-stage PTEs
target/riscv: Move the hfence instructions to the rvh decode
target/riscv: Implement checks for hfence
riscv/opentitan: Fix the ROM size
hw/char: Initial commit of Ibex UART
hw/intc: Initial commit of lowRISC Ibex PLIC
riscv/opentitan: Connect the PLIC device
riscv/opentitan: Connect the UART device
target/riscv: Use a smaller guess size for no-MMU PMP
Bin Meng (20):
riscv: Generalize CPU init routine for the base CPU
riscv: Generalize CPU init routine for the gcsu CPU
riscv: Generalize CPU init routine for the imacu CPU
riscv: Keep the CPU init routine names consistent
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
hw/riscv: sifive_u: Generate device tree node for OTP
hw/riscv: sifive_gpio: Clean up the codes
hw/riscv: sifive_gpio: Add a new 'ngpio' property
hw/riscv: sifive_u: Hook a GPIO controller
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
hw/riscv: sifive_u: Add reset functionality
hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
target/riscv: Rename IBEX CPU init routine
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
hw/riscv: sifive_u: Support different boot source per MSEL pin state
hw/riscv: sifive_u: Sort the SoC memmap table entries
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Ian Jiang (1):
riscv: Add helper to make NaN-boxing for FP register
include/hw/char/ibex_uart.h | 110 ++++++
include/hw/intc/ibex_plic.h | 63 ++++
include/hw/riscv/opentitan.h | 16 +
include/hw/riscv/sifive_e.h | 1 +
include/hw/riscv/sifive_gpio.h | 8 +-
include/hw/riscv/sifive_u.h | 27 ++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 8 +-
hw/char/ibex_uart.c | 492 +++++++++++++++++++++++++
hw/intc/ibex_plic.c | 261 +++++++++++++
hw/riscv/opentitan.c | 71 +++-
hw/riscv/sifive_e.c | 60 ++-
hw/riscv/sifive_gpio.c | 45 ++-
hw/riscv/sifive_u.c | 157 ++++++--
target/riscv/cpu.c | 69 ++--
target/riscv/cpu_helper.c | 9 +-
target/riscv/insn_trans/trans_privileged.inc.c | 38 --
target/riscv/insn_trans/trans_rvf.inc.c | 17 +-
target/riscv/insn_trans/trans_rvh.inc.c | 37 ++
target/riscv/op_helper.c | 13 +
target/riscv/pmp.c | 14 +-
target/riscv/translate.c | 1 +
MAINTAINERS | 4 +
hw/char/Makefile.objs | 1 +
hw/intc/Makefile.objs | 1 +
hw/riscv/Kconfig | 4 +
26 files changed, 1350 insertions(+), 182 deletions(-)
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 hw/char/ibex_uart.c
create mode 100644 hw/intc/ibex_plic.c
create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 02/32] sifive_e: Support the revB machine Alistair Francis
` (32 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Ian Jiang
From: Ian Jiang <ianjiang.ict@gmail.com>
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Message-Id: <20200128003707.17028-1-ianjiang.ict@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index e23cd639a6..3bfd8881e7 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -23,6 +23,20 @@
return false; \
} while (0)
+/*
+ * RISC-V requires NaN-boxing of narrower width floating
+ * point values. This applies when a 32-bit value is
+ * assigned to a 64-bit FP register. Thus this does not
+ * apply when the RVD extension is not present.
+ */
+static void gen_nanbox_fpr(DisasContext *ctx, int regno)
+{
+ if (has_ext(ctx, RVD)) {
+ tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
+ MAKE_64BIT_MASK(32, 32));
+ }
+}
+
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv t0 = tcg_temp_new();
@@ -32,8 +46,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
+ gen_nanbox_fpr(ctx, a->rd);
tcg_temp_free(t0);
mark_fs_dirty(ctx);
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 02/32] sifive_e: Support the revB machine
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
` (31 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_e.h | 1 +
hw/riscv/sifive_e.c | 34 ++++++++++++++++++++++++++++++----
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d386ea9223..637414130b 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
/*< public >*/
SiFiveESoCState soc;
+ bool revb;
} SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1c17d02cf0..36486b72d2 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -95,10 +95,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -112,8 +116,30 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board");
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
2020-06-19 16:57 ` [PULL v2 02/32] sifive_e: Support the revB machine Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-23 6:22 ` Bin Meng
2020-06-19 16:57 ` [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
` (30 subsequent siblings)
33 siblings, 1 reply; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have exactly the same
codes for 32-bit and 64-bit base CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3a6d202d03..81cdea8680 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void riscv_base32_cpu_init(Object *obj)
+static void riscv_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
@@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
-static void riscv_base64_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- set_misa(env, 0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -603,13 +595,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
` (29 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit gcsu CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81cdea8680..437e141ef2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
+static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
-static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
static void rv64imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -599,11 +591,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_gcsu_priv1_10_0_cpu_init),
#endif
};
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
` (28 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit imacu CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 437e141ef2..35a8c7853b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -142,23 +142,23 @@ static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void rv32imcu_nommu_cpu_init(Object *obj)
+static void rvxx_imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, 0x8090);
+ set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-static void rv32imacu_nommu_cpu_init(Object *obj)
+#if defined(TARGET_RISCV32)
+
+static void rv32imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+ set_misa(env, RV32 | RVI | RVM | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x8090);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-#elif defined(TARGET_RISCV64)
-
-static void rv64imacu_nommu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
- qdev_prop_set_bit(DEVICE(obj), "mmu", false);
-}
-
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -589,12 +578,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_gcsu_priv1_10_0_cpu_init),
#endif
};
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 06/32] riscv: Keep the CPU init routine names consistent
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
` (27 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Adding a _ to keep some consistency among the CPU init routines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 35a8c7853b..e867766cf0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj)
#if defined(TARGET_RISCV32)
-static void rv32imcu_nommu_cpu_init(Object *obj)
+static void rv32_imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
@@ -162,7 +162,7 @@ static void rv32imcu_nommu_cpu_init(Object *obj)
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-static void rv32imafcu_nommu_cpu_init(Object *obj)
+static void rv32_imafcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
@@ -577,9 +577,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
` (26 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Richard Henderson, Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fe1ecc8f..eda7057663 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,7 +435,7 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
` (25 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Richard Henderson, Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index eda7057663..75d2ae3434 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,8 +435,13 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
- mmu_idx, false, true);
+ int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
+ base, MMU_DATA_LOAD,
+ mmu_idx, false, true);
+
+ if (vbase_ret != TRANSLATE_SUCCESS) {
+ return vbase_ret;
+ }
pte_addr = vbase + idx * ptesize;
} else {
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 10/32] target/riscv: Implement checks for hfence Alistair Francis
` (24 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Richard Henderson, Alistair Francis
Also correct the name of the VVMA instruction.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 8 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 38 -------------
target/riscv/insn_trans/trans_rvh.inc.c | 57 +++++++++++++++++++
target/riscv/translate.c | 1 +
4 files changed, 63 insertions(+), 41 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b883672e63..4c8d1215ce 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -64,7 +64,7 @@
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
-@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@@ -77,8 +77,6 @@ uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
-hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
-hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
@@ -207,3 +205,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32H Base Instruction Set ***
+hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
+hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index 5f26e0f5ea..2a61a853bf 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -95,41 +95,3 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
{
return false;
}
-
-static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
- if (has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
-#endif
- return false;
-}
-
-static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
- if (has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
-#endif
- return false;
-}
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
new file mode 100644
index 0000000000..2c0359819d
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -0,0 +1,57 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
+
+static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 43bf7e39a6..ce71ca7a92 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_rvh.inc.c"
#include "insn_trans/trans_privileged.inc.c"
/* Include the auto-generated decoder for 16 bit insn */
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 10/32] target/riscv: Implement checks for hfence
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
` (23 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Richard Henderson, Alistair Francis
Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 5 ++++
target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++--------------------
target/riscv/op_helper.c | 13 ++++++++++
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a480..b36be978d5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
+
+/* Hypervisor functions */
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(hyp_tlb_flush, void, env)
+#endif
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index 2c0359819d..263b652d90 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -18,40 +18,20 @@
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
+ REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
{
+ REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b0c49efc4a..7cccd42a1e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -194,4 +194,17 @@ void helper_tlb_flush(CPURISCVState *env)
}
}
+void helper_hyp_tlb_flush(CPURISCVState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
+ tlb_flush(cs);
+ return;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
#endif /* !CONFIG_USER_ONLY */
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 11/32] riscv/opentitan: Fix the ROM size
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 10/32] target/riscv: Implement checks for hfence Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
` (22 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Damien Hedde, alistair23, Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Damien Hedde <damien.hedde@greensocs.com>
---
hw/riscv/opentitan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index f6776da8e9..011e4f7ee2 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -25,12 +25,13 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "exec/address-spaces.h"
+#include "qemu/units.h"
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} ibex_memmap[] = {
- [IBEX_ROM] = { 0x00008000, 0xc000 },
+ [IBEX_ROM] = { 0x00008000, 16 * KiB },
[IBEX_RAM] = { 0x10000000, 0x10000 },
[IBEX_FLASH] = { 0x20000000, 0x80000 },
[IBEX_UART] = { 0x40000000, 0x10000 },
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 12/32] hw/char: Initial commit of Ibex UART
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
` (21 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Alistair Francis, LIU Zhiwei
This is the initial commit of the Ibex UART device. Serial TX is
working, while RX has been implemeneted but untested.
This is based on the documentation from:
https://docs.opentitan.org/hw/ip/uart/doc/
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
---
include/hw/char/ibex_uart.h | 110 ++++++++
hw/char/ibex_uart.c | 492 ++++++++++++++++++++++++++++++++++++
MAINTAINERS | 2 +
hw/char/Makefile.objs | 1 +
hw/riscv/Kconfig | 4 +
5 files changed, 609 insertions(+)
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 hw/char/ibex_uart.c
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
new file mode 100644
index 0000000000..2bec772615
--- /dev/null
+++ b/include/hw/char/ibex_uart.h
@@ -0,0 +1,110 @@
+/*
+ * QEMU lowRISC Ibex UART device
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IBEX_UART_H
+#define HW_IBEX_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "qemu/timer.h"
+
+#define IBEX_UART_INTR_STATE 0x00
+ #define INTR_STATE_TX_WATERMARK (1 << 0)
+ #define INTR_STATE_RX_WATERMARK (1 << 1)
+ #define INTR_STATE_TX_EMPTY (1 << 2)
+ #define INTR_STATE_RX_OVERFLOW (1 << 3)
+#define IBEX_UART_INTR_ENABLE 0x04
+#define IBEX_UART_INTR_TEST 0x08
+
+#define IBEX_UART_CTRL 0x0c
+ #define UART_CTRL_TX_ENABLE (1 << 0)
+ #define UART_CTRL_RX_ENABLE (1 << 1)
+ #define UART_CTRL_NF (1 << 2)
+ #define UART_CTRL_SLPBK (1 << 4)
+ #define UART_CTRL_LLPBK (1 << 5)
+ #define UART_CTRL_PARITY_EN (1 << 6)
+ #define UART_CTRL_PARITY_ODD (1 << 7)
+ #define UART_CTRL_RXBLVL (3 << 8)
+ #define UART_CTRL_NCO (0xFFFF << 16)
+
+#define IBEX_UART_STATUS 0x10
+ #define UART_STATUS_TXFULL (1 << 0)
+ #define UART_STATUS_RXFULL (1 << 1)
+ #define UART_STATUS_TXEMPTY (1 << 2)
+ #define UART_STATUS_RXIDLE (1 << 4)
+ #define UART_STATUS_RXEMPTY (1 << 5)
+
+#define IBEX_UART_RDATA 0x14
+#define IBEX_UART_WDATA 0x18
+
+#define IBEX_UART_FIFO_CTRL 0x1c
+ #define FIFO_CTRL_RXRST (1 << 0)
+ #define FIFO_CTRL_TXRST (1 << 1)
+ #define FIFO_CTRL_RXILVL (7 << 2)
+ #define FIFO_CTRL_RXILVL_SHIFT (2)
+ #define FIFO_CTRL_TXILVL (3 << 5)
+ #define FIFO_CTRL_TXILVL_SHIFT (5)
+
+#define IBEX_UART_FIFO_STATUS 0x20
+#define IBEX_UART_OVRD 0x24
+#define IBEX_UART_VAL 0x28
+#define IBEX_UART_TIMEOUT_CTRL 0x2c
+
+#define IBEX_UART_TX_FIFO_SIZE 16
+
+#define TYPE_IBEX_UART "ibex-uart"
+#define IBEX_UART(obj) \
+ OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
+ uint32_t tx_level;
+
+ QEMUTimer *fifo_trigger_handle;
+ uint64_t char_tx_time;
+
+ uint32_t uart_intr_state;
+ uint32_t uart_intr_enable;
+ uint32_t uart_ctrl;
+ uint32_t uart_status;
+ uint32_t uart_rdata;
+ uint32_t uart_fifo_ctrl;
+ uint32_t uart_fifo_status;
+ uint32_t uart_ovrd;
+ uint32_t uart_val;
+ uint32_t uart_timeout_ctrl;
+
+ CharBackend chr;
+ qemu_irq tx_watermark;
+ qemu_irq rx_watermark;
+ qemu_irq tx_empty;
+ qemu_irq rx_overflow;
+} IbexUartState;
+#endif /* HW_IBEX_UART_H */
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
new file mode 100644
index 0000000000..3e0dd9968e
--- /dev/null
+++ b/hw/char/ibex_uart.c
@@ -0,0 +1,492 @@
+/*
+ * QEMU lowRISC Ibex UART device
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * For details check the documentation here:
+ * https://docs.opentitan.org/hw/ip/uart/doc/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/ibex_uart.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+
+static void ibex_uart_update_irqs(IbexUartState *s)
+{
+ if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {
+ qemu_set_irq(s->tx_watermark, 1);
+ } else {
+ qemu_set_irq(s->tx_watermark, 0);
+ }
+
+ if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {
+ qemu_set_irq(s->rx_watermark, 1);
+ } else {
+ qemu_set_irq(s->rx_watermark, 0);
+ }
+
+ if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {
+ qemu_set_irq(s->tx_empty, 1);
+ } else {
+ qemu_set_irq(s->tx_empty, 0);
+ }
+
+ if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {
+ qemu_set_irq(s->rx_overflow, 1);
+ } else {
+ qemu_set_irq(s->rx_overflow, 0);
+ }
+}
+
+static int ibex_uart_can_receive(void *opaque)
+{
+ IbexUartState *s = opaque;
+
+ if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ IbexUartState *s = opaque;
+ uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)
+ >> FIFO_CTRL_RXILVL_SHIFT;
+
+ s->uart_rdata = *buf;
+
+ s->uart_status &= ~UART_STATUS_RXIDLE;
+ s->uart_status &= ~UART_STATUS_RXEMPTY;
+
+ if (size > rx_fifo_level) {
+ s->uart_intr_state |= INTR_STATE_RX_WATERMARK;
+ }
+
+ ibex_uart_update_irqs(s);
+}
+
+static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
+ void *opaque)
+{
+ IbexUartState *s = opaque;
+ uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
+ >> FIFO_CTRL_TXILVL_SHIFT;
+ int ret;
+
+ /* instant drain the fifo when there's no back-end */
+ if (!qemu_chr_fe_backend_connected(&s->chr)) {
+ s->tx_level = 0;
+ return FALSE;
+ }
+
+ if (!s->tx_level) {
+ s->uart_status &= ~UART_STATUS_TXFULL;
+ s->uart_status |= UART_STATUS_TXEMPTY;
+ s->uart_intr_state |= INTR_STATE_TX_EMPTY;
+ s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+ ibex_uart_update_irqs(s);
+ return FALSE;
+ }
+
+ ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
+
+ if (ret >= 0) {
+ s->tx_level -= ret;
+ memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
+ }
+
+ if (s->tx_level) {
+ guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+ ibex_uart_xmit, s);
+ if (!r) {
+ s->tx_level = 0;
+ return FALSE;
+ }
+ }
+
+ /* Clear the TX Full bit */
+ if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
+ s->uart_status &= ~UART_STATUS_TXFULL;
+ }
+
+ /* Disable the TX_WATERMARK IRQ */
+ if (s->tx_level < tx_fifo_level) {
+ s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+ }
+
+ /* Set TX empty */
+ if (s->tx_level == 0) {
+ s->uart_status |= UART_STATUS_TXEMPTY;
+ s->uart_intr_state |= INTR_STATE_TX_EMPTY;
+ }
+
+ ibex_uart_update_irqs(s);
+ return FALSE;
+}
+
+static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
+ int size)
+{
+ uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
+ >> FIFO_CTRL_TXILVL_SHIFT;
+
+ if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
+ size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
+ qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow");
+ }
+
+ memcpy(s->tx_fifo + s->tx_level, buf, size);
+ s->tx_level += size;
+
+ if (s->tx_level > 0) {
+ s->uart_status &= ~UART_STATUS_TXEMPTY;
+ }
+
+ if (s->tx_level >= tx_fifo_level) {
+ s->uart_intr_state |= INTR_STATE_TX_WATERMARK;
+ ibex_uart_update_irqs(s);
+ }
+
+ if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
+ s->uart_status |= UART_STATUS_TXFULL;
+ }
+
+ timer_mod(s->fifo_trigger_handle, current_time +
+ (s->char_tx_time * 4));
+}
+
+static void ibex_uart_reset(DeviceState *dev)
+{
+ IbexUartState *s = IBEX_UART(dev);
+
+ s->uart_intr_state = 0x00000000;
+ s->uart_intr_state = 0x00000000;
+ s->uart_intr_enable = 0x00000000;
+ s->uart_ctrl = 0x00000000;
+ s->uart_status = 0x0000003c;
+ s->uart_rdata = 0x00000000;
+ s->uart_fifo_ctrl = 0x00000000;
+ s->uart_fifo_status = 0x00000000;
+ s->uart_ovrd = 0x00000000;
+ s->uart_val = 0x00000000;
+ s->uart_timeout_ctrl = 0x00000000;
+
+ s->tx_level = 0;
+
+ s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
+
+ ibex_uart_update_irqs(s);
+}
+
+static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ IbexUartState *s = opaque;
+ uint64_t retvalue = 0;
+
+ switch (addr) {
+ case IBEX_UART_INTR_STATE:
+ retvalue = s->uart_intr_state;
+ break;
+ case IBEX_UART_INTR_ENABLE:
+ retvalue = s->uart_intr_enable;
+ break;
+ case IBEX_UART_INTR_TEST:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: wdata is write only\n", __func__);
+ break;
+
+ case IBEX_UART_CTRL:
+ retvalue = s->uart_ctrl;
+ break;
+ case IBEX_UART_STATUS:
+ retvalue = s->uart_status;
+ break;
+
+ case IBEX_UART_RDATA:
+ retvalue = s->uart_rdata;
+ if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+ qemu_chr_fe_accept_input(&s->chr);
+
+ s->uart_status |= UART_STATUS_RXIDLE;
+ s->uart_status |= UART_STATUS_RXEMPTY;
+ }
+ break;
+ case IBEX_UART_WDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: wdata is write only\n", __func__);
+ break;
+
+ case IBEX_UART_FIFO_CTRL:
+ retvalue = s->uart_fifo_ctrl;
+ break;
+ case IBEX_UART_FIFO_STATUS:
+ retvalue = s->uart_fifo_status;
+
+ retvalue |= s->tx_level & 0x1F;
+
+ qemu_log_mask(LOG_UNIMP,
+ "%s: RX fifos are not supported\n", __func__);
+ break;
+
+ case IBEX_UART_OVRD:
+ retvalue = s->uart_ovrd;
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ovrd is not supported\n", __func__);
+ break;
+ case IBEX_UART_VAL:
+ retvalue = s->uart_val;
+ qemu_log_mask(LOG_UNIMP,
+ "%s: val is not supported\n", __func__);
+ break;
+ case IBEX_UART_TIMEOUT_CTRL:
+ retvalue = s->uart_timeout_ctrl;
+ qemu_log_mask(LOG_UNIMP,
+ "%s: timeout_ctrl is not supported\n", __func__);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return retvalue;
+}
+
+static void ibex_uart_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ IbexUartState *s = opaque;
+ uint32_t value = val64;
+
+ switch (addr) {
+ case IBEX_UART_INTR_STATE:
+ /* Write 1 clear */
+ s->uart_intr_state &= ~value;
+ ibex_uart_update_irqs(s);
+ break;
+ case IBEX_UART_INTR_ENABLE:
+ s->uart_intr_enable = value;
+ ibex_uart_update_irqs(s);
+ break;
+ case IBEX_UART_INTR_TEST:
+ s->uart_intr_state |= value;
+ ibex_uart_update_irqs(s);
+ break;
+
+ case IBEX_UART_CTRL:
+ s->uart_ctrl = value;
+
+ if (value & UART_CTRL_NF) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_NF is not supported\n", __func__);
+ }
+ if (value & UART_CTRL_SLPBK) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_SLPBK is not supported\n", __func__);
+ }
+ if (value & UART_CTRL_LLPBK) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_LLPBK is not supported\n", __func__);
+ }
+ if (value & UART_CTRL_PARITY_EN) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_PARITY_EN is not supported\n",
+ __func__);
+ }
+ if (value & UART_CTRL_PARITY_ODD) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_PARITY_ODD is not supported\n",
+ __func__);
+ }
+ if (value & UART_CTRL_RXBLVL) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
+ }
+ if (value & UART_CTRL_NCO) {
+ uint64_t baud = ((value & UART_CTRL_NCO) >> 16);
+ baud *= 1000;
+ baud /= 2 ^ 20;
+
+ s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
+ }
+ break;
+ case IBEX_UART_STATUS:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: status is read only\n", __func__);
+ break;
+
+ case IBEX_UART_RDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: rdata is read only\n", __func__);
+ break;
+ case IBEX_UART_WDATA:
+ uart_write_tx_fifo(s, (uint8_t *) &value, 1);
+ break;
+
+ case IBEX_UART_FIFO_CTRL:
+ s->uart_fifo_ctrl = value;
+
+ if (value & FIFO_CTRL_RXRST) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: RX fifos are not supported\n", __func__);
+ }
+ if (value & FIFO_CTRL_TXRST) {
+ s->tx_level = 0;
+ }
+ break;
+ case IBEX_UART_FIFO_STATUS:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: fifo_status is read only\n", __func__);
+ break;
+
+ case IBEX_UART_OVRD:
+ s->uart_ovrd = value;
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ovrd is not supported\n", __func__);
+ break;
+ case IBEX_UART_VAL:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: val is read only\n", __func__);
+ break;
+ case IBEX_UART_TIMEOUT_CTRL:
+ s->uart_timeout_ctrl = value;
+ qemu_log_mask(LOG_UNIMP,
+ "%s: timeout_ctrl is not supported\n", __func__);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static void fifo_trigger_update(void *opaque)
+{
+ IbexUartState *s = opaque;
+
+ if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {
+ ibex_uart_xmit(NULL, G_IO_OUT, s);
+ }
+}
+
+static const MemoryRegionOps ibex_uart_ops = {
+ .read = ibex_uart_read,
+ .write = ibex_uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+};
+
+static int ibex_uart_post_load(void *opaque, int version_id)
+{
+ IbexUartState *s = opaque;
+
+ ibex_uart_update_irqs(s);
+ return 0;
+}
+
+static const VMStateDescription vmstate_ibex_uart = {
+ .name = TYPE_IBEX_UART,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = ibex_uart_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
+ IBEX_UART_TX_FIFO_SIZE),
+ VMSTATE_UINT32(tx_level, IbexUartState),
+ VMSTATE_UINT64(char_tx_time, IbexUartState),
+ VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState),
+ VMSTATE_UINT32(uart_intr_state, IbexUartState),
+ VMSTATE_UINT32(uart_intr_enable, IbexUartState),
+ VMSTATE_UINT32(uart_ctrl, IbexUartState),
+ VMSTATE_UINT32(uart_status, IbexUartState),
+ VMSTATE_UINT32(uart_rdata, IbexUartState),
+ VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState),
+ VMSTATE_UINT32(uart_fifo_status, IbexUartState),
+ VMSTATE_UINT32(uart_ovrd, IbexUartState),
+ VMSTATE_UINT32(uart_val, IbexUartState),
+ VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property ibex_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", IbexUartState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ibex_uart_init(Object *obj)
+{
+ IbexUartState *s = IBEX_UART(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);
+
+ memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s,
+ TYPE_IBEX_UART, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ibex_uart_realize(DeviceState *dev, Error **errp)
+{
+ IbexUartState *s = IBEX_UART(dev);
+
+ s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ fifo_trigger_update, s);
+
+ qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive,
+ ibex_uart_receive, NULL, NULL,
+ s, NULL, true);
+}
+
+static void ibex_uart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = ibex_uart_reset;
+ dc->realize = ibex_uart_realize;
+ dc->vmsd = &vmstate_ibex_uart;
+ device_class_set_props(dc, ibex_uart_properties);
+}
+
+static const TypeInfo ibex_uart_info = {
+ .name = TYPE_IBEX_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IbexUartState),
+ .instance_init = ibex_uart_init,
+ .class_init = ibex_uart_class_init,
+};
+
+static void ibex_uart_register_types(void)
+{
+ type_register_static(&ibex_uart_info);
+}
+
+type_init(ibex_uart_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 955cc8dd5c..4010ea5606 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1250,7 +1250,9 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/opentitan.c
+F: hw/char/ibex_uart.c
F: include/hw/riscv/opentitan.h
+F: include/hw/char/ibex_uart.h
SH4 Machines
------------
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 9e9a6c1aff..633996be5b 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_VIRTIO_SERIAL) += virtio-console.o
common-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
common-obj-$(CONFIG_XEN) += xen_console.o
common-obj-$(CONFIG_CADENCE) += cadence_uart.o
+common-obj-$(CONFIG_IBEX) += ibex_uart.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_uart.o
common-obj-$(CONFIG_COLDFIRE) += mcf_uart.o
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 94d19571f7..28947ef3e0 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,9 @@ config HTIF
config HART
bool
+config IBEX
+ bool
+
config SIFIVE
bool
select MSI_NONBROKEN
@@ -29,6 +32,7 @@ config SPIKE
config OPENTITAN
bool
+ select IBEX
select HART
select UNIMP
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
` (20 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Alistair Francis, Philippe Mathieu-Daudé
The Ibex core contains a PLIC that although similar to the RISC-V spec
is not RISC-V spec compliant.
This patch implements a Ibex PLIC in a somewhat generic way.
As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex
PLIC move towards spec compliance this PLIC implementation can be
updated until it can replace the current PLIC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/intc/ibex_plic.h | 63 +++++++++
hw/intc/ibex_plic.c | 261 ++++++++++++++++++++++++++++++++++++
MAINTAINERS | 2 +
hw/intc/Makefile.objs | 1 +
4 files changed, 327 insertions(+)
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 hw/intc/ibex_plic.c
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
new file mode 100644
index 0000000000..ddc7909903
--- /dev/null
+++ b/include/hw/intc/ibex_plic.h
@@ -0,0 +1,63 @@
+/*
+ * QEMU RISC-V lowRISC Ibex PLIC
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_IBEX_PLIC_H
+#define HW_IBEX_PLIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IBEX_PLIC "ibex-plic"
+#define IBEX_PLIC(obj) \
+ OBJECT_CHECK(IbexPlicState, (obj), TYPE_IBEX_PLIC)
+
+typedef struct IbexPlicState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+
+ uint32_t *pending;
+ uint32_t *source;
+ uint32_t *priority;
+ uint32_t *enable;
+ uint32_t threshold;
+ uint32_t claim;
+
+ /* config */
+ uint32_t num_cpus;
+ uint32_t num_sources;
+
+ uint32_t pending_base;
+ uint32_t pending_num;
+
+ uint32_t source_base;
+ uint32_t source_num;
+
+ uint32_t priority_base;
+ uint32_t priority_num;
+
+ uint32_t enable_base;
+ uint32_t enable_num;
+
+ uint32_t threshold_base;
+
+ uint32_t claim_base;
+} IbexPlicState;
+
+#endif /* HW_IBEX_PLIC_H */
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
new file mode 100644
index 0000000000..41079518c6
--- /dev/null
+++ b/hw/intc/ibex_plic.c
@@ -0,0 +1,261 @@
+/*
+ * QEMU RISC-V lowRISC Ibex PLIC
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/core/cpu.h"
+#include "hw/boards.h"
+#include "hw/pci/msi.h"
+#include "target/riscv/cpu_bits.h"
+#include "target/riscv/cpu.h"
+#include "hw/intc/ibex_plic.h"
+
+static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
+{
+ uint32_t end = base + (num * 0x04);
+
+ if (addr >= base && addr < end) {
+ return true;
+ }
+
+ return false;
+}
+
+static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
+{
+ int pending_num = irq / 32;
+
+ s->pending[pending_num] |= level << (irq % 32);
+}
+
+static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
+{
+ int i;
+
+ for (i = 0; i < s->pending_num; i++) {
+ uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
+
+ if (!(s->pending[i] & s->enable[i])) {
+ /* No pending and enabled IRQ */
+ continue;
+ }
+
+ if (s->priority[irq_num] > s->threshold) {
+ if (!s->claim) {
+ s->claim = irq_num;
+ }
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static void ibex_plic_update(IbexPlicState *s)
+{
+ CPUState *cpu;
+ int level, i;
+
+ for (i = 0; i < s->num_cpus; i++) {
+ cpu = qemu_get_cpu(i);
+
+ if (!cpu) {
+ continue;
+ }
+
+ level = ibex_plic_irqs_pending(s, 0);
+
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
+ }
+}
+
+static void ibex_plic_reset(DeviceState *dev)
+{
+ IbexPlicState *s = IBEX_PLIC(dev);
+
+ s->threshold = 0x00000000;
+ s->claim = 0x00000000;
+}
+
+static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ IbexPlicState *s = opaque;
+ int offset;
+ uint32_t ret = 0;
+
+ if (addr_between(addr, s->pending_base, s->pending_num)) {
+ offset = (addr - s->pending_base) / 4;
+ ret = s->pending[offset];
+ } else if (addr_between(addr, s->source_base, s->source_num)) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Interrupt source mode not supported\n", __func__);
+ } else if (addr_between(addr, s->priority_base, s->priority_num)) {
+ offset = (addr - s->priority_base) / 4;
+ ret = s->priority[offset];
+ } else if (addr_between(addr, s->enable_base, s->enable_num)) {
+ offset = (addr - s->enable_base) / 4;
+ ret = s->enable[offset];
+ } else if (addr_between(addr, s->threshold_base, 1)) {
+ ret = s->threshold;
+ } else if (addr_between(addr, s->claim_base, 1)) {
+ int pending_num = s->claim / 32;
+ s->pending[pending_num] &= ~(1 << (s->claim % 32));
+
+ ret = s->claim;
+ }
+
+ return ret;
+}
+
+static void ibex_plic_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
+{
+ IbexPlicState *s = opaque;
+
+ if (addr_between(addr, s->pending_base, s->pending_num)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Pending registers are read only\n", __func__);
+ } else if (addr_between(addr, s->source_base, s->source_num)) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Interrupt source mode not supported\n", __func__);
+ } else if (addr_between(addr, s->priority_base, s->priority_num)) {
+ uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
+ s->priority[irq] = value & 7;
+ } else if (addr_between(addr, s->enable_base, s->enable_num)) {
+ uint32_t enable_reg = (addr - s->enable_base) / 4;
+
+ s->enable[enable_reg] = value;
+ } else if (addr_between(addr, s->threshold_base, 1)) {
+ s->threshold = value & 3;
+ } else if (addr_between(addr, s->claim_base, 1)) {
+ if (s->claim == value) {
+ /* Interrupt was completed */
+ s->claim = 0;
+ }
+ }
+
+ ibex_plic_update(s);
+}
+
+static const MemoryRegionOps ibex_plic_ops = {
+ .read = ibex_plic_read,
+ .write = ibex_plic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void ibex_plic_irq_request(void *opaque, int irq, int level)
+{
+ IbexPlicState *s = opaque;
+
+ ibex_plic_irqs_set_pending(s, irq, level > 0);
+ ibex_plic_update(s);
+}
+
+static Property ibex_plic_properties[] = {
+ DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
+ DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+
+ DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
+ DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+
+ DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
+ DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+
+ DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
+ DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+
+ DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
+ DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+
+ DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
+
+ DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ibex_plic_init(Object *obj)
+{
+ IbexPlicState *s = IBEX_PLIC(obj);
+
+ memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
+ TYPE_IBEX_PLIC, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ibex_plic_realize(DeviceState *dev, Error **errp)
+{
+ IbexPlicState *s = IBEX_PLIC(dev);
+ int i;
+
+ s->pending = g_new0(uint32_t, s->pending_num);
+ s->source = g_new0(uint32_t, s->source_num);
+ s->priority = g_new0(uint32_t, s->priority_num);
+ s->enable = g_new0(uint32_t, s->enable_num);
+
+ qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
+
+ /*
+ * We can't allow the supervisor to control SEIP as this would allow the
+ * supervisor to clear a pending external interrupt which will result in
+ * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
+ * hardware controlled when a PLIC is attached.
+ */
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
+ for (i = 0; i < smp_cpus; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
+ if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
+ error_report("SEIP already claimed");
+ exit(1);
+ }
+ }
+
+ msi_nonbroken = true;
+}
+
+static void ibex_plic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = ibex_plic_reset;
+ device_class_set_props(dc, ibex_plic_properties);
+ dc->realize = ibex_plic_realize;
+}
+
+static const TypeInfo ibex_plic_info = {
+ .name = TYPE_IBEX_PLIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IbexPlicState),
+ .instance_init = ibex_plic_init,
+ .class_init = ibex_plic_class_init,
+};
+
+static void ibex_plic_register_types(void)
+{
+ type_register_static(&ibex_plic_info);
+}
+
+type_init(ibex_plic_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4010ea5606..63b3bb3266 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1251,8 +1251,10 @@ L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/opentitan.c
F: hw/char/ibex_uart.c
+F: hw/intc/ibex_plic.c
F: include/hw/riscv/opentitan.h
F: include/hw/char/ibex_uart.h
+F: include/hw/intc/ibex_plic.h
SH4 Machines
------------
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index f726d87532..a61e6728fe 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -49,3 +49,4 @@ obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
obj-$(CONFIG_MIPS_CPS) += mips_gic.o
obj-$(CONFIG_NIOS2) += nios2_iic.o
obj-$(CONFIG_OMPIC) += ompic.o
+obj-$(CONFIG_IBEX) += ibex_plic.o
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 14/32] riscv/opentitan: Connect the PLIC device
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
@ 2020-06-19 16:57 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 15/32] riscv/opentitan: Connect the UART device Alistair Francis
` (19 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:57 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/riscv/opentitan.h | 3 +++
hw/riscv/opentitan.c | 14 ++++++++++++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index a4b6499444..76f72905a8 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -20,6 +20,7 @@
#define HW_OPENTITAN_H
#include "hw/riscv/riscv_hart.h"
+#include "hw/intc/ibex_plic.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
#define RISCV_IBEX_SOC(obj) \
@@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
+ IbexPlicState plic;
+
MemoryRegion flash_mem;
MemoryRegion rom;
} LowRISCIbexSoCState;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 011e4f7ee2..835b2c503f 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -26,6 +26,7 @@
#include "hw/riscv/boot.h"
#include "exec/address-spaces.h"
#include "qemu/units.h"
+#include "sysemu/sysemu.h"
static const struct MemmapEntry {
hwaddr base;
@@ -94,6 +95,8 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
+
+ object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -102,6 +105,7 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
+ Error *err = NULL;
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
@@ -121,6 +125,14 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
&s->flash_mem);
+ /* PLIC */
+ sysbus_realize(SYS_BUS_DEVICE(&s->plic), &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);
+
create_unimplemented_device("riscv.lowrisc.ibex.uart",
memmap[IBEX_UART].base, memmap[IBEX_UART].size);
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
@@ -141,8 +153,6 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_AES].base, memmap[IBEX_AES].size);
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
- create_unimplemented_device("riscv.lowrisc.ibex.plic",
- memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 15/32] riscv/opentitan: Connect the UART device
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2020-06-19 16:57 ` [PULL v2 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
` (18 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/riscv/opentitan.h | 13 +++++++++++++
hw/riscv/opentitan.c | 25 +++++++++++++++++++++++--
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 76f72905a8..8f29b9cbbf 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
+#include "hw/char/ibex_uart.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
#define RISCV_IBEX_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
IbexPlicState plic;
+ IbexUartState uart;
MemoryRegion flash_mem;
MemoryRegion rom;
@@ -68,4 +70,15 @@ enum {
IBEX_PADCTRL,
};
+enum {
+ IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
+ IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
+ IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
+ IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
+ IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
+ IBEX_UART_TX_EMPTY_IRQ = 0x23,
+ IBEX_UART_RX_WATERMARK_IRQ = 0x22,
+ IBEX_UART_TX_WATERMARK_IRQ = 0x21,
+};
+
#endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 835b2c503f..675ce900bd 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -97,6 +97,8 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
+
+ object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -133,8 +135,27 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);
- create_unimplemented_device("riscv.lowrisc.ibex.uart",
- memmap[IBEX_UART].base, memmap[IBEX_UART].size);
+ /* UART */
+ qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_UART].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+ 0, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_TX_WATERMARK_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+ 1, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_RX_WATERMARK_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+ 2, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_TX_EMPTY_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+ 3, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_RX_OVERFLOW_IRQ));
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi",
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 15/32] riscv/opentitan: Connect the UART device Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
` (17 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/pmp.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0e6b640fbd..9418660f1b 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -233,12 +233,16 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
return true;
}
- /*
- * if size is unknown (0), assume that all bytes
- * from addr to the end of the page will be accessed.
- */
if (size == 0) {
- pmp_size = -(addr | TARGET_PAGE_MASK);
+ if (riscv_feature(env, RISCV_FEATURE_MMU)) {
+ /*
+ * If size is unknown (0), assume that all bytes
+ * from addr to the end of the page will be accessed.
+ */
+ pmp_size = -(addr | TARGET_PAGE_MASK);
+ } else {
+ pmp_size = sizeof(target_ulong);
+ }
} else {
pmp_size = size;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 18/32] hw/riscv: opentitan: " Alistair Francis
` (16 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36486b72d2..01626820bb 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -75,7 +75,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void riscv_sifive_e_init(MachineState *machine)
+static void sifive_e_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -147,7 +147,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
+ mc->init = sifive_e_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
}
@@ -167,7 +167,7 @@ static void sifive_e_machine_init_register_types(void)
type_init(sifive_e_machine_init_register_types)
-static void riscv_sifive_e_soc_init(Object *obj)
+static void sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
@@ -179,7 +179,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
TYPE_SIFIVE_GPIO);
}
-static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
+static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -262,26 +262,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
+static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = riscv_sifive_e_soc_realize;
+ dc->realize = sifive_e_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
-static const TypeInfo riscv_sifive_e_soc_type_info = {
+static const TypeInfo sifive_e_soc_type_info = {
.name = TYPE_RISCV_E_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SiFiveESoCState),
- .instance_init = riscv_sifive_e_soc_init,
- .class_init = riscv_sifive_e_soc_class_init,
+ .instance_init = sifive_e_soc_init,
+ .class_init = sifive_e_soc_class_init,
};
-static void riscv_sifive_e_soc_register_types(void)
+static void sifive_e_soc_register_types(void)
{
- type_register_static(&riscv_sifive_e_soc_type_info);
+ type_register_static(&sifive_e_soc_type_info);
}
-type_init(riscv_sifive_e_soc_register_types)
+type_init(sifive_e_soc_register_types)
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (16 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
` (15 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 675ce900bd..19223e4c29 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
};
-static void riscv_opentitan_init(MachineState *machine)
+static void opentitan_board_init(MachineState *machine)
{
const struct MemmapEntry *memmap = ibex_memmap;
OpenTitanState *s = g_new0(OpenTitanState, 1);
@@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
memory_region_add_subregion(sys_mem,
memmap[IBEX_RAM].base, main_mem);
-
if (machine->firmware) {
riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
}
@@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
}
}
-static void riscv_opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with OpenTitan";
- mc->init = riscv_opentitan_init;
+ mc->init = opentitan_board_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
}
-DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_init)
-static void riscv_lowrisc_ibex_soc_init(Object *obj)
+static void lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
@@ -101,7 +100,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
}
-static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
const struct MemmapEntry *memmap = ibex_memmap;
MachineState *ms = MACHINE(qdev_get_machine());
@@ -186,26 +185,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
}
-static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
+static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = riscv_lowrisc_ibex_soc_realize;
+ dc->realize = lowrisc_ibex_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
-static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
+static const TypeInfo lowrisc_ibex_soc_type_info = {
.name = TYPE_RISCV_IBEX_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(LowRISCIbexSoCState),
- .instance_init = riscv_lowrisc_ibex_soc_init,
- .class_init = riscv_lowrisc_ibex_soc_class_init,
+ .instance_init = lowrisc_ibex_soc_init,
+ .class_init = lowrisc_ibex_soc_class_init,
};
-static void riscv_lowrisc_ibex_soc_register_types(void)
+static void lowrisc_ibex_soc_register_types(void)
{
- type_register_static(&riscv_lowrisc_ibex_soc_type_info);
+ type_register_static(&lowrisc_ibex_soc_type_info);
}
-type_init(riscv_lowrisc_ibex_soc_register_types)
+type_init(lowrisc_ibex_soc_register_types)
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (17 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 18/32] hw/riscv: opentitan: " Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
` (14 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
There is no need to retrieve all PLIC IRQ information in order to
just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
what is done for other peripherals.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-4-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ea197ab64f..20b0276ea3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -514,7 +514,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
- qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -594,10 +593,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
- for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
- plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
- }
-
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
@@ -611,7 +606,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
- plic_gpios[SIFIVE_U_GEM_IRQ]);
+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (18 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
` (13 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
based on device tree information. Let's generate the device tree
node for OTP.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 20b0276ea3..a6dfce4273 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/otp@%lx",
+ (long)memmap[SIFIVE_U_OTP].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_OTP].base,
+ 0x0, memmap[SIFIVE_U_OTP].size);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "sifive,fu540-c000-otp");
+ g_free(nodename);
+
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
(long)memmap[SIFIVE_U_PRCI].base);
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (19 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
` (12 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_gpio.h | 7 ++++---
hw/riscv/sifive_gpio.c | 13 +++++--------
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index fce03d6c41..ad915b26d6 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -10,10 +10,12 @@
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
+
#ifndef SIFIVE_GPIO_H
#define SIFIVE_GPIO_H
#include "hw/sysbus.h"
+
#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
@@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
uint32_t out_xor;
uint32_t in;
uint32_t in_mask;
-
} SIFIVEGPIOState;
-#endif
+#endif /* SIFIVE_GPIO_H */
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 5c7c596e6b..c9cffa2eba 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -20,7 +20,6 @@
static void update_output_irq(SIFIVEGPIOState *s)
{
-
uint32_t pending;
uint32_t pin;
@@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
}
static void sifive_gpio_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned int size)
+ uint64_t value, unsigned int size)
{
SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
@@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
s->out_xor = 0;
s->in = 0;
s->in_mask = 0;
-
}
static const VMStateDescription vmstate_sifive_gpio = {
@@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
- VMSTATE_UINT32(in, SIFIVEGPIOState),
- VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+ VMSTATE_UINT32(in, SIFIVEGPIOState),
+ VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
VMSTATE_END_OF_LIST()
}
};
@@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-
for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
}
@@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_sifive_gpio;
dc->reset = sifive_gpio_reset;
- dc->desc = "sifive GPIO";
+ dc->desc = "SiFive GPIO";
}
static const TypeInfo sifive_gpio_info = {
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (20 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
` (11 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Add a new property to represent the number of GPIO pins supported
by the GPIO controller.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-7-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_gpio.h | 3 +++
hw/riscv/sifive_gpio.c | 30 +++++++++++++++++++-----------
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index ad915b26d6..cf12fcfd62 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -68,6 +68,9 @@ typedef struct SIFIVEGPIOState {
uint32_t out_xor;
uint32_t in;
uint32_t in_mask;
+
+ /* config */
+ uint32_t ngpio;
} SIFIVEGPIOState;
#endif /* SIFIVE_GPIO_H */
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index c9cffa2eba..0d0fd2ba5e 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -14,6 +14,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "hw/riscv/sifive_gpio.h"
#include "migration/vmstate.h"
#include "trace.h"
@@ -28,7 +29,7 @@ static void update_output_irq(SIFIVEGPIOState *s)
pending |= s->rise_ip & s->rise_ie;
pending |= s->fall_ip & s->fall_ie;
- for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ for (int i = 0; i < s->ngpio; i++) {
pin = 1 << i;
qemu_set_irq(s->irq[i], (pending & pin) != 0);
trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
@@ -41,7 +42,7 @@ static void update_state(SIFIVEGPIOState *s)
bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
- for (i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ for (i = 0; i < s->ngpio; i++) {
prev_ival = extract32(s->value, i, 1);
in = extract32(s->in, i, 1);
@@ -346,27 +347,35 @@ static const VMStateDescription vmstate_sifive_gpio = {
}
};
-static void sifive_gpio_init(Object *obj)
+static Property sifive_gpio_properties[] = {
+ DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_gpio_realize(DeviceState *dev, Error **errp)
{
- SIFIVEGPIOState *s = SIFIVE_GPIO(obj);
+ SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
- memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
+ memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
- for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ for (int i = 0; i < s->ngpio; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
}
- qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);
- qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);
+ qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
+ qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
}
static void sifive_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, sifive_gpio_properties);
dc->vmsd = &vmstate_sifive_gpio;
+ dc->realize = sifive_gpio_realize;
dc->reset = sifive_gpio_reset;
dc->desc = "SiFive GPIO";
}
@@ -375,7 +384,6 @@ static const TypeInfo sifive_gpio_info = {
.name = TYPE_SIFIVE_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SIFIVEGPIOState),
- .instance_init = sifive_gpio_init,
.class_init = sifive_gpio_class_init
};
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (21 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
` (10 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
This hooks the exsiting SiFive GPIO model to the SoC, and adds its
device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 19 ++++++++++++++++
hw/riscv/sifive_u.c | 43 +++++++++++++++++++++++++++++++++++--
2 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5f62cf5f85..b1399a90a6 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -22,6 +22,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
+#include "hw/riscv/sifive_gpio.h"
#include "hw/riscv/sifive_u_prci.h"
#include "hw/riscv/sifive_u_otp.h"
@@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
+ SIFIVEGPIOState gpio;
SiFiveUOTPState otp;
CadenceGEMState gem;
@@ -73,6 +75,7 @@ enum {
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
+ SIFIVE_U_GPIO,
SIFIVE_U_OTP,
SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
@@ -83,6 +86,22 @@ enum {
enum {
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
+ SIFIVE_U_GPIO_IRQ0 = 7,
+ SIFIVE_U_GPIO_IRQ1 = 8,
+ SIFIVE_U_GPIO_IRQ2 = 9,
+ SIFIVE_U_GPIO_IRQ3 = 10,
+ SIFIVE_U_GPIO_IRQ4 = 11,
+ SIFIVE_U_GPIO_IRQ5 = 12,
+ SIFIVE_U_GPIO_IRQ6 = 13,
+ SIFIVE_U_GPIO_IRQ7 = 14,
+ SIFIVE_U_GPIO_IRQ8 = 15,
+ SIFIVE_U_GPIO_IRQ9 = 16,
+ SIFIVE_U_GPIO_IRQ10 = 17,
+ SIFIVE_U_GPIO_IRQ11 = 18,
+ SIFIVE_U_GPIO_IRQ12 = 19,
+ SIFIVE_U_GPIO_IRQ13 = 20,
+ SIFIVE_U_GPIO_IRQ14 = 21,
+ SIFIVE_U_GPIO_IRQ15 = 22,
SIFIVE_U_GEM_IRQ = 0x35
};
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a6dfce4273..f6976a0d09 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -11,8 +11,9 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
* 3) PRCI (Power, Reset, Clock, Interrupt)
- * 4) OTP (One-Time Programmable) memory with stored serial number
- * 5) GEM (Gigabit Ethernet Controller) and management block
+ * 4) GPIO (General Purpose Input/Output Controller)
+ * 5) OTP (One-Time Programmable) memory with stored serial number
+ * 6) GEM (Gigabit Ethernet Controller) and management block
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -75,6 +76,7 @@ static const struct MemmapEntry {
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
@@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/gpio@%lx",
+ (long)memmap[SIFIVE_U_GPIO].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
+ qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_GPIO].base,
+ 0x0, memmap[SIFIVE_U_GPIO].size);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
+ SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
+ SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
+ SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
+ SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
+ SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
+ g_free(nodename);
+
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -515,6 +539,7 @@ static void sifive_u_soc_instance_init(Object *obj)
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -600,6 +625,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->prci), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+
+ /* Pass all GPIOs to the SOC layer so they are available to the board */
+ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
+
+ /* Connect GPIO interrupts to the PLIC */
+ for (i = 0; i < 16; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_U_GPIO_IRQ0 + i));
+ }
+
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (22 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
` (9 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_gpio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 0d0fd2ba5e..aac6b44cac 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
actual_value = pull;
}
- qemu_set_irq(s->output[i], actual_value);
+ if (output_en) {
+ qemu_set_irq(s->output[i], actual_value);
+ }
/* Input value */
ival = input_en && actual_value;
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (23 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
` (8 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-10-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f6976a0d09..b9d2185c04 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -37,6 +37,7 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "hw/boards.h"
+#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@@ -53,6 +54,7 @@
#include "net/eth.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
+#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
@@ -96,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint32_t *cells;
char *nodename;
char ethclk_names[] = "pclk\0hclk";
- uint32_t plic_phandle, prci_phandle, phandle = 1;
+ uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -270,9 +272,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
(long)memmap[SIFIVE_U_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
@@ -292,6 +296,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
g_free(nodename);
+ nodename = g_strdup_printf("/gpio-restart");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
+ g_free(nodename);
+
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -352,6 +362,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
+static void sifive_u_machine_reset(void *opaque, int n, int level)
+{
+ /* gpio pin active low triggers reset */
+ if (!level) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
+}
+
static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
@@ -380,6 +398,10 @@ static void sifive_u_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
flash0);
+ /* register gpio-restart */
+ qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
+ qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
+
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (24 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
` (7 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
In prepration to add more properties to this machine, rename the
existing serial property get/set functions to a generic name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-11-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b9d2185c04..6dac662910 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -478,14 +478,16 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
-static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
-static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
@@ -504,8 +506,8 @@ static void sifive_u_machine_instance_init(Object *obj)
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
- sifive_u_machine_get_serial,
- sifive_u_machine_set_serial, NULL, &s->serial);
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->serial);
object_property_set_description(obj, "serial", "Board serial number");
}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (25 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
` (6 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
On SiFive FU540 SoC, the value stored at physical address 0x1000
stores the MSEL pin state that is used to control the next boot
location that ROM codes jump to.
Add a new property msel to sifive_u machine for this.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index b1399a90a6..f6d10ebfb6 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -63,6 +63,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t msel;
uint32_t serial;
} SiFiveUState;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6dac662910..b04be42167 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -504,6 +504,13 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to "
"flash. Otherwise QEMU will jump to DRAM");
+ s->msel = 0;
+ object_property_add(obj, "msel", "uint32",
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+ object_property_set_description(obj, "msel",
+ "Mode Select (MSEL[3:0]) pin state");
+
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
sifive_u_machine_get_uint32_prop,
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (26 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
` (5 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Current IBEX CPU init routine name seems to be too generic.
Since it uses a different reset vector from the generic one,
it merits a dedicated name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e867766cf0..5f034588ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj)
#if defined(TARGET_RISCV32)
-static void rv32_imcu_nommu_cpu_init(Object *obj)
+static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
@@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (27 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
` (4 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 10 ++++++----
hw/riscv/sifive_u.c | 6 +++---
target/riscv/cpu.c | 16 ++++++++--------
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 01626820bb..0cb66ac4e2 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -95,14 +95,16 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2];
+ uint32_t reset_vec[4];
if (s->revb) {
- reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */
} else {
- reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */
}
- reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
+ reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */
+
+ reset_vec[0] = reset_vec[3] = 0;
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b04be42167..ed13bc043c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -430,18 +430,18 @@ static void sifive_u_machine_init(MachineState *machine)
/* reset vector */
uint32_t reset_vec[8] = {
+ 0x00000000,
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
+ 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
+ 0x0182e283, /* lwu t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
0x00000000,
start_addr, /* start: .dword */
- 0x00000000,
/* dtb: */
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5f034588ec..391a0b9eec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -134,20 +134,20 @@ static void riscv_base_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj)
+static void rvxx_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x1004);
}
-static void rvxx_imacu_nommu_cpu_init(Object *obj)
+static void rvxx_sifive_e_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x1004);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -578,13 +578,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init),
#endif
};
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (28 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
` (3 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.
The SoC supports booting from memory-mapped QSPI flash, which is
how start_in_flash property is used for at present. This matches
MSEL = 1 configuration (QSPI0).
Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
It's not necessary for QEMU to implement the full ZSBL ROM codes,
because we know ZSBL downloads the next stage program into the L2
LIM at address 0x8000000 and executes from there. We can bypass
the whole ZSBL execution and use "-bios" to load the next stage
program directly if MSEL indicates a ZSBL booting flow.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 6 ++++++
hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++--------
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index f6d10ebfb6..27dc35e0a3 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -111,6 +111,12 @@ enum {
SIFIVE_U_RTCCLK_FREQ = 1000000
};
+enum {
+ MSEL_MEMMAP_QSPI0_FLASH = 1,
+ MSEL_L2LIM_QSPI0_FLASH = 6,
+ MSEL_L2LIM_QSPI2_SD = 11
+};
+
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ed13bc043c..eb767aa863 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -405,8 +405,34 @@ static void sifive_u_machine_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
- riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[SIFIVE_U_DRAM].base, NULL);
+ if (s->start_in_flash) {
+ /*
+ * If start_in_flash property is given, assign s->msel to a value
+ * that representing booting from QSPI0 memory-mapped flash.
+ *
+ * This also means that when both start_in_flash and msel properties
+ * are given, start_in_flash takes the precedence over msel.
+ *
+ * Note this is to keep backward compatibility not to break existing
+ * users that use start_in_flash property.
+ */
+ s->msel = MSEL_MEMMAP_QSPI0_FLASH;
+ }
+
+ switch (s->msel) {
+ case MSEL_MEMMAP_QSPI0_FLASH:
+ start_addr = memmap[SIFIVE_U_FLASH0].base;
+ break;
+ case MSEL_L2LIM_QSPI0_FLASH:
+ case MSEL_L2LIM_QSPI2_SD:
+ start_addr = memmap[SIFIVE_U_L2LIM].base;
+ break;
+ default:
+ start_addr = memmap[SIFIVE_U_DRAM].base;
+ break;
+ }
+
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
@@ -424,13 +450,9 @@ static void sifive_u_machine_init(MachineState *machine)
}
}
- if (s->start_in_flash) {
- start_addr = memmap[SIFIVE_U_FLASH0].base;
- }
-
/* reset vector */
uint32_t reset_vec[8] = {
- 0x00000000,
+ s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
@@ -502,7 +524,8 @@ static void sifive_u_machine_instance_init(Object *obj)
sifive_u_machine_set_start_in_flash);
object_property_set_description(obj, "start-in-flash",
"Set on to tell QEMU's ROM to jump to "
- "flash. Otherwise QEMU will jump to DRAM");
+ "flash. Otherwise QEMU will jump to DRAM "
+ "or L2LIM depending on the msel value");
s->msel = 0;
object_property_add(obj, "msel", "uint32",
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (29 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 16:58 ` [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
` (2 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index eb767aa863..b9d0a6901a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -80,10 +80,10 @@ static const struct MemmapEntry {
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (30 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
@ 2020-06-19 16:58 ` Alistair Francis
2020-06-19 18:29 ` [PULL v2 00/32] riscv-to-apply queue no-reply
2020-06-22 15:01 ` Peter Maydell
33 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-19 16:58 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
It is enough to simply map the SiFive FU540 DDR memory controller
into the MMIO space using create_unimplemented_device(), to make
the upstream U-Boot v2020.07 DDR memory initialization codes happy.
Note we do not generate device tree fragment for the DDR memory
controller. Since the controller data in device tree consumes a
very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
U-Boot source), and it is only needed by U-Boot SPL but not any
operating system, we choose not to generate the fragment here.
This also means when testing with U-Boot SPL, the device tree has
to come from U-Boot SPL itself, but not the one generated by QEMU
on the fly. The memory has to be set to 8GiB to match the real
HiFive Unleashed board when invoking QEMU (-m 8G).
With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:
$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014
The above exception is expected because QSPI is unsupported yet.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-6-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 27dc35e0a3..aba4d0181f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -78,6 +78,7 @@ enum {
SIFIVE_U_UART1,
SIFIVE_U_GPIO,
SIFIVE_U_OTP,
+ SIFIVE_U_DMC,
SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
SIFIVE_U_GEM,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b9d0a6901a..7d051e7c92 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -82,6 +82,7 @@ static const struct MemmapEntry {
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
@@ -714,6 +715,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+
+ create_unimplemented_device("riscv.sifive.u.dmc",
+ memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
}
static Property sifive_u_soc_props[] = {
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PULL v2 00/32] riscv-to-apply queue
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (31 preceding siblings ...)
2020-06-19 16:58 ` [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
@ 2020-06-19 18:29 ` no-reply
2020-06-22 15:01 ` Peter Maydell
33 siblings, 0 replies; 38+ messages in thread
From: no-reply @ 2020-06-19 18:29 UTC (permalink / raw)
To: alistair.francis; +Cc: peter.maydell, alistair.francis, qemu-devel, alistair23
Patchew URL: https://patchew.org/QEMU/20200619165817.4144200-1-alistair.francis@wdc.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1
=== TEST SCRIPT END ===
GEN docs/interop/qemu-ga-ref.html
GEN docs/interop/qemu-ga-ref.txt
GEN docs/interop/qemu-ga-ref.7
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-keymap
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-storage-daemon
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-img
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-io
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-edid
LINK fsdev/virtfs-proxy-helper
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK scsi/qemu-pr-helper
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK qemu-bridge-helper
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
LINK virtiofsd
LINK vhost-user-input
LINK qemu-ga
AS pc-bios/optionrom/multiboot.o
AS pc-bios/optionrom/linuxboot.o
CC pc-bios/optionrom/linuxboot_dma.o
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
AS pc-bios/optionrom/kvmvapic.o
/usr/bin/ld/usr/bin/ld: : /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o)/usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o): warning: common of `
__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
AS pc-bios/optionrom/pvh.o
CC pc-bios/optionrom/pvh_main.o
---
CC x86_64-softmmu/gdbstub-xml.o
CC x86_64-softmmu/trace/generated-helpers.o
LINK x86_64-softmmu/qemu-system-x86_64
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
common.rc: line 50: test: check: binary operator expected
(printf '#define QEMU_PKGVERSION ""\n'; printf '#define QEMU_FULL_VERSION "5.0.50"\n'; ) > qemu-version.h.tmp
make -C /tmp/qemu-test/src/slirp BUILD_DIR="/tmp/qemu-test/build/slirp" PKG_CONFIG="pkg-config" CC="clang" AR="ar" LD="ld" RANLIB="ranlib" CFLAGS="-I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -I/tmp/qemu-test/src/tests -I/tmp/qemu-test/src/tests/qtest -g " LDFLAGS="-Wl,--warn-common -fsanitize=undefined -fsanitize=address -Wl,-z,relro -Wl,-z,now -pie -m64 -fstack-protector-strong"
---
clang -iquote /tmp/qemu-test/build/tests/qtest/libqos -iquote tests/qtest/libqos -iquote /tmp/qemu-test/src/tcg/i386 -isystem /tmp/qemu-test/src/linux-headers -isystem /tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include -iquote /tmp/qemu-test/src/disas/libvixl -I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -I/tmp/qemu-test/src/tests -I/tmp/qemu-test/src/tests/qtest -MMD -MP -MT tests/qtest/libqos/libqos.o -MF tests/qtest/libqos/libqos.d -g -c -o tests/qtest/libqos/libqos.o /tmp/qemu-test/src/tests/qtest/libqos/libqos.c
clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg/i386 -isystem /tmp/qemu-test/src/linux-headers -isystem /tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include -iquote /tmp/qemu-test/src/disas/libvixl -I/tmp/qemu-test/src/tests/fp -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE -I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source -I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64 -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80 -Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized -Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD -MP -MT genCases_common.o -MF ./genCases_common.d -g -c -o genCases_common.o /tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/genCases_common.c
clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg/i386 -isystem /tmp/qemu-test/src/linux-headers -isystem /tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include -iquote /tmp/qemu-test/src/disas/libvixl -I/tmp/qemu-test/src/tests/fp -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE -I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source -I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64 -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80 -Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized -Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD -MP -MT genCases_ui32.o -MF ./genCases_ui32.d -g -c -o genCases_ui32.o /tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/genCases_ui32.c
/tmp/qemu-test/src/tests/qht-bench.c:287:29: error: implicit conversion from 'unsigned long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-int-float-conversion]
*threshold = rate * UINT64_MAX;
~ ^~~~~~~~~~
/usr/include/stdint.h:130:23: note: expanded from macro 'UINT64_MAX'
---
18446744073709551615UL
^~~~~~~~~~~~~~~~~~~~~~
1 error generated.
make: *** [/tmp/qemu-test/src/rules.mak:69: tests/qht-bench.o] Error 1
make: *** Waiting for unfinished jobs....
clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg/i386 -isystem /tmp/qemu-test/src/linux-headers -isystem /tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include -iquote /tmp/qemu-test/src/disas/libvixl -I/tmp/qemu-test/src/tests/fp -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE -I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source -I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64 -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80 -Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized -Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD -MP -MT genCases_ui64.o -MF ./genCases_ui64.d -g -c -o genCases_ui64.o /tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/genCases_ui64.c
clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg/i386 -isystem /tmp/qemu-test/src/linux-headers -isystem /tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include -iquote /tmp/qemu-test/src/disas/libvixl -I/tmp/qemu-test/src/tests/fp -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include -I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE -I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source -I/usr/include/pixman-1 -Werror -fsanitize=undefined -fsanitize=address -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wno-initializer-overrides -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-string-plus-int -Wno-typedef-redefinition -Wno-tautological-type-limit-compare -fstack-protector-strong -I/usr/include/p11-kit-1 -DSTRUCT_IOVEC_DEFINED -I/usr/include/libpng16 -I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 -I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64 -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80 -Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized -Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD -MP -MT genCases_i32.o -MF ./genCases_i32.d -g -c -o genCases_i32.o /tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/genCases_i32.c
---
rm -f libtestfloat.a && ar rcs libtestfloat.a uint128_inline.o uint128.o fail.o functions_common.o functionInfos.o standardFunctionInfos.o random.o genCases_common.o genCases_ui32.o genCases_ui64.o genCases_i32.o genCases_i64.o genCases_f16.o genCases_f32.o genCases_f64.o genCases_extF80.o genCases_f128.o genCases_writeTestsTotal.o verCases_inline.o verCases_common.o verCases_writeFunctionName.o readHex.o writeHex.o writeCase_a_ui32.o writeCase_a_ui64.o writeCase_a_f16.o writeCase_ab_f16.o writeCase_abc_f16.o writeCase_a_f32.o writeCase_ab_f32.o writeCase_abc_f32.o writeCase_a_f64.o writeCase_ab_f64.o writeCase_abc_f64.o writeCase_a_extF80M.o writeCase_ab_extF80M.o writeCase_a_f128M.o writeCase_ab_f128M.o writeCase_abc_f128M.o writeCase_z_bool.o writeCase_z_ui32.o writeCase_z_ui64.o writeCase_z_f16.o writeCase_z_f32.o writeCase_z_f64.o writeCase_z_extF80M.o writeCase_z_f128M.o testLoops_common.o test_a_ui32_z_f16.o test_a_ui32_z_f32.o test_a_ui32_z_f64.o test_a_ui32_z_extF80.o test_a_ui32_z_f128.o test_a_ui64_z_f16.o test_a_ui64_z_f32.o test_a_ui64_z_f64.o test_a_ui64_z_extF80.o test_a_ui64_z_f128.o test_a_i32_z_f16.o test_a_i32_z_f32.o test_a_i32_z_f64.o test_a_i32_z_extF80.o test_a_i32_z_f128.o test_a_i64_z_f16.o test_a_i64_z_f32.o test_a_i64_z_f64.o test_a_i64_z_extF80.o test_a_i64_z_f128.o test_a_f16_z_ui32_rx.o test_a_f16_z_ui64_rx.o test_a_f16_z_i32_rx.o test_a_f16_z_i64_rx.o test_a_f16_z_ui32_x.o test_a_f16_z_ui64_x.o test_a_f16_z_i32_x.o test_a_f16_z_i64_x.o test_a_f16_z_f32.o test_a_f16_z_f64.o test_a_f16_z_extF80.o test_a_f16_z_f128.o test_az_f16.o test_az_f16_rx.o test_abz_f16.o test_abcz_f16.o test_ab_f16_z_bool.o test_a_f32_z_ui32_rx.o test_a_f32_z_ui64_rx.o test_a_f32_z_i32_rx.o test_a_f32_z_i64_rx.o test_a_f32_z_ui32_x.o test_a_f32_z_ui64_x.o test_a_f32_z_i32_x.o test_a_f32_z_i64_x.o test_a_f32_z_f16.o test_a_f32_z_f64.o test_a_f32_z_extF80.o test_a_f32_z_f128.o test_az_f32.o test_az_f32_rx.o test_abz_f32.o test_abcz_f32.o test_ab_f32_z_bool.o test_a_f64_z_ui32_rx.o test_a_f64_z_ui64_rx.o test_a_f64_z_i32_rx.o test_a_f64_z_i64_rx.o test_a_f64_z_ui32_x.o test_a_f64_z_ui64_x.o test_a_f64_z_i32_x.o test_a_f64_z_i64_x.o test_a_f64_z_f16.o test_a_f64_z_f32.o test_a_f64_z_extF80.o test_a_f64_z_f128.o test_az_f64.o test_az_f64_rx.o test_abz_f64.o test_abcz_f64.o test_ab_f64_z_bool.o test_a_extF80_z_ui32_rx.o test_a_extF80_z_ui64_rx.o test_a_extF80_z_i32_rx.o test_a_extF80_z_i64_rx.o test_a_extF80_z_ui32_x.o test_a_extF80_z_ui64_x.o test_a_extF80_z_i32_x.o test_a_extF80_z_i64_x.o test_a_extF80_z_f16.o test_a_extF80_z_f32.o test_a_extF80_z_f64.o test_a_extF80_z_f128.o test_az_extF80.o test_az_extF80_rx.o test_abz_extF80.o test_ab_extF80_z_bool.o test_a_f128_z_ui32_rx.o test_a_f128_z_ui64_rx.o test_a_f128_z_i32_rx.o test_a_f128_z_i64_rx.o test_a_f128_z_ui32_x.o test_a_f128_z_ui64_x.o test_a_f128_z_i32_x.o test_a_f128_z_i64_x.o test_a_f128_z_f16.o test_a_f128_z_f32.o test_a_f128_z_f64.o test_a_f128_z_extF80.o test_az_f128.o test_az_f128_rx.o test_abz_f128.o test_abcz_f128.o test_ab_f128_z_bool.o
rm -f libsoftfloat.a && ar rcs libsoftfloat.a s_eq128.o s_le128.o s_lt128.o s_shortShiftLeft128.o s_shortShiftRight128.o s_shortShiftRightJam64.o s_shortShiftRightJam64Extra.o s_shortShiftRightJam128.o s_shortShiftRightJam128Extra.o s_shiftRightJam32.o s_shiftRightJam64.o s_shiftRightJam64Extra.o s_shiftRightJam128.o s_shiftRightJam128Extra.o s_shiftRightJam256M.o s_countLeadingZeros8.o s_countLeadingZeros16.o s_countLeadingZeros32.o s_countLeadingZeros64.o s_add128.o s_add256M.o s_sub128.o s_sub256M.o s_mul64ByShifted32To128.o s_mul64To128.o s_mul128By32.o s_mul128To256M.o s_approxRecip_1Ks.o s_approxRecip32_1.o s_approxRecipSqrt_1Ks.o s_approxRecipSqrt32_1.o s_roundToUI32.o s_roundToUI64.o s_roundToI32.o s_roundToI64.o s_normSubnormalF16Sig.o s_roundPackToF16.o s_normRoundPackToF16.o s_addMagsF16.o s_subMagsF16.o s_mulAddF16.o s_normSubnormalF32Sig.o s_roundPackToF32.o s_normRoundPackToF32.o s_addMagsF32.o s_subMagsF32.o s_mulAddF32.o s_normSubnormalF64Sig.o s_roundPackToF64.o s_normRoundPackToF64.o s_addMagsF64.o s_subMagsF64.o s_mulAddF64.o s_normSubnormalExtF80Sig.o s_roundPackToExtF80.o s_normRoundPackToExtF80.o s_addMagsExtF80.o s_subMagsExtF80.o s_normSubnormalF128Sig.o s_roundPackToF128.o s_normRoundPackToF128.o s_addMagsF128.o s_subMagsF128.o s_mulAddF128.o softfloat_state.o ui32_to_f16.o ui32_to_f32.o ui32_to_f64.o ui32_to_extF80.o ui32_to_extF80M.o ui32_to_f128.o ui32_to_f128M.o ui64_to_f16.o ui64_to_f32.o ui64_to_f64.o ui64_to_extF80.o ui64_to_extF80M.o ui64_to_f128.o ui64_to_f128M.o i32_to_f16.o i32_to_f32.o i32_to_f64.o i32_to_extF80.o i32_to_extF80M.o i32_to_f128.o i32_to_f128M.o i64_to_f16.o i64_to_f32.o i64_to_f64.o i64_to_extF80.o i64_to_extF80M.o i64_to_f128.o i64_to_f128M.o f16_to_ui32.o f16_to_ui64.o f16_to_i32.o f16_to_i64.o f16_to_ui32_r_minMag.o f16_to_ui64_r_minMag.o f16_to_i32_r_minMag.o f16_to_i64_r_minMag.o f16_to_f32.o f16_to_f64.o f16_to_extF80.o f16_to_extF80M.o f16_to_f128.o f16_to_f128M.o f16_roundToInt.o f16_add.o f16_sub.o f16_mul.o f16_mulAdd.o f16_div.o f16_rem.o f16_sqrt.o f16_eq.o f16_le.o f16_lt.o f16_eq_signaling.o f16_le_quiet.o f16_lt_quiet.o f16_isSignalingNaN.o f32_to_ui32.o f32_to_ui64.o f32_to_i32.o f32_to_i64.o f32_to_ui32_r_minMag.o f32_to_ui64_r_minMag.o f32_to_i32_r_minMag.o f32_to_i64_r_minMag.o f32_to_f16.o f32_to_f64.o f32_to_extF80.o f32_to_extF80M.o f32_to_f128.o f32_to_f128M.o f32_roundToInt.o f32_add.o f32_sub.o f32_mul.o f32_mulAdd.o f32_div.o f32_rem.o f32_sqrt.o f32_eq.o f32_le.o f32_lt.o f32_eq_signaling.o f32_le_quiet.o f32_lt_quiet.o f32_isSignalingNaN.o f64_to_ui32.o f64_to_ui64.o f64_to_i32.o f64_to_i64.o f64_to_ui32_r_minMag.o f64_to_ui64_r_minMag.o f64_to_i32_r_minMag.o f64_to_i64_r_minMag.o f64_to_f16.o f64_to_f32.o f64_to_extF80.o f64_to_extF80M.o f64_to_f128.o f64_to_f128M.o f64_roundToInt.o f64_add.o f64_sub.o f64_mul.o f64_mulAdd.o f64_div.o f64_rem.o f64_sqrt.o f64_eq.o f64_le.o f64_lt.o f64_eq_signaling.o f64_le_quiet.o f64_lt_quiet.o f64_isSignalingNaN.o extF80_to_ui32.o extF80_to_ui64.o extF80_to_i32.o extF80_to_i64.o extF80_to_ui32_r_minMag.o extF80_to_ui64_r_minMag.o extF80_to_i32_r_minMag.o extF80_to_i64_r_minMag.o extF80_to_f16.o extF80_to_f32.o extF80_to_f64.o extF80_to_f128.o extF80_roundToInt.o extF80_add.o extF80_sub.o extF80_mul.o extF80_div.o extF80_rem.o extF80_sqrt.o extF80_eq.o extF80_le.o extF80_lt.o extF80_eq_signaling.o extF80_le_quiet.o extF80_lt_quiet.o extF80_isSignalingNaN.o extF80M_to_ui32.o extF80M_to_ui64.o extF80M_to_i32.o extF80M_to_i64.o extF80M_to_ui32_r_minMag.o extF80M_to_ui64_r_minMag.o extF80M_to_i32_r_minMag.o extF80M_to_i64_r_minMag.o extF80M_to_f16.o extF80M_to_f32.o extF80M_to_f64.o extF80M_to_f128M.o extF80M_roundToInt.o extF80M_add.o extF80M_sub.o extF80M_mul.o extF80M_div.o extF80M_rem.o extF80M_sqrt.o extF80M_eq.o extF80M_le.o extF80M_lt.o extF80M_eq_signaling.o extF80M_le_quiet.o extF80M_lt_quiet.o f128_to_ui32.o f128_to_ui64.o f128_to_i32.o f128_to_i64.o f128_to_ui32_r_minMag.o f128_to_ui64_r_minMag.o f128_to_i32_r_minMag.o f128_to_i64_r_minMag.o f128_to_f16.o f128_to_f32.o f128_to_extF80.o f128_to_f64.o f128_roundToInt.o f128_add.o f128_sub.o f128_mul.o f128_mulAdd.o f128_div.o f128_rem.o f128_sqrt.o f128_eq.o f128_le.o f128_lt.o f128_eq_signaling.o f128_le_quiet.o f128_lt_quiet.o f128_isSignalingNaN.o f128M_to_ui32.o f128M_to_ui64.o f128M_to_i32.o f128M_to_i64.o f128M_to_ui32_r_minMag.o f128M_to_ui64_r_minMag.o f128M_to_i32_r_minMag.o f128M_to_i64_r_minMag.o f128M_to_f16.o f128M_to_f32.o f128M_to_extF80M.o f128M_to_f64.o f128M_roundToInt.o f128M_add.o f128M_sub.o f128M_mul.o f128M_mulAdd.o f128M_div.o f128M_rem.o f128M_sqrt.o f128M_eq.o f128M_le.o f128M_lt.o f128M_eq_signaling.o f128M_le_quiet.o f128M_lt_quiet.o softfloat_raiseFlags.o s_f16UIToCommonNaN.o s_commonNaNToF16UI.o s_propagateNaNF16UI.o s_f32UIToCommonNaN.o s_commonNaNToF32UI.o s_propagateNaNF32UI.o s_f64UIToCommonNaN.o s_commonNaNToF64UI.o s_propagateNaNF64UI.o extF80M_isSignalingNaN.o s_extF80UIToCommonNaN.o s_commonNaNToExtF80UI.o s_propagateNaNExtF80UI.o f128M_isSignalingNaN.o s_f128UIToCommonNaN.o s_commonNaNToF128UI.o s_propagateNaNF128UI.o
clang++ -g -Wl,--warn-common -fsanitize=undefined -fsanitize=address -Wl,-z,relro -Wl,-z,now -pie -m64 -fstack-protector-strong -o fp-test fp-test.o slowfloat.o softfloat.o libtestfloat.a libsoftfloat.a /tmp/qemu-test/build/libqemuutil.a -lm -lz -lgthread-2.0 -pthread -lglib-2.0 -lnettle -lgnutls -lzstd -lrt
/usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o)
make[1]: Leaving directory '/tmp/qemu-test/build/tests/fp'
Traceback (most recent call last):
File "./tests/docker/docker.py", line 669, in <module>
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=1a1e627b37924de681c864acbda022c4', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=x86_64-softmmu', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-e1l3nubc/src/docker-src.2020-06-19-14.23.48.17611:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-debug']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=1a1e627b37924de681c864acbda022c4
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-e1l3nubc/src'
make: *** [docker-run-test-debug@fedora] Error 2
real 5m30.110s
user 0m7.995s
The full log is available at
http://patchew.org/logs/20200619165817.4144200-1-alistair.francis@wdc.com/testing.asan/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PULL v2 00/32] riscv-to-apply queue
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
` (32 preceding siblings ...)
2020-06-19 18:29 ` [PULL v2 00/32] riscv-to-apply queue no-reply
@ 2020-06-22 15:01 ` Peter Maydell
33 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2020-06-22 15:01 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, QEMU Developers
On Fri, 19 Jun 2020 at 18:07, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 4d285821c5055ed68a6f6b7693fd11a06a1aa426:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into staging (2020-06-19 11:44:03 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200619-3
>
> for you to fetch changes up to 3eaea6eb4e534f7b87c6eca808149bb671976800:
>
> hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-19 08:25:27 -0700)
>
> ----------------------------------------------------------------
> This is a range of patches for RISC-V.
>
> Some key points are:
> - Generalise the CPU init functions
> - Support the SiFive revB machine
> - Improvements to the Hypervisor implementation and error checking
> - Connect some OpenTitan devices
> - Changes to the sifive_u machine to support U-boot
>
> v2:
> - Fix missing realise assert
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
@ 2020-06-23 6:22 ` Bin Meng
2020-06-23 9:08 ` Markus Armbruster
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2020-06-23 6:22 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, Bin Meng, qemu-devel@nongnu.org Developers,
Alistair Francis
Hi Alistair,
On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have exactly the same
> codes for 32-bit and 64-bit base CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
> Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
I noticed that patches from other people than you have the
"Message-id" tags, but your patch [1] does not. Is this intentional?
(not sure why we need 2 "Message-id" tags here, with one has <> ?)
Just want to know what's the best practice here.
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
[1] https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg06208.html
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU
2020-06-23 6:22 ` Bin Meng
@ 2020-06-23 9:08 ` Markus Armbruster
2020-06-23 23:28 ` Alistair Francis
0 siblings, 1 reply; 38+ messages in thread
From: Markus Armbruster @ 2020-06-23 9:08 UTC (permalink / raw)
To: Bin Meng
Cc: Peter Maydell, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, Alistair Francis
Bin Meng <bmeng.cn@gmail.com> writes:
> Hi Alistair,
>
> On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
>>
>> From: Bin Meng <bin.meng@windriver.com>
>>
>> There is no need to have two functions that have exactly the same
>> codes for 32-bit and 64-bit base CPUs.
>>
>> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
>> Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
>
> I noticed that patches from other people than you have the
> "Message-id" tags, but your patch [1] does not. Is this intentional?
>
> (not sure why we need 2 "Message-id" tags here, with one has <> ?)
We don't. Looks like an accident.
> Just want to know what's the best practice here.
The Message-Id tag's purpose is connecting commits back to the mailing
list. Useful when you want to look up their review later.
To get them into git, maintainers should use git-am -m to apply
patches. I have
[am]
messageid = true
in my .gitconfig.
Maintainers may be tempted to use git-rebase or git-cherry-pick instead
for patches they already have in their local git (such as their own
patches). No good, because we don't get the Message-Id that way.
Patch submissions (as opposed to pull requests) generally do not have
Message-Id tags in commit messages.
Hope this helps!
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> target/riscv/cpu.c | 18 +++++-------------
>> 1 file changed, 5 insertions(+), 13 deletions(-)
>>
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg06208.html
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU
2020-06-23 9:08 ` Markus Armbruster
@ 2020-06-23 23:28 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2020-06-23 23:28 UTC (permalink / raw)
To: Markus Armbruster
Cc: Bin Meng, Peter Maydell, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Tue, Jun 23, 2020 at 2:08 AM Markus Armbruster <armbru@redhat.com> wrote:
>
> Bin Meng <bmeng.cn@gmail.com> writes:
>
> > Hi Alistair,
> >
> > On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> >>
> >> From: Bin Meng <bin.meng@windriver.com>
> >>
> >> There is no need to have two functions that have exactly the same
> >> codes for 32-bit and 64-bit base CPUs.
> >>
> >> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> >> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> >> Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
> >> Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
> >
> > I noticed that patches from other people than you have the
> > "Message-id" tags, but your patch [1] does not. Is this intentional?
> >
> > (not sure why we need 2 "Message-id" tags here, with one has <> ?)
>
> We don't. Looks like an accident.
Yeah, that must have been an accident.
>
> > Just want to know what's the best practice here.
>
> The Message-Id tag's purpose is connecting commits back to the mailing
> list. Useful when you want to look up their review later.
>
> To get them into git, maintainers should use git-am -m to apply
> patches. I have
>
> [am]
> messageid = true
>
> in my .gitconfig.
>
> Maintainers may be tempted to use git-rebase or git-cherry-pick instead
> for patches they already have in their local git (such as their own
> patches). No good, because we don't get the Message-Id that way.
Ah, thanks for clarifying that. I was never sure. I'll be sure to not
rebase or cherry-pick my own patches in the future.
Alistair
>
> Patch submissions (as opposed to pull requests) generally do not have
> Message-Id tags in commit messages.
>
> Hope this helps!
>
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> ---
> >> target/riscv/cpu.c | 18 +++++-------------
> >> 1 file changed, 5 insertions(+), 13 deletions(-)
> >>
> >
> > [1] https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg06208.html
> >
> > Regards,
> > Bin
>
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2020-06-23 23:39 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
2020-06-19 16:57 ` [PULL v2 02/32] sifive_e: Support the revB machine Alistair Francis
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
2020-06-23 6:22 ` Bin Meng
2020-06-23 9:08 ` Markus Armbruster
2020-06-23 23:28 ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
2020-06-19 16:57 ` [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-19 16:57 ` [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-19 16:57 ` [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-19 16:57 ` [PULL v2 10/32] target/riscv: Implement checks for hfence Alistair Francis
2020-06-19 16:57 ` [PULL v2 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
2020-06-19 16:57 ` [PULL v2 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-19 16:57 ` [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-06-19 16:57 ` [PULL v2 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-06-19 16:58 ` [PULL v2 15/32] riscv/opentitan: Connect the UART device Alistair Francis
2020-06-19 16:58 ` [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-06-19 16:58 ` [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
2020-06-19 16:58 ` [PULL v2 18/32] hw/riscv: opentitan: " Alistair Francis
2020-06-19 16:58 ` [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
2020-06-19 16:58 ` [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
2020-06-19 16:58 ` [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
2020-06-19 16:58 ` [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
2020-06-19 16:58 ` [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
2020-06-19 16:58 ` [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
2020-06-19 16:58 ` [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
2020-06-19 16:58 ` [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
2020-06-19 16:58 ` [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
2020-06-19 16:58 ` [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
2020-06-19 16:58 ` [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
2020-06-19 16:58 ` [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
2020-06-19 18:29 ` [PULL v2 00/32] riscv-to-apply queue no-reply
2020-06-22 15:01 ` Peter Maydell
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