From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Date: Fri, 4 Sep 2020 14:53:45 +0300 [thread overview] Message-ID: <20200904115354.25336-10-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200904115354.25336-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Move the downstream facing port dotclock check into a new function (intel_dp_mode_valid_downstream()) so that we have a nice future place where we can collect other related checks. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++---------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8699c001969d..1dea017dc505 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1381,6 +1381,7 @@ struct intel_dp { /* Downstream facing port caps */ struct { + int max_dotclock; u8 max_bpc; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8f4aee35c203..6f55e15136b0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -247,29 +247,6 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) return max_link_clock * max_lanes; } -static int -intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) -{ - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int max_dotclk = dev_priv->max_dotclk_freq; - int ds_max_dotclk; - - int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; - - if (type != DP_DS_PORT_TYPE_VGA) - return max_dotclk; - - ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd, - intel_dp->downstream_ports); - - if (ds_max_dotclk != 0) - max_dotclk = min(max_dotclk, ds_max_dotclk); - - return max_dotclk; -} - static int cnl_max_source_rate(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -634,6 +611,19 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, return hdisplay == 4096 && !HAS_DDI(dev_priv); } +static enum drm_mode_status +intel_dp_mode_valid_downstream(struct intel_connector *connector, + int target_clock) +{ + struct intel_dp *intel_dp = intel_attached_dp(connector); + + if (intel_dp->dfp.max_dotclock && + target_clock > intel_dp->dfp.max_dotclock) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -644,15 +634,14 @@ intel_dp_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->dev); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; - int max_dotclk; + int max_dotclk = dev_priv->max_dotclk_freq; u16 dsc_max_output_bpp = 0; u8 dsc_slice_count = 0; + enum drm_mode_status status; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; - max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); - if (intel_dp_is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -708,6 +697,10 @@ intel_dp_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) return MODE_H_ILLEGAL; + status = intel_dp_mode_valid_downstream(intel_connector, target_clock); + if (status != MODE_OK) + return status; + return intel_mode_valid_max_plane_size(dev_priv, mode); } @@ -6073,9 +6066,14 @@ intel_dp_set_edid(struct intel_dp *intel_dp) drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports, edid); - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] DFP max bpc %d\n", + intel_dp->dfp.max_dotclock = + drm_dp_downstream_max_dotclock(intel_dp->dpcd, + intel_dp->downstream_ports); + + drm_dbg_kms(&i915->drm, + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d\n", connector->base.base.id, connector->base.name, - intel_dp->dfp.max_bpc); + intel_dp->dfp.max_bpc, intel_dp->dfp.max_dotclock); if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); @@ -6100,6 +6098,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->edid_quirks = 0; intel_dp->dfp.max_bpc = 0; + intel_dp->dfp.max_dotclock = 0; } static int -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Date: Fri, 4 Sep 2020 14:53:45 +0300 [thread overview] Message-ID: <20200904115354.25336-10-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200904115354.25336-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Move the downstream facing port dotclock check into a new function (intel_dp_mode_valid_downstream()) so that we have a nice future place where we can collect other related checks. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++---------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8699c001969d..1dea017dc505 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1381,6 +1381,7 @@ struct intel_dp { /* Downstream facing port caps */ struct { + int max_dotclock; u8 max_bpc; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8f4aee35c203..6f55e15136b0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -247,29 +247,6 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) return max_link_clock * max_lanes; } -static int -intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) -{ - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int max_dotclk = dev_priv->max_dotclk_freq; - int ds_max_dotclk; - - int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; - - if (type != DP_DS_PORT_TYPE_VGA) - return max_dotclk; - - ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd, - intel_dp->downstream_ports); - - if (ds_max_dotclk != 0) - max_dotclk = min(max_dotclk, ds_max_dotclk); - - return max_dotclk; -} - static int cnl_max_source_rate(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -634,6 +611,19 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, return hdisplay == 4096 && !HAS_DDI(dev_priv); } +static enum drm_mode_status +intel_dp_mode_valid_downstream(struct intel_connector *connector, + int target_clock) +{ + struct intel_dp *intel_dp = intel_attached_dp(connector); + + if (intel_dp->dfp.max_dotclock && + target_clock > intel_dp->dfp.max_dotclock) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -644,15 +634,14 @@ intel_dp_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->dev); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; - int max_dotclk; + int max_dotclk = dev_priv->max_dotclk_freq; u16 dsc_max_output_bpp = 0; u8 dsc_slice_count = 0; + enum drm_mode_status status; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; - max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); - if (intel_dp_is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -708,6 +697,10 @@ intel_dp_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) return MODE_H_ILLEGAL; + status = intel_dp_mode_valid_downstream(intel_connector, target_clock); + if (status != MODE_OK) + return status; + return intel_mode_valid_max_plane_size(dev_priv, mode); } @@ -6073,9 +6066,14 @@ intel_dp_set_edid(struct intel_dp *intel_dp) drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports, edid); - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] DFP max bpc %d\n", + intel_dp->dfp.max_dotclock = + drm_dp_downstream_max_dotclock(intel_dp->dpcd, + intel_dp->downstream_ports); + + drm_dbg_kms(&i915->drm, + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d\n", connector->base.base.id, connector->base.name, - intel_dp->dfp.max_bpc); + intel_dp->dfp.max_bpc, intel_dp->dfp.max_dotclock); if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); @@ -6100,6 +6098,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->edid_quirks = 0; intel_dp->dfp.max_bpc = 0; + intel_dp->dfp.max_dotclock = 0; } static int -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-09-04 11:54 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-04 11:53 [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:30 ` Lyude Paul 2020-09-08 17:30 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:32 ` Lyude Paul 2020-09-08 17:32 ` [Intel-gfx] " Lyude Paul 2020-09-08 17:51 ` Lyude Paul 2020-09-08 17:51 ` [Intel-gfx] " Lyude Paul 2020-09-10 14:46 ` Ville Syrjälä 2020-09-10 14:46 ` [Intel-gfx] " Ville Syrjälä 2020-09-10 19:40 ` Lyude Paul 2020-09-10 19:40 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:56 ` Lyude Paul 2020-09-08 17:56 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` Ville Syrjala [this message] 2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:04 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-08 18:04 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-17 12:46 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä 2020-09-17 12:46 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä 2020-09-08 18:08 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-08 18:08 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-10 13:55 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä 2020-09-10 13:55 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä 2020-09-10 19:40 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-10 19:40 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-04 11:53 ` [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:11 ` Lyude Paul 2020-09-08 18:11 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:13 ` Lyude Paul 2020-09-08 18:13 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:15 ` Lyude Paul 2020-09-08 18:15 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork 2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-09-04 20:09 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul 2020-09-04 20:09 ` [Intel-gfx] " Lyude Paul 2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork 2020-09-08 18:34 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul 2020-09-08 18:34 ` [Intel-gfx] " Lyude Paul [not found] ` <fa772231854424f2b4edc69e23b0edd924695e6c.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2020-09-17 16:11 ` Ville Syrjälä 2020-09-17 16:11 ` [Intel-gfx] " Ville Syrjälä 2020-09-17 16:11 ` Ville Syrjälä
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