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From: Lyude Paul <lyude@redhat.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	 dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
Date: Tue, 08 Sep 2020 14:15:44 -0400	[thread overview]
Message-ID: <e93d42d137ce8572244ecba8662167930399decc.camel@redhat.com> (raw)
In-Reply-To: <20200904115354.25336-18-ville.syrjala@linux.intel.com>

On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add helpers to determine whether the DFP supports
> YCbCr 4:2:0 passthrough or YCbCr 4:4:4->4:2:0 conversion.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 44 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |  8 ++++++
>  2 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 0d5e9bcf11d0..dc68e10aa1fd 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -808,6 +808,50 @@ int drm_dp_downstream_max_bpc(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
>  
> +bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				       const u8 port_cap[4])
> +{
> +	if (!drm_dp_is_branch(dpcd))
> +		return false;
> +
> +	if (dpcd[DP_DPCD_REV] < 0x13)
> +		return false;
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_DP:
> +		return true;
> +	case DP_DS_PORT_TYPE_HDMI:
> +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> +			return false;
> +
> +		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
> +	default:
> +		return false;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);

Forgot the kdocs again

> +
> +bool drm_dp_downstream_444_to_420_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +					     const u8 port_cap[4])
> +{
> +	if (!drm_dp_is_branch(dpcd))
> +		return false;
> +
> +	if (dpcd[DP_DPCD_REV] < 0x13)
> +		return false;
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_HDMI:
> +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> +			return false;
> +
> +		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
> +	default:
> +		return false;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
> +
>  /**
>   * drm_dp_downstream_mode() - return a mode for downstream facing port
>   * @dpcd: DisplayPort configuration data
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index fbba4a0f7366..c9f2851904d0 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -407,6 +407,10 @@ struct drm_device;
>  # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
>  /* offset 3 for HDMI */
>  # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
> +# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
> +# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
> +# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
> +# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
>  
>  #define DP_MAX_DOWNSTREAM_PORTS		    0x10
>  
> @@ -1663,6 +1667,10 @@ int drm_dp_downstream_min_tmds_clock(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  			      const u8 port_cap[4],
>  			      const struct edid *edid);
> +bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				       const u8 port_cap[4]);
> +bool drm_dp_downstream_444_to_420_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +					     const u8 port_cap[4]);
>  struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
>  						const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  						const u8 port_cap[4]);
-- 
Cheers,
	Lyude Paul (she/her)
	Software Engineer at Red Hat

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Lyude Paul <lyude@redhat.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	 dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
Date: Tue, 08 Sep 2020 14:15:44 -0400	[thread overview]
Message-ID: <e93d42d137ce8572244ecba8662167930399decc.camel@redhat.com> (raw)
In-Reply-To: <20200904115354.25336-18-ville.syrjala@linux.intel.com>

On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add helpers to determine whether the DFP supports
> YCbCr 4:2:0 passthrough or YCbCr 4:4:4->4:2:0 conversion.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 44 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |  8 ++++++
>  2 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 0d5e9bcf11d0..dc68e10aa1fd 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -808,6 +808,50 @@ int drm_dp_downstream_max_bpc(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
>  
> +bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				       const u8 port_cap[4])
> +{
> +	if (!drm_dp_is_branch(dpcd))
> +		return false;
> +
> +	if (dpcd[DP_DPCD_REV] < 0x13)
> +		return false;
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_DP:
> +		return true;
> +	case DP_DS_PORT_TYPE_HDMI:
> +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> +			return false;
> +
> +		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
> +	default:
> +		return false;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);

Forgot the kdocs again

> +
> +bool drm_dp_downstream_444_to_420_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +					     const u8 port_cap[4])
> +{
> +	if (!drm_dp_is_branch(dpcd))
> +		return false;
> +
> +	if (dpcd[DP_DPCD_REV] < 0x13)
> +		return false;
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_HDMI:
> +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> +			return false;
> +
> +		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
> +	default:
> +		return false;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
> +
>  /**
>   * drm_dp_downstream_mode() - return a mode for downstream facing port
>   * @dpcd: DisplayPort configuration data
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index fbba4a0f7366..c9f2851904d0 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -407,6 +407,10 @@ struct drm_device;
>  # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
>  /* offset 3 for HDMI */
>  # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
> +# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
> +# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
> +# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
> +# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
>  
>  #define DP_MAX_DOWNSTREAM_PORTS		    0x10
>  
> @@ -1663,6 +1667,10 @@ int drm_dp_downstream_min_tmds_clock(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  			      const u8 port_cap[4],
>  			      const struct edid *edid);
> +bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				       const u8 port_cap[4]);
> +bool drm_dp_downstream_444_to_420_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +					     const u8 port_cap[4]);
>  struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
>  						const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  						const u8 port_cap[4]);
-- 
Cheers,
	Lyude Paul (she/her)
	Software Engineer at Red Hat

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-09-08 18:15 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 11:53 [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 17:30   ` Lyude Paul
2020-09-08 17:30     ` [Intel-gfx] " Lyude Paul
2020-09-04 11:53 ` [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 17:32   ` Lyude Paul
2020-09-08 17:32     ` [Intel-gfx] " Lyude Paul
2020-09-08 17:51   ` Lyude Paul
2020-09-08 17:51     ` [Intel-gfx] " Lyude Paul
2020-09-10 14:46     ` Ville Syrjälä
2020-09-10 14:46       ` [Intel-gfx] " Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-10 19:40         ` [Intel-gfx] " Lyude Paul
2020-09-04 11:53 ` [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 17:56   ` Lyude Paul
2020-09-08 17:56     ` [Intel-gfx] " Lyude Paul
2020-09-04 11:53 ` [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 18:04   ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul
2020-09-08 18:04     ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul
2020-09-17 12:46     ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä
2020-09-17 12:46       ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä
2020-09-08 18:08   ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul
2020-09-08 18:08     ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul
2020-09-10 13:55     ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä
2020-09-10 13:55       ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä
2020-09-10 19:40       ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul
2020-09-10 19:40         ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul
2020-09-04 11:53 ` [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 18:11   ` Lyude Paul
2020-09-08 18:11     ` [Intel-gfx] " Lyude Paul
2020-09-04 11:53 ` [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 18:13   ` Lyude Paul
2020-09-08 18:13     ` [Intel-gfx] " Lyude Paul
2020-09-04 11:53 ` [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 11:53 ` [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-08 18:15   ` Lyude Paul [this message]
2020-09-08 18:15     ` Lyude Paul
2020-09-04 11:53 ` [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala
2020-09-04 11:53   ` [Intel-gfx] " Ville Syrjala
2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-04 20:09 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-04 20:09   ` [Intel-gfx] " Lyude Paul
2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-08 18:34 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-08 18:34   ` [Intel-gfx] " Lyude Paul
     [not found]   ` <fa772231854424f2b4edc69e23b0edd924695e6c.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2020-09-17 16:11     ` Ville Syrjälä
2020-09-17 16:11       ` [Intel-gfx] " Ville Syrjälä
2020-09-17 16:11       ` Ville Syrjälä

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