From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Date: Fri, 4 Sep 2020 14:53:52 +0300 [thread overview] Message-ID: <20200904115354.25336-17-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200904115354.25336-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Account for the TMDS clock limits declared by the DFP/DP++ dongle when determining what color depth we're going to use. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 63 ++++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ++++++++++-------- drivers/gpu/drm/i915/display/intel_hdmi.h | 2 + 3 files changed, 88 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2798621a466a..c7aa66d2eb90 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1977,18 +1977,69 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } -static int intel_dp_compute_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config) +static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; +} + +static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, int bpc) +{ + int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; + + if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) + clock /= 2; + + return clock; +} + +static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, int bpc) +{ + int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); + + if (intel_dp->dfp.min_tmds_clock && + tmds_clock < intel_dp->dfp.min_tmds_clock) + return false; + + if (intel_dp->dfp.max_tmds_clock && + tmds_clock > intel_dp->dfp.max_tmds_clock) + return false; + + return true; +} + +static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int bpc) +{ + bool has_hdmi_sink = intel_dp->has_hdmi_sink; + + return intel_hdmi_deep_color_possible(crtc_state, bpc, has_hdmi_sink) && + intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); +} + +static int intel_dp_max_bpp(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct intel_connector *intel_connector = intel_dp->attached_connector; - int bpp; + int bpp, bpc; - bpp = pipe_config->pipe_bpp; + bpc = crtc_state->pipe_bpp / 3; if (intel_dp->dfp.max_bpc) - bpp = min(bpp, 3 * intel_dp->dfp.max_bpc); + bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); + if (intel_dp->dfp.min_tmds_clock) { + for (; bpc >= 10; bpc -= 2) { + if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) + break; + } + } + + bpp = bpc * 3; if (intel_dp_is_edp(intel_dp)) { /* Get bpp from vbt only for panels that dont have bpp in edid */ if (intel_connector->base.display_info.bpc == 0 && @@ -2310,7 +2361,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.max_lane_count = intel_dp_max_lane_count(intel_dp); limits.min_bpp = intel_dp_min_bpp(pipe_config); - limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); + limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); if (intel_dp_is_edp(intel_dp)) { /* diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 9bf664bfd7de..929ae22b0a49 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2277,35 +2277,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector, return intel_mode_valid_max_plane_size(dev_priv, mode); } -static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, - int bpc) +bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc, bool has_hdmi_sink) { - struct drm_i915_private *dev_priv = - to_i915(crtc_state->uapi.crtc->dev); struct drm_atomic_state *state = crtc_state->uapi.state; struct drm_connector_state *connector_state; struct drm_connector *connector; - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; int i; - if (HAS_GMCH(dev_priv)) - return false; - - if (bpc == 10 && INTEL_GEN(dev_priv) < 11) - return false; - if (crtc_state->pipe_bpp < bpc * 3) return false; - if (!crtc_state->has_hdmi_sink) - return false; - - /* - * HDMI deep color affects the clocks, so it's only possible - * when not cloning with other encoder types. - */ - if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) + if (!has_hdmi_sink) return false; for_each_new_connector_in_state(state, connector, connector_state, i) { @@ -2333,6 +2316,30 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, } } + return true; +} + +static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc) +{ + struct drm_i915_private *dev_priv = + to_i915(crtc_state->uapi.crtc->dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + if (HAS_GMCH(dev_priv)) + return false; + + if (bpc == 10 && INTEL_GEN(dev_priv) < 11) + return false; + + /* + * HDMI deep color affects the clocks, so it's only possible + * when not cloning with other encoder types. + */ + if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) + return false; + /* Display Wa_1405510057:icl,ehl */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && bpc == 10 && IS_GEN(dev_priv, 11) && @@ -2340,7 +2347,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, adjusted_mode->crtc_hblank_start) % 8 == 2) return false; - return true; + return intel_hdmi_deep_color_possible(crtc_state, bpc, + crtc_state->has_hdmi_sink); } static int diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 5b348dcab77a..c382930a992e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -48,5 +48,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, union hdmi_infoframe *frame); bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); +bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc, bool has_hdmi_sink); #endif /* __INTEL_HDMI_H__ */ -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Date: Fri, 4 Sep 2020 14:53:52 +0300 [thread overview] Message-ID: <20200904115354.25336-17-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200904115354.25336-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Account for the TMDS clock limits declared by the DFP/DP++ dongle when determining what color depth we're going to use. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 63 ++++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ++++++++++-------- drivers/gpu/drm/i915/display/intel_hdmi.h | 2 + 3 files changed, 88 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2798621a466a..c7aa66d2eb90 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1977,18 +1977,69 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } -static int intel_dp_compute_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config) +static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; +} + +static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, int bpc) +{ + int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; + + if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) + clock /= 2; + + return clock; +} + +static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, int bpc) +{ + int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); + + if (intel_dp->dfp.min_tmds_clock && + tmds_clock < intel_dp->dfp.min_tmds_clock) + return false; + + if (intel_dp->dfp.max_tmds_clock && + tmds_clock > intel_dp->dfp.max_tmds_clock) + return false; + + return true; +} + +static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int bpc) +{ + bool has_hdmi_sink = intel_dp->has_hdmi_sink; + + return intel_hdmi_deep_color_possible(crtc_state, bpc, has_hdmi_sink) && + intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); +} + +static int intel_dp_max_bpp(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct intel_connector *intel_connector = intel_dp->attached_connector; - int bpp; + int bpp, bpc; - bpp = pipe_config->pipe_bpp; + bpc = crtc_state->pipe_bpp / 3; if (intel_dp->dfp.max_bpc) - bpp = min(bpp, 3 * intel_dp->dfp.max_bpc); + bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); + if (intel_dp->dfp.min_tmds_clock) { + for (; bpc >= 10; bpc -= 2) { + if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) + break; + } + } + + bpp = bpc * 3; if (intel_dp_is_edp(intel_dp)) { /* Get bpp from vbt only for panels that dont have bpp in edid */ if (intel_connector->base.display_info.bpc == 0 && @@ -2310,7 +2361,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.max_lane_count = intel_dp_max_lane_count(intel_dp); limits.min_bpp = intel_dp_min_bpp(pipe_config); - limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); + limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); if (intel_dp_is_edp(intel_dp)) { /* diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 9bf664bfd7de..929ae22b0a49 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2277,35 +2277,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector, return intel_mode_valid_max_plane_size(dev_priv, mode); } -static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, - int bpc) +bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc, bool has_hdmi_sink) { - struct drm_i915_private *dev_priv = - to_i915(crtc_state->uapi.crtc->dev); struct drm_atomic_state *state = crtc_state->uapi.state; struct drm_connector_state *connector_state; struct drm_connector *connector; - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; int i; - if (HAS_GMCH(dev_priv)) - return false; - - if (bpc == 10 && INTEL_GEN(dev_priv) < 11) - return false; - if (crtc_state->pipe_bpp < bpc * 3) return false; - if (!crtc_state->has_hdmi_sink) - return false; - - /* - * HDMI deep color affects the clocks, so it's only possible - * when not cloning with other encoder types. - */ - if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) + if (!has_hdmi_sink) return false; for_each_new_connector_in_state(state, connector, connector_state, i) { @@ -2333,6 +2316,30 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, } } + return true; +} + +static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc) +{ + struct drm_i915_private *dev_priv = + to_i915(crtc_state->uapi.crtc->dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + if (HAS_GMCH(dev_priv)) + return false; + + if (bpc == 10 && INTEL_GEN(dev_priv) < 11) + return false; + + /* + * HDMI deep color affects the clocks, so it's only possible + * when not cloning with other encoder types. + */ + if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) + return false; + /* Display Wa_1405510057:icl,ehl */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && bpc == 10 && IS_GEN(dev_priv, 11) && @@ -2340,7 +2347,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, adjusted_mode->crtc_hblank_start) % 8 == 2) return false; - return true; + return intel_hdmi_deep_color_possible(crtc_state, bpc, + crtc_state->has_hdmi_sink); } static int diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 5b348dcab77a..c382930a992e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -48,5 +48,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, union hdmi_infoframe *frame); bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); +bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, + int bpc, bool has_hdmi_sink); #endif /* __INTEL_HDMI_H__ */ -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-09-04 11:54 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-04 11:53 [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:30 ` Lyude Paul 2020-09-08 17:30 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:32 ` Lyude Paul 2020-09-08 17:32 ` [Intel-gfx] " Lyude Paul 2020-09-08 17:51 ` Lyude Paul 2020-09-08 17:51 ` [Intel-gfx] " Lyude Paul 2020-09-10 14:46 ` Ville Syrjälä 2020-09-10 14:46 ` [Intel-gfx] " Ville Syrjälä 2020-09-10 19:40 ` Lyude Paul 2020-09-10 19:40 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 17:56 ` Lyude Paul 2020-09-08 17:56 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:04 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-08 18:04 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-17 12:46 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä 2020-09-17 12:46 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä 2020-09-08 18:08 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-08 18:08 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-10 13:55 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjälä 2020-09-10 13:55 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjälä 2020-09-10 19:40 ` [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Lyude Paul 2020-09-10 19:40 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Lyude Paul 2020-09-04 11:53 ` [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:11 ` Lyude Paul 2020-09-08 18:11 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:13 ` Lyude Paul 2020-09-08 18:13 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 11:53 ` Ville Syrjala [this message] 2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala 2020-09-04 11:53 ` [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-08 18:15 ` Lyude Paul 2020-09-08 18:15 ` [Intel-gfx] " Lyude Paul 2020-09-04 11:53 ` [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala 2020-09-04 11:53 ` [Intel-gfx] " Ville Syrjala 2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork 2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-09-04 20:09 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul 2020-09-04 20:09 ` [Intel-gfx] " Lyude Paul 2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork 2020-09-08 18:34 ` [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul 2020-09-08 18:34 ` [Intel-gfx] " Lyude Paul [not found] ` <fa772231854424f2b4edc69e23b0edd924695e6c.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2020-09-17 16:11 ` Ville Syrjälä 2020-09-17 16:11 ` [Intel-gfx] " Ville Syrjälä 2020-09-17 16:11 ` Ville Syrjälä
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