From: Pratyush Yadav <p.yadav@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org> Cc: Pratyush Yadav <p.yadav@ti.com>, Sekhar Nori <nsekhar@ti.com>, Boris Brezillon <boris.brezillon@collabora.com> Subject: [PATCH v14 02/15] mtd: spi-nor: add spi_nor_controller_ops_{read_reg,write_reg,erase}() Date: Thu, 1 Oct 2020 00:27:19 +0530 [thread overview] Message-ID: <20200930185732.6201-3-p.yadav@ti.com> (raw) In-Reply-To: <20200930185732.6201-1-p.yadav@ti.com> They are thin wrappers around nor->controller_ops->{read_reg,write_reg,erase}(). In a future commit DTR support will be added. These ops can not be supported by the controller_ops hooks and these helpers will make it easier to reject those calls. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/mtd/spi-nor/core.c | 87 +++++++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4d0f8d165544..7a3bf460a2fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -82,6 +82,23 @@ static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) return spi_mem_exec_op(nor->spimem, op); } +static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, + u8 *buf, size_t len) +{ + return nor->controller_ops->read_reg(nor, opcode, buf, len); +} + +static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, + const u8 *buf, size_t len) +{ + return nor->controller_ops->write_reg(nor, opcode, buf, len); +} + +static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) +{ + return nor->controller_ops->erase(nor, offs); +} + /** * spi_nor_spimem_read_data() - read data from flash's memory region via * spi-mem @@ -229,8 +246,8 @@ int spi_nor_write_enable(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, + NULL, 0); } if (ret) @@ -258,8 +275,8 @@ int spi_nor_write_disable(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, + NULL, 0); } if (ret) @@ -289,8 +306,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, - sr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, + 1); } if (ret) @@ -320,8 +337,8 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR, - fsr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, + 1); } if (ret) @@ -352,7 +369,8 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, + 1); } if (ret) @@ -385,10 +403,10 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, - enable ? SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, + enable ? SPINOR_OP_EN4B : + SPINOR_OP_EX4B, + NULL, 0); } if (ret) @@ -421,8 +439,8 @@ static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, - nor->bouncebuf, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, + nor->bouncebuf, 1); } if (ret) @@ -453,8 +471,8 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, - nor->bouncebuf, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR, + nor->bouncebuf, 1); } if (ret) @@ -484,8 +502,8 @@ int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, - sr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, + 1); } if (ret) @@ -529,8 +547,8 @@ static void spi_nor_clear_sr(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, + NULL, 0); } if (ret) @@ -593,8 +611,8 @@ static void spi_nor_clear_fsr(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, + NULL, 0); } if (ret) @@ -737,8 +755,8 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - sr, len); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, + len); } if (ret) { @@ -939,8 +957,8 @@ static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, - sr2, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); } if (ret) { @@ -973,8 +991,8 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, - sr2, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, + 1); } if (ret) @@ -1004,8 +1022,9 @@ static int spi_nor_erase_chip(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, + SPINOR_OP_CHIP_ERASE, + NULL, 0); } if (ret) @@ -1146,7 +1165,7 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) return spi_mem_exec_op(nor->spimem, &op); } else if (nor->controller_ops->erase) { - return nor->controller_ops->erase(nor, addr); + return spi_nor_controller_ops_erase(nor, addr); } /* @@ -1158,8 +1177,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) addr >>= 8; } - return nor->controller_ops->write_reg(nor, nor->erase_opcode, - nor->bouncebuf, nor->addr_width); + return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, + nor->bouncebuf, nor->addr_width); } /** -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <p.yadav@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org> Cc: Boris Brezillon <boris.brezillon@collabora.com>, Sekhar Nori <nsekhar@ti.com>, Pratyush Yadav <p.yadav@ti.com> Subject: [PATCH v14 02/15] mtd: spi-nor: add spi_nor_controller_ops_{read_reg, write_reg, erase}() Date: Thu, 1 Oct 2020 00:27:19 +0530 [thread overview] Message-ID: <20200930185732.6201-3-p.yadav@ti.com> (raw) In-Reply-To: <20200930185732.6201-1-p.yadav@ti.com> They are thin wrappers around nor->controller_ops->{read_reg,write_reg,erase}(). In a future commit DTR support will be added. These ops can not be supported by the controller_ops hooks and these helpers will make it easier to reject those calls. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/mtd/spi-nor/core.c | 87 +++++++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4d0f8d165544..7a3bf460a2fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -82,6 +82,23 @@ static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) return spi_mem_exec_op(nor->spimem, op); } +static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, + u8 *buf, size_t len) +{ + return nor->controller_ops->read_reg(nor, opcode, buf, len); +} + +static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, + const u8 *buf, size_t len) +{ + return nor->controller_ops->write_reg(nor, opcode, buf, len); +} + +static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) +{ + return nor->controller_ops->erase(nor, offs); +} + /** * spi_nor_spimem_read_data() - read data from flash's memory region via * spi-mem @@ -229,8 +246,8 @@ int spi_nor_write_enable(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, + NULL, 0); } if (ret) @@ -258,8 +275,8 @@ int spi_nor_write_disable(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, + NULL, 0); } if (ret) @@ -289,8 +306,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, - sr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, + 1); } if (ret) @@ -320,8 +337,8 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR, - fsr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, + 1); } if (ret) @@ -352,7 +369,8 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, + 1); } if (ret) @@ -385,10 +403,10 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, - enable ? SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, + enable ? SPINOR_OP_EN4B : + SPINOR_OP_EX4B, + NULL, 0); } if (ret) @@ -421,8 +439,8 @@ static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, - nor->bouncebuf, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, + nor->bouncebuf, 1); } if (ret) @@ -453,8 +471,8 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, - nor->bouncebuf, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR, + nor->bouncebuf, 1); } if (ret) @@ -484,8 +502,8 @@ int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, - sr, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, + 1); } if (ret) @@ -529,8 +547,8 @@ static void spi_nor_clear_sr(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, + NULL, 0); } if (ret) @@ -593,8 +611,8 @@ static void spi_nor_clear_fsr(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, + NULL, 0); } if (ret) @@ -737,8 +755,8 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - sr, len); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, + len); } if (ret) { @@ -939,8 +957,8 @@ static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, - sr2, 1); + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); } if (ret) { @@ -973,8 +991,8 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, - sr2, 1); + ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, + 1); } if (ret) @@ -1004,8 +1022,9 @@ static int spi_nor_erase_chip(struct spi_nor *nor) ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, - NULL, 0); + ret = spi_nor_controller_ops_write_reg(nor, + SPINOR_OP_CHIP_ERASE, + NULL, 0); } if (ret) @@ -1146,7 +1165,7 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) return spi_mem_exec_op(nor->spimem, &op); } else if (nor->controller_ops->erase) { - return nor->controller_ops->erase(nor, addr); + return spi_nor_controller_ops_erase(nor, addr); } /* @@ -1158,8 +1177,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) addr >>= 8; } - return nor->controller_ops->write_reg(nor, nor->erase_opcode, - nor->bouncebuf, nor->addr_width); + return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, + nor->bouncebuf, nor->addr_width); } /** -- 2.28.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-09-30 18:57 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-30 18:57 [PATCH v14 00/15] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-09-30 18:57 ` [PATCH v14 01/15] mtd: spi-nor: core: use EOPNOTSUPP instead of ENOTSUPP Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 7:19 ` Tudor.Ambarus 2020-10-01 7:19 ` Tudor.Ambarus 2020-10-01 7:34 ` Pratyush Yadav 2020-10-01 7:34 ` Pratyush Yadav 2020-10-01 7:50 ` Miquel Raynal 2020-10-01 7:50 ` Miquel Raynal 2020-10-01 8:18 ` Tudor.Ambarus 2020-10-01 8:18 ` Tudor.Ambarus 2020-10-01 10:50 ` Vignesh Raghavendra 2020-10-01 10:50 ` Vignesh Raghavendra 2020-09-30 18:57 ` Pratyush Yadav [this message] 2020-09-30 18:57 ` [PATCH v14 02/15] mtd: spi-nor: add spi_nor_controller_ops_{read_reg, write_reg, erase}() Pratyush Yadav 2020-10-01 7:21 ` [PATCH v14 02/15] mtd: spi-nor: add spi_nor_controller_ops_{read_reg,write_reg,erase}() Tudor.Ambarus 2020-10-01 7:21 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 03/15] mtd: spi-nor: add support for DTR protocol Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 7:46 ` Tudor.Ambarus 2020-10-01 7:46 ` Tudor.Ambarus 2020-10-01 8:37 ` Pratyush Yadav 2020-10-01 8:37 ` Pratyush Yadav 2020-10-01 8:49 ` Tudor.Ambarus 2020-10-01 8:49 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 04/15] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-09-30 18:57 ` [PATCH v14 05/15] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 7:49 ` Tudor.Ambarus 2020-10-01 7:49 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 06/15] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 7:50 ` Tudor.Ambarus 2020-10-01 7:50 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 07/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 7:52 ` Tudor.Ambarus 2020-10-01 7:52 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 08/15] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:09 ` Tudor.Ambarus 2020-10-01 8:09 ` Tudor.Ambarus 2020-10-01 8:42 ` Pratyush Yadav 2020-10-01 8:42 ` Pratyush Yadav 2020-09-30 18:57 ` [PATCH v14 09/15] mtd: spi-nor: Introduce SNOR_F_IO_MODE_EN_VOLATILE Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-09-30 18:57 ` [PATCH v14 10/15] mtd: spi-nor: Parse SFDP SCCR Map Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:20 ` Tudor.Ambarus 2020-10-01 8:20 ` Tudor.Ambarus 2020-10-01 11:56 ` Pratyush Yadav 2020-10-01 11:56 ` Pratyush Yadav 2020-09-30 18:57 ` [PATCH v14 11/15] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:21 ` Tudor.Ambarus 2020-10-01 8:21 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 12/15] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:23 ` Tudor.Ambarus 2020-10-01 8:23 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 13/15] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:26 ` Tudor.Ambarus 2020-10-01 8:26 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 14/15] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:35 ` Tudor.Ambarus 2020-10-01 8:35 ` Tudor.Ambarus 2020-10-01 8:40 ` Pratyush Yadav 2020-10-01 8:40 ` Pratyush Yadav 2020-10-01 8:50 ` Tudor.Ambarus 2020-10-01 8:50 ` Tudor.Ambarus 2020-09-30 18:57 ` [PATCH v14 15/15] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav 2020-09-30 18:57 ` Pratyush Yadav 2020-10-01 8:38 ` Tudor.Ambarus 2020-10-01 8:38 ` Tudor.Ambarus 2020-10-01 19:43 ` Pratyush Yadav 2020-10-01 19:43 ` Pratyush Yadav
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