All of lore.kernel.org
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com,
	LIU Zhiwei <zhiwei_liu@c-sky.com>,
	wxy194768@alibaba-inc.com
Subject: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
Date: Fri,  9 Apr 2021 15:48:57 +0800	[thread overview]
Message-ID: <20210409074857.166082-12-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>

When a vectored interrupt is selected and serviced, the hardware will
automatically clear the corresponding pending bit in edge-triggered mode.
This may lead to a lower priviledge interrupt pending forever.

Therefore when interrupts return, pull a pending interrupt to service.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/op_helper.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1eddcb94de..42563b22ba 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -24,6 +24,10 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
 /* Exceptions processing helpers */
 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
                                           uint32_t exception, uintptr_t pc)
@@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
         mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
         env->mstatus = mstatus;
+
+        if (riscv_clic_is_clic_mode(env)) {
+            CPUState *cs = env_cpu(env);
+            target_ulong spil = get_field(env->scause, SCAUSE_SPIL);
+            env->mintstatus = set_field(env->mintstatus, MINTSTATUS_SIL, spil);
+            env->scause = set_field(env->scause, SCAUSE_SPIE, 0);
+            env->scause = set_field(env->scause, SCAUSE_SPP, PRV_U);
+            qemu_mutex_lock_iothread();
+            riscv_clic_get_next_interrupt(env->clic, cs->cpu_index);
+            qemu_mutex_unlock_iothread();
+        }
     }
 
     riscv_cpu_set_mode(env, prev_priv);
@@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
         riscv_cpu_set_virt_enabled(env, prev_virt);
     }
 
+    if (riscv_clic_is_clic_mode(env)) {
+        CPUState *cs = env_cpu(env);
+        target_ulong mpil = get_field(env->mcause, MCAUSE_MPIL);
+        env->mintstatus = set_field(env->mintstatus, MINTSTATUS_MIL, mpil);
+        env->mcause = set_field(env->mcause, MCAUSE_MPIE, 0);
+        env->mcause = set_field(env->mcause, MCAUSE_MPP, PRV_U);
+        qemu_mutex_lock_iothread();
+        riscv_clic_get_next_interrupt(env->clic, cs->cpu_index);
+        qemu_mutex_unlock_iothread();
+    }
     return retpc;
 }
 
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
Date: Fri,  9 Apr 2021 15:48:57 +0800	[thread overview]
Message-ID: <20210409074857.166082-12-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>

When a vectored interrupt is selected and serviced, the hardware will
automatically clear the corresponding pending bit in edge-triggered mode.
This may lead to a lower priviledge interrupt pending forever.

Therefore when interrupts return, pull a pending interrupt to service.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/op_helper.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1eddcb94de..42563b22ba 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -24,6 +24,10 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
 /* Exceptions processing helpers */
 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
                                           uint32_t exception, uintptr_t pc)
@@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
         mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
         env->mstatus = mstatus;
+
+        if (riscv_clic_is_clic_mode(env)) {
+            CPUState *cs = env_cpu(env);
+            target_ulong spil = get_field(env->scause, SCAUSE_SPIL);
+            env->mintstatus = set_field(env->mintstatus, MINTSTATUS_SIL, spil);
+            env->scause = set_field(env->scause, SCAUSE_SPIE, 0);
+            env->scause = set_field(env->scause, SCAUSE_SPP, PRV_U);
+            qemu_mutex_lock_iothread();
+            riscv_clic_get_next_interrupt(env->clic, cs->cpu_index);
+            qemu_mutex_unlock_iothread();
+        }
     }
 
     riscv_cpu_set_mode(env, prev_priv);
@@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
         riscv_cpu_set_virt_enabled(env, prev_virt);
     }
 
+    if (riscv_clic_is_clic_mode(env)) {
+        CPUState *cs = env_cpu(env);
+        target_ulong mpil = get_field(env->mcause, MCAUSE_MPIL);
+        env->mintstatus = set_field(env->mintstatus, MINTSTATUS_MIL, mpil);
+        env->mcause = set_field(env->mcause, MCAUSE_MPIE, 0);
+        env->mcause = set_field(env->mcause, MCAUSE_MPP, PRV_U);
+        qemu_mutex_lock_iothread();
+        riscv_clic_get_next_interrupt(env->clic, cs->cpu_index);
+        qemu_mutex_unlock_iothread();
+    }
     return retpc;
 }
 
-- 
2.25.1



  parent reply	other threads:[~2021-04-09  7:55 UTC|newest]

Thread overview: 162+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09  7:48 ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:23   ` Alistair Francis
2021-04-19 23:23     ` Alistair Francis
2021-04-20  0:49     ` LIU Zhiwei
2021-04-20  0:49       ` LIU Zhiwei
2021-07-01  8:45       ` Frank Chang
2021-07-01  8:45         ` Frank Chang
2021-07-01  9:38         ` LIU Zhiwei
2021-07-01  9:38           ` LIU Zhiwei
2021-07-02  5:38         ` Alistair Francis
2021-07-02  5:38           ` Alistair Francis
2021-07-02  6:09           ` LIU Zhiwei
2021-07-02  6:09             ` LIU Zhiwei
2021-07-02  7:16             ` Alistair Francis
2021-07-02  7:16               ` Alistair Francis
2021-09-28  8:10               ` Frank Chang
2021-09-28  8:10                 ` Frank Chang
2021-09-29  3:55                 ` Alistair Francis
2021-09-29  3:55                   ` Alistair Francis
2021-04-09  7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 17:23   ` Frank Chang
2021-06-26 17:23     ` Frank Chang
2021-06-27  8:23     ` Frank Chang
2021-06-27  8:23       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:25   ` Alistair Francis
2021-04-19 23:25     ` Alistair Francis
2021-04-20  0:57     ` LIU Zhiwei
2021-04-20  0:57       ` LIU Zhiwei
2021-04-22  0:16       ` Alistair Francis
2021-04-22  0:16         ` Alistair Francis
2021-06-13 10:10   ` Frank Chang
2021-06-13 10:10     ` Frank Chang
2021-06-16  2:56     ` LIU Zhiwei
2021-06-16  2:56       ` LIU Zhiwei
2021-06-26 12:56       ` Frank Chang
2021-06-26 12:56         ` Frank Chang
2021-06-28  7:15         ` LIU Zhiwei
2021-06-28  7:15           ` LIU Zhiwei
2021-06-28  7:23           ` Frank Chang
2021-06-28  7:23             ` Frank Chang
2021-06-28  7:39             ` LIU Zhiwei
2021-06-28  7:39               ` LIU Zhiwei
2021-06-28  7:49               ` Frank Chang
2021-06-28  7:49                 ` Frank Chang
2021-06-28  8:01                 ` LIU Zhiwei
2021-06-28  8:01                   ` LIU Zhiwei
2021-06-28  8:07                   ` Frank Chang
2021-06-28  8:07                     ` Frank Chang
2021-06-28  8:11                     ` LIU Zhiwei
2021-06-28  8:11                       ` LIU Zhiwei
2021-06-28  8:19                       ` Frank Chang
2021-06-28  8:19                         ` Frank Chang
2021-06-28  8:43                         ` LIU Zhiwei
2021-06-28  8:43                           ` LIU Zhiwei
2021-06-28  9:11                           ` Frank Chang
2021-06-28  9:11                             ` Frank Chang
2021-06-26 15:03   ` Frank Chang
2021-06-26 15:03     ` Frank Chang
2021-06-26 15:26     ` Frank Chang
2021-06-26 15:26       ` Frank Chang
2021-06-29  2:52       ` LIU Zhiwei
2021-06-29  2:52         ` LIU Zhiwei
2021-06-29  2:43     ` LIU Zhiwei
2021-06-29  2:43       ` LIU Zhiwei
2021-06-30  5:37       ` Frank Chang
2021-06-30  5:37         ` Frank Chang
2021-06-26 15:20   ` Frank Chang
2021-06-26 15:20     ` Frank Chang
2021-06-29  2:50     ` LIU Zhiwei
2021-06-29  2:50       ` LIU Zhiwei
2021-06-26 17:15   ` Frank Chang
2021-06-26 17:15     ` Frank Chang
2021-06-26 17:19     ` Frank Chang
2021-06-26 17:19       ` Frank Chang
2021-06-28 10:16   ` Frank Chang
2021-06-28 10:16     ` Frank Chang
2021-06-28 12:56     ` LIU Zhiwei
2021-06-28 12:56       ` LIU Zhiwei
2021-06-28 14:30       ` Frank Chang
2021-06-28 14:30         ` Frank Chang
2021-06-28 21:36         ` LIU Zhiwei
2021-06-28 21:36           ` LIU Zhiwei
2021-06-28 10:24   ` Frank Chang
2021-06-28 10:24     ` Frank Chang
2021-06-28 10:48     ` LIU Zhiwei
2021-06-28 10:48       ` LIU Zhiwei
2021-07-13  6:53   ` Frank Chang
2021-07-13  6:53     ` Frank Chang
2021-07-13  6:57     ` Frank Chang
2021-07-13  6:57       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:50   ` Frank Chang
2021-06-27  6:50     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:45   ` Frank Chang
2021-06-27  6:45     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:59   ` Frank Chang
2021-06-27  8:59     ` Frank Chang
2021-07-10 15:04   ` Frank Chang
2021-07-10 15:04     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:33   ` Frank Chang
2021-06-27  8:33     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-11  8:15   ` Frank Chang
2021-06-11  8:15     ` Frank Chang
2021-06-11  8:30     ` LIU Zhiwei
2021-06-11  8:30       ` LIU Zhiwei
2021-06-11  8:42       ` Frank Chang
2021-06-11  8:42         ` Frank Chang
2021-06-11  8:56         ` LIU Zhiwei
2021-06-11  8:56           ` LIU Zhiwei
2021-06-11  9:07           ` Frank Chang
2021-06-11  9:07             ` Frank Chang
2021-06-11  9:26             ` LIU Zhiwei
2021-06-11  9:26               ` LIU Zhiwei
2021-06-15  7:45             ` Alistair Francis
2021-06-15  7:45               ` Alistair Francis
2021-06-27 10:07   ` Frank Chang
2021-06-27 10:07     ` Frank Chang
2021-07-10 14:59   ` Frank Chang
2021-07-10 14:59     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 15:31   ` Frank Chang
2021-06-26 15:31     ` Frank Chang
2021-06-29  2:54     ` LIU Zhiwei
2021-06-29  2:54       ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 15:39   ` Frank Chang
2021-06-27 15:39     ` Frank Chang
2021-04-09  7:48 ` LIU Zhiwei [this message]
2021-04-09  7:48   ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-06-27 12:08   ` Frank Chang
2021-06-27 12:08     ` Frank Chang
2021-07-13  7:15   ` Frank Chang
2021-07-13  7:15     ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30   ` Alistair Francis
2021-04-20  1:44   ` LIU Zhiwei
2021-04-20  1:44     ` LIU Zhiwei
2021-04-20  6:26     ` Alistair Francis
2021-04-20  6:26       ` Alistair Francis
2021-04-20  7:20       ` LIU Zhiwei
2021-04-20  7:20         ` LIU Zhiwei
2021-04-22  0:21         ` Alistair Francis
2021-04-22  0:21           ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55   ` Frank Chang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210409074857.166082-12-zhiwei_liu@c-sky.com \
    --to=zhiwei_liu@c-sky.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=wxy194768@alibaba-inc.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.