From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Frank Chang <frank.chang@sifive.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wxy194768@alibaba-inc.com, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus Date: Fri, 2 Jul 2021 17:16:54 +1000 [thread overview] Message-ID: <CAKmqyKOb9FP-UKkdBmr7dEKxWLv8x=J=3Rz=w8csRpWf8vh2xA@mail.gmail.com> (raw) In-Reply-To: <3e7f6ec6-21a0-9a21-8126-68ea8c2fbf15@c-sky.com> On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > On 2021/7/2 下午1:38, Alistair Francis wrote: > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang <frank.chang@sifive.com> wrote: > >> LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月20日 週二 上午8:49寫道: > >>> > >>> On 2021/4/20 上午7:23, Alistair Francis wrote: > >>>> On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >>>>> CSR mintstatus holds the active interrupt level for each supported > >>>>> privilege mode. sintstatus, and user, uintstatus, provide restricted > >>>>> views of mintstatus. > >>>>> > >>>>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > >>>>> --- > >>>>> target/riscv/cpu.h | 2 ++ > >>>>> target/riscv/cpu_bits.h | 11 +++++++++++ > >>>>> target/riscv/csr.c | 26 ++++++++++++++++++++++++++ > >>>>> 3 files changed, 39 insertions(+) > >>>>> > >>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >>>>> index 0a33d387ba..1a44ca62c7 100644 > >>>>> --- a/target/riscv/cpu.h > >>>>> +++ b/target/riscv/cpu.h > >>>>> @@ -159,6 +159,7 @@ struct CPURISCVState { > >>>>> target_ulong mip; > >>>>> > >>>>> uint32_t miclaim; > >>>>> + uint32_t mintstatus; /* clic-spec */ > >>>>> > >>>>> target_ulong mie; > >>>>> target_ulong mideleg; > >>>>> @@ -243,6 +244,7 @@ struct CPURISCVState { > >>>>> > >>>>> /* Fields from here on are preserved across CPU reset. */ > >>>>> QEMUTimer *timer; /* Internal timer */ > >>>>> + void *clic; /* clic interrupt controller */ > >>>> This should be the CLIC type. > >>> OK. > >>> > >>> Actually there are many versions of CLIC in my branch as different > >>> devices. But it is better to use CLIC type for the upstream version. > >> > >> Hi Alistair and Zhiwei, > >> > >> Replacing void *clic with RISCVCLICState *clic may create a circular loop > >> because CPURISCVState is also referenced in riscv_clic.h. > >> > >> However, I would like to ask what is the best approach to add > >> the reference of CLIC device in CPURISCVState struct? > >> > >> There may be different kinds of CLIC devices. > >> AFAK, there was another RFC patchset trying to add void *eclic > >> for Nuclei processor into CPURISCVState struct: > >> https://patchwork.kernel.org/project/qemu-devel/patch/20210507081654.11056-2-wangjunqiang@iscas.ac.cn/ > >> > >> Is it okay to add the device reference directly into CPURISCVState struct like that, > >> or we should create some abstraction for these CLIC devices? > >> (However, I'm not sure how big the differences are for these CLIC devices...) > > I would prefer to not have the CLIC in the struct at all. > > > > Why is the CLIC required from the CPU? > > In my opinion, the tight coupled interrupt controller, like NVIC in > ARM, is much different from other devices. > CPU harts need to communicate with it through many ways. Agreed. The difference with RISC-V is that we already have multiple tightly coupled interrupt controllers. We have the PLIC, CLIC, eCLIC and AIA, not to mention possible vendor controllers. Do we really need a CPU struct entry for every single one? I would like to try and keep all of that logic outside of the CPU state. It might not be possible (at least without being a mess) in which case that's fine, but it's at least worth considering. > > We can store the CLIC instance in the struct CPURISCVState or a global > variable. Is that any other way? We could split the device. So for example the CSRs and other parts that relate to the CPU could be in the CPU while the register mappings and GPIO lines could be it's own device. Another option is to use GPIO lines to indicate the status, but for anything too complex that will be messy. > > > I'm guessing we at least need it for CLIC CSR accesses. Could we > > handle that in the CPU and avoid needing a reference to the CLIC? > CSR access is one case. Other cases are: > > 1. When process an interrupt and decide ISP address, we need to know > current interrupt is vectored or not. > > 2. When interrupt returned, we need to choose another interrupt to > serve, so that it will not miss any interrupt. Thanks! Alistair > > Thanks, > Zhiwei > > > > Alistair > > > >> Thanks, > >> Frank Chang > >> > >>> > >>>>> }; > >>>>> > >>>>> OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, > >>>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > >>>>> index caf4599207..c4ce6ec3d9 100644 > >>>>> --- a/target/riscv/cpu_bits.h > >>>>> +++ b/target/riscv/cpu_bits.h > >>>>> @@ -165,6 +165,7 @@ > >>>>> #define CSR_MCAUSE 0x342 > >>>>> #define CSR_MTVAL 0x343 > >>>>> #define CSR_MIP 0x344 > >>>>> +#define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ > >>>>> > >>>>> /* Legacy Machine Trap Handling (priv v1.9.1) */ > >>>>> #define CSR_MBADADDR 0x343 > >>>>> @@ -183,6 +184,7 @@ > >>>>> #define CSR_SCAUSE 0x142 > >>>>> #define CSR_STVAL 0x143 > >>>>> #define CSR_SIP 0x144 > >>>>> +#define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ > >>>>> > >>>>> /* Legacy Supervisor Trap Handling (priv v1.9.1) */ > >>>>> #define CSR_SBADADDR 0x143 > >>>>> @@ -585,6 +587,15 @@ > >>>>> #define SIP_STIP MIP_STIP > >>>>> #define SIP_SEIP MIP_SEIP > >>>>> > >>>>> +/* mintstatus */ > >>>>> +#define MINTSTATUS_MIL 0xff000000 /* mil[7:0] */ > >>>>> +#define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >>>>> +#define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > >>>>> + > >>>>> +/* sintstatus */ > >>>>> +#define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >>>>> +#define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > >>>> The bit fields in the comments are out of date. > >>> I didn't notice it. Fix it in next version. > >>> > >>> Thanks. > >>> > >>> Zhiwei > >>> > >>>> Alistair > >>>> > >>>>> + > >>>>> /* MIE masks */ > >>>>> #define MIE_SEIE (1 << IRQ_S_EXT) > >>>>> #define MIE_UEIE (1 << IRQ_U_EXT) > >>>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c > >>>>> index d2585395bf..320b18ab60 100644 > >>>>> --- a/target/riscv/csr.c > >>>>> +++ b/target/riscv/csr.c > >>>>> @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno) > >>>>> { > >>>>> return -!riscv_feature(env, RISCV_FEATURE_PMP); > >>>>> } > >>>>> + > >>>>> +static int clic(CPURISCVState *env, int csrno) > >>>>> +{ > >>>>> + return !!env->clic; > >>>>> +} > >>>>> + > >>>>> #endif > >>>>> > >>>>> /* User Floating-Point CSRs */ > >>>>> @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, > >>>>> return 0; > >>>>> } > >>>>> > >>>>> +static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> +{ > >>>>> + *val = env->mintstatus; > >>>>> + return 0; > >>>>> +} > >>>>> + > >>>>> /* Supervisor Trap Setup */ > >>>>> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> { > >>>>> @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, > >>>>> return ret; > >>>>> } > >>>>> > >>>>> +static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> +{ > >>>>> + target_ulong mask = SINTSTATUS_SIL | SINTSTATUS_UIL; > >>>>> + *val = env->mintstatus & mask; > >>>>> + return 0; > >>>>> +} > >>>>> + > >>>>> /* Supervisor Protection and Translation */ > >>>>> static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> { > >>>>> @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > >>>>> [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, > >>>>> [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, > >>>>> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, > >>>>> + > >>>>> + /* Machine Mode Core Level Interrupt Controller */ > >>>>> + [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, > >>>>> + > >>>>> + /* Supervisor Mode Core Level Interrupt Controller */ > >>>>> + [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus }, > >>>>> + > >>>>> #endif /* !CONFIG_USER_ONLY */ > >>>>> }; > >>>>> -- > >>>>> 2.25.1 > >>>>> > >>>>>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wxy194768@alibaba-inc.com Subject: Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus Date: Fri, 2 Jul 2021 17:16:54 +1000 [thread overview] Message-ID: <CAKmqyKOb9FP-UKkdBmr7dEKxWLv8x=J=3Rz=w8csRpWf8vh2xA@mail.gmail.com> (raw) In-Reply-To: <3e7f6ec6-21a0-9a21-8126-68ea8c2fbf15@c-sky.com> On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > On 2021/7/2 下午1:38, Alistair Francis wrote: > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang <frank.chang@sifive.com> wrote: > >> LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月20日 週二 上午8:49寫道: > >>> > >>> On 2021/4/20 上午7:23, Alistair Francis wrote: > >>>> On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >>>>> CSR mintstatus holds the active interrupt level for each supported > >>>>> privilege mode. sintstatus, and user, uintstatus, provide restricted > >>>>> views of mintstatus. > >>>>> > >>>>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > >>>>> --- > >>>>> target/riscv/cpu.h | 2 ++ > >>>>> target/riscv/cpu_bits.h | 11 +++++++++++ > >>>>> target/riscv/csr.c | 26 ++++++++++++++++++++++++++ > >>>>> 3 files changed, 39 insertions(+) > >>>>> > >>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >>>>> index 0a33d387ba..1a44ca62c7 100644 > >>>>> --- a/target/riscv/cpu.h > >>>>> +++ b/target/riscv/cpu.h > >>>>> @@ -159,6 +159,7 @@ struct CPURISCVState { > >>>>> target_ulong mip; > >>>>> > >>>>> uint32_t miclaim; > >>>>> + uint32_t mintstatus; /* clic-spec */ > >>>>> > >>>>> target_ulong mie; > >>>>> target_ulong mideleg; > >>>>> @@ -243,6 +244,7 @@ struct CPURISCVState { > >>>>> > >>>>> /* Fields from here on are preserved across CPU reset. */ > >>>>> QEMUTimer *timer; /* Internal timer */ > >>>>> + void *clic; /* clic interrupt controller */ > >>>> This should be the CLIC type. > >>> OK. > >>> > >>> Actually there are many versions of CLIC in my branch as different > >>> devices. But it is better to use CLIC type for the upstream version. > >> > >> Hi Alistair and Zhiwei, > >> > >> Replacing void *clic with RISCVCLICState *clic may create a circular loop > >> because CPURISCVState is also referenced in riscv_clic.h. > >> > >> However, I would like to ask what is the best approach to add > >> the reference of CLIC device in CPURISCVState struct? > >> > >> There may be different kinds of CLIC devices. > >> AFAK, there was another RFC patchset trying to add void *eclic > >> for Nuclei processor into CPURISCVState struct: > >> https://patchwork.kernel.org/project/qemu-devel/patch/20210507081654.11056-2-wangjunqiang@iscas.ac.cn/ > >> > >> Is it okay to add the device reference directly into CPURISCVState struct like that, > >> or we should create some abstraction for these CLIC devices? > >> (However, I'm not sure how big the differences are for these CLIC devices...) > > I would prefer to not have the CLIC in the struct at all. > > > > Why is the CLIC required from the CPU? > > In my opinion, the tight coupled interrupt controller, like NVIC in > ARM, is much different from other devices. > CPU harts need to communicate with it through many ways. Agreed. The difference with RISC-V is that we already have multiple tightly coupled interrupt controllers. We have the PLIC, CLIC, eCLIC and AIA, not to mention possible vendor controllers. Do we really need a CPU struct entry for every single one? I would like to try and keep all of that logic outside of the CPU state. It might not be possible (at least without being a mess) in which case that's fine, but it's at least worth considering. > > We can store the CLIC instance in the struct CPURISCVState or a global > variable. Is that any other way? We could split the device. So for example the CSRs and other parts that relate to the CPU could be in the CPU while the register mappings and GPIO lines could be it's own device. Another option is to use GPIO lines to indicate the status, but for anything too complex that will be messy. > > > I'm guessing we at least need it for CLIC CSR accesses. Could we > > handle that in the CPU and avoid needing a reference to the CLIC? > CSR access is one case. Other cases are: > > 1. When process an interrupt and decide ISP address, we need to know > current interrupt is vectored or not. > > 2. When interrupt returned, we need to choose another interrupt to > serve, so that it will not miss any interrupt. Thanks! Alistair > > Thanks, > Zhiwei > > > > Alistair > > > >> Thanks, > >> Frank Chang > >> > >>> > >>>>> }; > >>>>> > >>>>> OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, > >>>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > >>>>> index caf4599207..c4ce6ec3d9 100644 > >>>>> --- a/target/riscv/cpu_bits.h > >>>>> +++ b/target/riscv/cpu_bits.h > >>>>> @@ -165,6 +165,7 @@ > >>>>> #define CSR_MCAUSE 0x342 > >>>>> #define CSR_MTVAL 0x343 > >>>>> #define CSR_MIP 0x344 > >>>>> +#define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ > >>>>> > >>>>> /* Legacy Machine Trap Handling (priv v1.9.1) */ > >>>>> #define CSR_MBADADDR 0x343 > >>>>> @@ -183,6 +184,7 @@ > >>>>> #define CSR_SCAUSE 0x142 > >>>>> #define CSR_STVAL 0x143 > >>>>> #define CSR_SIP 0x144 > >>>>> +#define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ > >>>>> > >>>>> /* Legacy Supervisor Trap Handling (priv v1.9.1) */ > >>>>> #define CSR_SBADADDR 0x143 > >>>>> @@ -585,6 +587,15 @@ > >>>>> #define SIP_STIP MIP_STIP > >>>>> #define SIP_SEIP MIP_SEIP > >>>>> > >>>>> +/* mintstatus */ > >>>>> +#define MINTSTATUS_MIL 0xff000000 /* mil[7:0] */ > >>>>> +#define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >>>>> +#define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > >>>>> + > >>>>> +/* sintstatus */ > >>>>> +#define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >>>>> +#define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > >>>> The bit fields in the comments are out of date. > >>> I didn't notice it. Fix it in next version. > >>> > >>> Thanks. > >>> > >>> Zhiwei > >>> > >>>> Alistair > >>>> > >>>>> + > >>>>> /* MIE masks */ > >>>>> #define MIE_SEIE (1 << IRQ_S_EXT) > >>>>> #define MIE_UEIE (1 << IRQ_U_EXT) > >>>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c > >>>>> index d2585395bf..320b18ab60 100644 > >>>>> --- a/target/riscv/csr.c > >>>>> +++ b/target/riscv/csr.c > >>>>> @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno) > >>>>> { > >>>>> return -!riscv_feature(env, RISCV_FEATURE_PMP); > >>>>> } > >>>>> + > >>>>> +static int clic(CPURISCVState *env, int csrno) > >>>>> +{ > >>>>> + return !!env->clic; > >>>>> +} > >>>>> + > >>>>> #endif > >>>>> > >>>>> /* User Floating-Point CSRs */ > >>>>> @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, > >>>>> return 0; > >>>>> } > >>>>> > >>>>> +static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> +{ > >>>>> + *val = env->mintstatus; > >>>>> + return 0; > >>>>> +} > >>>>> + > >>>>> /* Supervisor Trap Setup */ > >>>>> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> { > >>>>> @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, > >>>>> return ret; > >>>>> } > >>>>> > >>>>> +static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> +{ > >>>>> + target_ulong mask = SINTSTATUS_SIL | SINTSTATUS_UIL; > >>>>> + *val = env->mintstatus & mask; > >>>>> + return 0; > >>>>> +} > >>>>> + > >>>>> /* Supervisor Protection and Translation */ > >>>>> static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) > >>>>> { > >>>>> @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > >>>>> [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, > >>>>> [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, > >>>>> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, > >>>>> + > >>>>> + /* Machine Mode Core Level Interrupt Controller */ > >>>>> + [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, > >>>>> + > >>>>> + /* Supervisor Mode Core Level Interrupt Controller */ > >>>>> + [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus }, > >>>>> + > >>>>> #endif /* !CONFIG_USER_ONLY */ > >>>>> }; > >>>>> -- > >>>>> 2.25.1 > >>>>> > >>>>>
next prev parent reply other threads:[~2021-07-02 7:18 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-09 7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:23 ` Alistair Francis 2021-04-19 23:23 ` Alistair Francis 2021-04-20 0:49 ` LIU Zhiwei 2021-04-20 0:49 ` LIU Zhiwei 2021-07-01 8:45 ` Frank Chang 2021-07-01 8:45 ` Frank Chang 2021-07-01 9:38 ` LIU Zhiwei 2021-07-01 9:38 ` LIU Zhiwei 2021-07-02 5:38 ` Alistair Francis 2021-07-02 5:38 ` Alistair Francis 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 7:16 ` Alistair Francis [this message] 2021-07-02 7:16 ` Alistair Francis 2021-09-28 8:10 ` Frank Chang 2021-09-28 8:10 ` Frank Chang 2021-09-29 3:55 ` Alistair Francis 2021-09-29 3:55 ` Alistair Francis 2021-04-09 7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 17:23 ` Frank Chang 2021-06-26 17:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:25 ` Alistair Francis 2021-04-19 23:25 ` Alistair Francis 2021-04-20 0:57 ` LIU Zhiwei 2021-04-20 0:57 ` LIU Zhiwei 2021-04-22 0:16 ` Alistair Francis 2021-04-22 0:16 ` Alistair Francis 2021-06-13 10:10 ` Frank Chang 2021-06-13 10:10 ` Frank Chang 2021-06-16 2:56 ` LIU Zhiwei 2021-06-16 2:56 ` LIU Zhiwei 2021-06-26 12:56 ` Frank Chang 2021-06-26 12:56 ` Frank Chang 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:49 ` Frank Chang 2021-06-28 7:49 ` Frank Chang 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 9:11 ` Frank Chang 2021-06-28 9:11 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-30 5:37 ` Frank Chang 2021-06-30 5:37 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-29 2:50 ` LIU Zhiwei 2021-06-29 2:50 ` LIU Zhiwei 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 14:30 ` Frank Chang 2021-06-28 14:30 ` Frank Chang 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:48 ` LIU Zhiwei 2021-06-28 10:48 ` LIU Zhiwei 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:50 ` Frank Chang 2021-06-27 6:50 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:45 ` Frank Chang 2021-06-27 6:45 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:59 ` Frank Chang 2021-06-27 8:59 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:33 ` Frank Chang 2021-06-27 8:33 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:26 ` LIU Zhiwei 2021-06-11 9:26 ` LIU Zhiwei 2021-06-15 7:45 ` Alistair Francis 2021-06-15 7:45 ` Alistair Francis 2021-06-27 10:07 ` Frank Chang 2021-06-27 10:07 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 15:31 ` Frank Chang 2021-06-26 15:31 ` Frank Chang 2021-06-29 2:54 ` LIU Zhiwei 2021-06-29 2:54 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 15:39 ` Frank Chang 2021-06-27 15:39 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 12:08 ` Frank Chang 2021-06-27 12:08 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis 2021-04-19 23:30 ` Alistair Francis 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 6:26 ` Alistair Francis 2021-04-20 6:26 ` Alistair Francis 2021-04-20 7:20 ` LIU Zhiwei 2021-04-20 7:20 ` LIU Zhiwei 2021-04-22 0:21 ` Alistair Francis 2021-04-22 0:21 ` Alistair Francis 2021-06-27 15:55 ` Frank Chang 2021-06-27 15:55 ` Frank Chang
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