All of lore.kernel.org
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	wxy194768@alibaba-inc.com
Subject: Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
Date: Tue, 29 Jun 2021 10:50:15 +0800	[thread overview]
Message-ID: <9ff6e3f9-58ff-7a9b-2678-486d0f3b9cdf@c-sky.com> (raw)
In-Reply-To: <CANzO1D0Mxg6-AfPYb36=e4EebcSNF=u+yM5c=L+chLNq-n3xKw@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2297 bytes --]


On 2021/6/26 下午11:20, Frank Chang wrote:
> LIU Zhiwei <zhiwei_liu@c-sky.com <mailto:zhiwei_liu@c-sky.com>> 於 
> 2021年4月9日 週五 下午3:57寫道:
>
>
>     +
>     +/*
>     + * riscv_clic_create:
>     + *
>     + * @addr: base address of M-Mode CLIC memory-mapped registers
>     + * @prv_s: have smode region
>     + * @prv_u: have umode region
>     + * @num_harts: number of CPU harts
>     + * @num_sources: number of interrupts supporting by each aperture
>     + * @clicintctlbits: bits are actually implemented in the
>     clicintctl registers
>     + * @version: clic version, such as "v0.9"
>     + *
>     + * Returns: the device object
>     + */
>     +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u,
>     +                               uint32_t num_harts, uint32_t
>     num_sources,
>     +                               uint8_t clicintctlbits,
>     +                               const char *version)
>     +{
>     +    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC);
>     +
>     +    assert(num_sources <= 4096);
>     +    assert(num_harts <= 1024);
>     +    assert(clicintctlbits <= 8);
>     +    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9"));
>     +
>     +    qdev_prop_set_bit(dev, "prv-s", prv_s);
>     +    qdev_prop_set_bit(dev, "prv-u", prv_u);
>     +    qdev_prop_set_uint32(dev, "num-harts", num_harts);
>     +    qdev_prop_set_uint32(dev, "num-sources", num_sources);
>     +    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits);
>     +    qdev_prop_set_uint64(dev, "mclicbase", addr);
>
>
> According to spec:
>   Since the CLIC memory map must be aligned at a 4KiB boundary,
>   the mclicbase CSR has its 12 least-significant bits hardwired to zero.
>   It is used to inform software about the location of CLIC memory 
> mappped registers.
>
> I think it's better to add another addr check to ensure it's 4KiB aligned.
>
Agree.

Thanks,
Zhiwei

> Thanks,
> Frank Chang
>
>     +    qdev_prop_set_string(dev, "version", version);
>     +
>     +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>     +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
>     +    return dev;
>     +}
>     +
>

[-- Attachment #2: Type: text/html, Size: 4322 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	wxy194768@alibaba-inc.com
Subject: Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
Date: Tue, 29 Jun 2021 10:50:15 +0800	[thread overview]
Message-ID: <9ff6e3f9-58ff-7a9b-2678-486d0f3b9cdf@c-sky.com> (raw)
In-Reply-To: <CANzO1D0Mxg6-AfPYb36=e4EebcSNF=u+yM5c=L+chLNq-n3xKw@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2297 bytes --]


On 2021/6/26 下午11:20, Frank Chang wrote:
> LIU Zhiwei <zhiwei_liu@c-sky.com <mailto:zhiwei_liu@c-sky.com>> 於 
> 2021年4月9日 週五 下午3:57寫道:
>
>
>     +
>     +/*
>     + * riscv_clic_create:
>     + *
>     + * @addr: base address of M-Mode CLIC memory-mapped registers
>     + * @prv_s: have smode region
>     + * @prv_u: have umode region
>     + * @num_harts: number of CPU harts
>     + * @num_sources: number of interrupts supporting by each aperture
>     + * @clicintctlbits: bits are actually implemented in the
>     clicintctl registers
>     + * @version: clic version, such as "v0.9"
>     + *
>     + * Returns: the device object
>     + */
>     +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u,
>     +                               uint32_t num_harts, uint32_t
>     num_sources,
>     +                               uint8_t clicintctlbits,
>     +                               const char *version)
>     +{
>     +    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC);
>     +
>     +    assert(num_sources <= 4096);
>     +    assert(num_harts <= 1024);
>     +    assert(clicintctlbits <= 8);
>     +    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9"));
>     +
>     +    qdev_prop_set_bit(dev, "prv-s", prv_s);
>     +    qdev_prop_set_bit(dev, "prv-u", prv_u);
>     +    qdev_prop_set_uint32(dev, "num-harts", num_harts);
>     +    qdev_prop_set_uint32(dev, "num-sources", num_sources);
>     +    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits);
>     +    qdev_prop_set_uint64(dev, "mclicbase", addr);
>
>
> According to spec:
>   Since the CLIC memory map must be aligned at a 4KiB boundary,
>   the mclicbase CSR has its 12 least-significant bits hardwired to zero.
>   It is used to inform software about the location of CLIC memory 
> mappped registers.
>
> I think it's better to add another addr check to ensure it's 4KiB aligned.
>
Agree.

Thanks,
Zhiwei

> Thanks,
> Frank Chang
>
>     +    qdev_prop_set_string(dev, "version", version);
>     +
>     +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>     +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
>     +    return dev;
>     +}
>     +
>

[-- Attachment #2: Type: text/html, Size: 4322 bytes --]

  reply	other threads:[~2021-06-29  2:52 UTC|newest]

Thread overview: 162+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09  7:48 ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:23   ` Alistair Francis
2021-04-19 23:23     ` Alistair Francis
2021-04-20  0:49     ` LIU Zhiwei
2021-04-20  0:49       ` LIU Zhiwei
2021-07-01  8:45       ` Frank Chang
2021-07-01  8:45         ` Frank Chang
2021-07-01  9:38         ` LIU Zhiwei
2021-07-01  9:38           ` LIU Zhiwei
2021-07-02  5:38         ` Alistair Francis
2021-07-02  5:38           ` Alistair Francis
2021-07-02  6:09           ` LIU Zhiwei
2021-07-02  6:09             ` LIU Zhiwei
2021-07-02  7:16             ` Alistair Francis
2021-07-02  7:16               ` Alistair Francis
2021-09-28  8:10               ` Frank Chang
2021-09-28  8:10                 ` Frank Chang
2021-09-29  3:55                 ` Alistair Francis
2021-09-29  3:55                   ` Alistair Francis
2021-04-09  7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 17:23   ` Frank Chang
2021-06-26 17:23     ` Frank Chang
2021-06-27  8:23     ` Frank Chang
2021-06-27  8:23       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:25   ` Alistair Francis
2021-04-19 23:25     ` Alistair Francis
2021-04-20  0:57     ` LIU Zhiwei
2021-04-20  0:57       ` LIU Zhiwei
2021-04-22  0:16       ` Alistair Francis
2021-04-22  0:16         ` Alistair Francis
2021-06-13 10:10   ` Frank Chang
2021-06-13 10:10     ` Frank Chang
2021-06-16  2:56     ` LIU Zhiwei
2021-06-16  2:56       ` LIU Zhiwei
2021-06-26 12:56       ` Frank Chang
2021-06-26 12:56         ` Frank Chang
2021-06-28  7:15         ` LIU Zhiwei
2021-06-28  7:15           ` LIU Zhiwei
2021-06-28  7:23           ` Frank Chang
2021-06-28  7:23             ` Frank Chang
2021-06-28  7:39             ` LIU Zhiwei
2021-06-28  7:39               ` LIU Zhiwei
2021-06-28  7:49               ` Frank Chang
2021-06-28  7:49                 ` Frank Chang
2021-06-28  8:01                 ` LIU Zhiwei
2021-06-28  8:01                   ` LIU Zhiwei
2021-06-28  8:07                   ` Frank Chang
2021-06-28  8:07                     ` Frank Chang
2021-06-28  8:11                     ` LIU Zhiwei
2021-06-28  8:11                       ` LIU Zhiwei
2021-06-28  8:19                       ` Frank Chang
2021-06-28  8:19                         ` Frank Chang
2021-06-28  8:43                         ` LIU Zhiwei
2021-06-28  8:43                           ` LIU Zhiwei
2021-06-28  9:11                           ` Frank Chang
2021-06-28  9:11                             ` Frank Chang
2021-06-26 15:03   ` Frank Chang
2021-06-26 15:03     ` Frank Chang
2021-06-26 15:26     ` Frank Chang
2021-06-26 15:26       ` Frank Chang
2021-06-29  2:52       ` LIU Zhiwei
2021-06-29  2:52         ` LIU Zhiwei
2021-06-29  2:43     ` LIU Zhiwei
2021-06-29  2:43       ` LIU Zhiwei
2021-06-30  5:37       ` Frank Chang
2021-06-30  5:37         ` Frank Chang
2021-06-26 15:20   ` Frank Chang
2021-06-26 15:20     ` Frank Chang
2021-06-29  2:50     ` LIU Zhiwei [this message]
2021-06-29  2:50       ` LIU Zhiwei
2021-06-26 17:15   ` Frank Chang
2021-06-26 17:15     ` Frank Chang
2021-06-26 17:19     ` Frank Chang
2021-06-26 17:19       ` Frank Chang
2021-06-28 10:16   ` Frank Chang
2021-06-28 10:16     ` Frank Chang
2021-06-28 12:56     ` LIU Zhiwei
2021-06-28 12:56       ` LIU Zhiwei
2021-06-28 14:30       ` Frank Chang
2021-06-28 14:30         ` Frank Chang
2021-06-28 21:36         ` LIU Zhiwei
2021-06-28 21:36           ` LIU Zhiwei
2021-06-28 10:24   ` Frank Chang
2021-06-28 10:24     ` Frank Chang
2021-06-28 10:48     ` LIU Zhiwei
2021-06-28 10:48       ` LIU Zhiwei
2021-07-13  6:53   ` Frank Chang
2021-07-13  6:53     ` Frank Chang
2021-07-13  6:57     ` Frank Chang
2021-07-13  6:57       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:50   ` Frank Chang
2021-06-27  6:50     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:45   ` Frank Chang
2021-06-27  6:45     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:59   ` Frank Chang
2021-06-27  8:59     ` Frank Chang
2021-07-10 15:04   ` Frank Chang
2021-07-10 15:04     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:33   ` Frank Chang
2021-06-27  8:33     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-11  8:15   ` Frank Chang
2021-06-11  8:15     ` Frank Chang
2021-06-11  8:30     ` LIU Zhiwei
2021-06-11  8:30       ` LIU Zhiwei
2021-06-11  8:42       ` Frank Chang
2021-06-11  8:42         ` Frank Chang
2021-06-11  8:56         ` LIU Zhiwei
2021-06-11  8:56           ` LIU Zhiwei
2021-06-11  9:07           ` Frank Chang
2021-06-11  9:07             ` Frank Chang
2021-06-11  9:26             ` LIU Zhiwei
2021-06-11  9:26               ` LIU Zhiwei
2021-06-15  7:45             ` Alistair Francis
2021-06-15  7:45               ` Alistair Francis
2021-06-27 10:07   ` Frank Chang
2021-06-27 10:07     ` Frank Chang
2021-07-10 14:59   ` Frank Chang
2021-07-10 14:59     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 15:31   ` Frank Chang
2021-06-26 15:31     ` Frank Chang
2021-06-29  2:54     ` LIU Zhiwei
2021-06-29  2:54       ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 15:39   ` Frank Chang
2021-06-27 15:39     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 12:08   ` Frank Chang
2021-06-27 12:08     ` Frank Chang
2021-07-13  7:15   ` Frank Chang
2021-07-13  7:15     ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30   ` Alistair Francis
2021-04-20  1:44   ` LIU Zhiwei
2021-04-20  1:44     ` LIU Zhiwei
2021-04-20  6:26     ` Alistair Francis
2021-04-20  6:26       ` Alistair Francis
2021-04-20  7:20       ` LIU Zhiwei
2021-04-20  7:20         ` LIU Zhiwei
2021-04-22  0:21         ` Alistair Francis
2021-04-22  0:21           ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55   ` Frank Chang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9ff6e3f9-58ff-7a9b-2678-486d0f3b9cdf@c-sky.com \
    --to=zhiwei_liu@c-sky.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=frank.chang@sifive.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=wxy194768@alibaba-inc.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.