From: Frank Chang <frank.chang@sifive.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wxy194768@alibaba-inc.com Subject: Re: [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode Date: Sun, 27 Jun 2021 16:33:26 +0800 [thread overview] Message-ID: <CANzO1D3=c3PqA5VG=ORM3KsddDcFLMqCWZ3azpShXFsaBgXtaA@mail.gmail.com> (raw) In-Reply-To: <20210409074857.166082-8-zhiwei_liu@c-sky.com> [-- Attachment #1: Type: text/plain, Size: 4226 bytes --] LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道: > The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table, > aligned on a 64-byte or greater power-of-two boundary. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_bits.h | 2 ++ > target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ > 3 files changed, 32 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 9e389d7bbf..b5fd796f98 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -173,11 +173,13 @@ struct CPURISCVState { > target_ulong medeleg; > > target_ulong stvec; > + target_ulong stvt; /* clic-spec */ > target_ulong sepc; > target_ulong scause; > target_ulong sintthresh; /* clic-spec */ > > target_ulong mtvec; > + target_ulong mtvt; /* clic-spec */ > target_ulong mepc; > target_ulong mcause; > target_ulong mtval; /* since: priv-1.10.0 */ > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 9447801d22..7922097776 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -149,6 +149,7 @@ > #define CSR_MIE 0x304 > #define CSR_MTVEC 0x305 > #define CSR_MCOUNTEREN 0x306 > +#define CSR_MTVT 0x307 /* clic-spec-draft */ > > /* 32-bit only */ > #define CSR_MSTATUSH 0x310 > @@ -178,6 +179,7 @@ > #define CSR_SIE 0x104 > #define CSR_STVEC 0x105 > #define CSR_SCOUNTEREN 0x106 > +#define CSR_STVT 0x107 /* clic-spec-draft */ > > /* Supervisor Trap Handling */ > #define CSR_SSCRATCH 0x140 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 39ff72041a..e12222b77f 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -667,6 +667,18 @@ static int write_mcounteren(CPURISCVState *env, int > csrno, target_ulong val) > return 0; > } > > +static int read_mtvt(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->mtvt; > + return 0; > +} > + > +static int write_mtvt(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->mtvt = val & ~((1ULL << 6) - 1); > mtvt CSR has additional minimum alignment restriction in v0.8 CLIC spec[1]: 2^ceiling(log2(N)) x 4 bytes, where N is the maximum number of interrupt sources. > + return 0; > +} > + > /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong > *val) > { > @@ -876,6 +888,18 @@ static int write_scounteren(CPURISCVState *env, int > csrno, target_ulong val) > return 0; > } > > +static int read_stvt(CPURISCVState *env, int csrno, target_ulong *val) stvt CSR seems not to exist in v0.8 CLIC spec[1]. [1] https://github.com/riscv/riscv-fast-interrupt/blob/74f86c3858/clic.adoc Regards, Frank Chang > +{ > + *val = env->stvt; > + return 0; > +} > + > +static int write_stvt(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->stvt = val & ~((1ULL << 6) - 1); > + return 0; > +} > + > /* Supervisor Trap Handling */ > static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) > { > @@ -1730,6 +1754,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, > > /* Machine Mode Core Level Interrupt Controller */ > + [CSR_MTVT] = { "mtvt", clic, read_mtvt, write_mtvt }, > [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, > [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh, > write_mintthresh }, > @@ -1739,5 +1764,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh, > write_sintthresh }, > > + /* Supervisor Mode Core Level Interrupt Controller */ > + [CSR_STVT] = { "stvt", clic, read_stvt, write_stvt }, > + > #endif /* !CONFIG_USER_ONLY */ > }; > -- > 2.25.1 > > > [-- Attachment #2: Type: text/html, Size: 5685 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Frank Chang <frank.chang@sifive.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, wxy194768@alibaba-inc.com Subject: Re: [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode Date: Sun, 27 Jun 2021 16:33:26 +0800 [thread overview] Message-ID: <CANzO1D3=c3PqA5VG=ORM3KsddDcFLMqCWZ3azpShXFsaBgXtaA@mail.gmail.com> (raw) In-Reply-To: <20210409074857.166082-8-zhiwei_liu@c-sky.com> [-- Attachment #1: Type: text/plain, Size: 4226 bytes --] LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道: > The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table, > aligned on a 64-byte or greater power-of-two boundary. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_bits.h | 2 ++ > target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ > 3 files changed, 32 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 9e389d7bbf..b5fd796f98 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -173,11 +173,13 @@ struct CPURISCVState { > target_ulong medeleg; > > target_ulong stvec; > + target_ulong stvt; /* clic-spec */ > target_ulong sepc; > target_ulong scause; > target_ulong sintthresh; /* clic-spec */ > > target_ulong mtvec; > + target_ulong mtvt; /* clic-spec */ > target_ulong mepc; > target_ulong mcause; > target_ulong mtval; /* since: priv-1.10.0 */ > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 9447801d22..7922097776 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -149,6 +149,7 @@ > #define CSR_MIE 0x304 > #define CSR_MTVEC 0x305 > #define CSR_MCOUNTEREN 0x306 > +#define CSR_MTVT 0x307 /* clic-spec-draft */ > > /* 32-bit only */ > #define CSR_MSTATUSH 0x310 > @@ -178,6 +179,7 @@ > #define CSR_SIE 0x104 > #define CSR_STVEC 0x105 > #define CSR_SCOUNTEREN 0x106 > +#define CSR_STVT 0x107 /* clic-spec-draft */ > > /* Supervisor Trap Handling */ > #define CSR_SSCRATCH 0x140 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 39ff72041a..e12222b77f 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -667,6 +667,18 @@ static int write_mcounteren(CPURISCVState *env, int > csrno, target_ulong val) > return 0; > } > > +static int read_mtvt(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->mtvt; > + return 0; > +} > + > +static int write_mtvt(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->mtvt = val & ~((1ULL << 6) - 1); > mtvt CSR has additional minimum alignment restriction in v0.8 CLIC spec[1]: 2^ceiling(log2(N)) x 4 bytes, where N is the maximum number of interrupt sources. > + return 0; > +} > + > /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong > *val) > { > @@ -876,6 +888,18 @@ static int write_scounteren(CPURISCVState *env, int > csrno, target_ulong val) > return 0; > } > > +static int read_stvt(CPURISCVState *env, int csrno, target_ulong *val) stvt CSR seems not to exist in v0.8 CLIC spec[1]. [1] https://github.com/riscv/riscv-fast-interrupt/blob/74f86c3858/clic.adoc Regards, Frank Chang > +{ > + *val = env->stvt; > + return 0; > +} > + > +static int write_stvt(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->stvt = val & ~((1ULL << 6) - 1); > + return 0; > +} > + > /* Supervisor Trap Handling */ > static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) > { > @@ -1730,6 +1754,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, > > /* Machine Mode Core Level Interrupt Controller */ > + [CSR_MTVT] = { "mtvt", clic, read_mtvt, write_mtvt }, > [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, > [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh, > write_mintthresh }, > @@ -1739,5 +1764,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh, > write_sintthresh }, > > + /* Supervisor Mode Core Level Interrupt Controller */ > + [CSR_STVT] = { "stvt", clic, read_stvt, write_stvt }, > + > #endif /* !CONFIG_USER_ONLY */ > }; > -- > 2.25.1 > > > [-- Attachment #2: Type: text/html, Size: 5685 bytes --]
next prev parent reply other threads:[~2021-06-27 8:35 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-09 7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:23 ` Alistair Francis 2021-04-19 23:23 ` Alistair Francis 2021-04-20 0:49 ` LIU Zhiwei 2021-04-20 0:49 ` LIU Zhiwei 2021-07-01 8:45 ` Frank Chang 2021-07-01 8:45 ` Frank Chang 2021-07-01 9:38 ` LIU Zhiwei 2021-07-01 9:38 ` LIU Zhiwei 2021-07-02 5:38 ` Alistair Francis 2021-07-02 5:38 ` Alistair Francis 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 6:09 ` LIU Zhiwei 2021-07-02 7:16 ` Alistair Francis 2021-07-02 7:16 ` Alistair Francis 2021-09-28 8:10 ` Frank Chang 2021-09-28 8:10 ` Frank Chang 2021-09-29 3:55 ` Alistair Francis 2021-09-29 3:55 ` Alistair Francis 2021-04-09 7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 17:23 ` Frank Chang 2021-06-26 17:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-06-27 8:23 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-04-19 23:25 ` Alistair Francis 2021-04-19 23:25 ` Alistair Francis 2021-04-20 0:57 ` LIU Zhiwei 2021-04-20 0:57 ` LIU Zhiwei 2021-04-22 0:16 ` Alistair Francis 2021-04-22 0:16 ` Alistair Francis 2021-06-13 10:10 ` Frank Chang 2021-06-13 10:10 ` Frank Chang 2021-06-16 2:56 ` LIU Zhiwei 2021-06-16 2:56 ` LIU Zhiwei 2021-06-26 12:56 ` Frank Chang 2021-06-26 12:56 ` Frank Chang 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:15 ` LIU Zhiwei 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:23 ` Frank Chang 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:39 ` LIU Zhiwei 2021-06-28 7:49 ` Frank Chang 2021-06-28 7:49 ` Frank Chang 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:01 ` LIU Zhiwei 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:07 ` Frank Chang 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:11 ` LIU Zhiwei 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:19 ` Frank Chang 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 8:43 ` LIU Zhiwei 2021-06-28 9:11 ` Frank Chang 2021-06-28 9:11 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:03 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-26 15:26 ` Frank Chang 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:52 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-29 2:43 ` LIU Zhiwei 2021-06-30 5:37 ` Frank Chang 2021-06-30 5:37 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-26 15:20 ` Frank Chang 2021-06-29 2:50 ` LIU Zhiwei 2021-06-29 2:50 ` LIU Zhiwei 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:15 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-26 17:19 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 10:16 ` Frank Chang 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 12:56 ` LIU Zhiwei 2021-06-28 14:30 ` Frank Chang 2021-06-28 14:30 ` Frank Chang 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 21:36 ` LIU Zhiwei 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:24 ` Frank Chang 2021-06-28 10:48 ` LIU Zhiwei 2021-06-28 10:48 ` LIU Zhiwei 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:53 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-07-13 6:57 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:50 ` Frank Chang 2021-06-27 6:50 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 6:45 ` Frank Chang 2021-06-27 6:45 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:59 ` Frank Chang 2021-06-27 8:59 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-07-10 15:04 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 8:33 ` Frank Chang [this message] 2021-06-27 8:33 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:15 ` Frank Chang 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:30 ` LIU Zhiwei 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:42 ` Frank Chang 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 8:56 ` LIU Zhiwei 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:07 ` Frank Chang 2021-06-11 9:26 ` LIU Zhiwei 2021-06-11 9:26 ` LIU Zhiwei 2021-06-15 7:45 ` Alistair Francis 2021-06-15 7:45 ` Alistair Francis 2021-06-27 10:07 ` Frank Chang 2021-06-27 10:07 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-07-10 14:59 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-26 15:31 ` Frank Chang 2021-06-26 15:31 ` Frank Chang 2021-06-29 2:54 ` LIU Zhiwei 2021-06-29 2:54 ` LIU Zhiwei 2021-04-09 7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 15:39 ` Frank Chang 2021-06-27 15:39 ` Frank Chang 2021-04-09 7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei 2021-04-09 7:48 ` LIU Zhiwei 2021-06-27 12:08 ` Frank Chang 2021-06-27 12:08 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-07-13 7:15 ` Frank Chang 2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis 2021-04-19 23:30 ` Alistair Francis 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 1:44 ` LIU Zhiwei 2021-04-20 6:26 ` Alistair Francis 2021-04-20 6:26 ` Alistair Francis 2021-04-20 7:20 ` LIU Zhiwei 2021-04-20 7:20 ` LIU Zhiwei 2021-04-22 0:21 ` Alistair Francis 2021-04-22 0:21 ` Alistair Francis 2021-06-27 15:55 ` Frank Chang 2021-06-27 15:55 ` Frank Chang
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